JPH059966B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transistor circuit, and in particular to an insulated gate field effect transistor (hereinafter referred to as
This relates to decoder circuits such as memory circuits using IGFETs.

There are various types of memory circuits using IGFETs, and various types are also used as decoder circuits, but one of the basic types is the logic circuit part of the decoder and the decoded signal. A typical circuit is shown in FIG. 1, which includes a buffer section for amplifying the impedance. The operating waveforms are shown in FIG. To explain the decoder circuit using these drawings, in the drawing, transistors Q1, Q2, Q3, and Q4 constitute the logic circuit part of the decoder, and transistor Q
2, Q3, Q4 gate signals Ai, Ai+1, Ai+
If all of the transistor Q1
A timing signal P1 is input to the gate terminal of the gate terminal, and the gate signals Ai, Ai+1, and Ai+2 are also provided with timing, and these signals are output while the signal P1 is at "1" level.
In the case of a dynamic type in which point a is precharged by resetting Ai, Ai+1, and Ai+2 to the "0" level, and then a desired signal is given to signals Ai to Ai+2 to select point a and perform decoder operation. There are many.

Transistor Q5 is a gate transistor that connects the logic circuit section of the decoder and the buffer circuit section consisting of transistors Q7 and Q6, and when point a is selected after precharge T _p , that is, signal Ai
When both ~Ai+2 are at the "0" level, at the rise of the timing φ2, the capacitor _C1 functions so that the point b becomes a higher level "1" than the point a. Therefore, a high level of approximately _φ2 is generated at the output _d1 , and the "1" level is surely generated. At this time, the rising voltage ΔV _b at point b due to the action of the putot strap capacitor C ₁ is ΔV _b = C _b /C + C _b · ΔV _d1 , where C is the size of the capacitor C ₁ and C _b is b. It is the size of the capacitance unique to a point. ΔV _d1 is ΔV _b
is the rising voltage of the output output _d1 due to In this case, if there is no gate effect by transistor Q5, the rising voltage ΔV _b ′ at point b will be ΔV _b ′=C/C+C _a +C _b・ΔV _d1 , which is the size of the capacitance unique to point a. The lift can be weakened by C _a . Therefore, only a low "1" level can be obtained at the output _d1 . Note that the chain line in FIG. 2 indicates the case where point a is not selected.

On the other hand, in a so-called 3.5-wire 3-transistor memory cell that consists of three transistors and has only one digital line, the address signal lines are the RA line for reading and the WA line for writing.
Requires two wires. Moreover, since the RA and WA lines are driven at different timings φ2 and φ3, two gate transistors are also required to separate the decoder logic circuit section and the buffer section.

The circuit in Figure 3 has 3.5 memory cells as described above.
This is an example of a decoder circuit in the case of a linear three-transistor type, and FIG. 4 is a waveform diagram for explaining its operation.

In the figure, the gate terminals of transistors Q5 and Q8 are connected to the power supply voltage V _DD , and the precharge timing P1 often reaches its highest level at the power supply voltage V _DD . Moreover, when the final level at timing P1 is _VDD , it takes a long time to reach the final value, and it is normal that the voltage does not reach the power supply voltage within the limited precharge time. At this time, the level at point a becomes a value lower than the level at P1 by the threshold voltage _VTH .

In order for transistors Q5 and Q8 to turn off,
It is necessary for point a to be a value lower than the power supply voltage V _DD by the threshold voltage V _TH , and the level at point a does not reach the power supply voltage V _DD as described above.
A value that is V _TH below the level of V _DD −V _TH
If the value is smaller, then the transistor Q
5, Q8 is in the on state even if it is a little.

In this way, when timing φ2 is added while transistor Q5 is on, the level at point b1 is
Due to the function of the capacitor C1, the level does not increase as calculated above, and the level at point b1 decreases by the amount that increases the level at point a to V _DD -V _TH .
Therefore, the signal of the output R _A line is sufficiently high “1”
It cannot be a level. In FIG. 4, the broken line in the waveform at point b1 is the waveform when point a has been sufficiently precharged to V _DD -V _TH .

FIG. 5 is one of the reference examples of the present invention, and FIG. 6 is an operation waveform diagram thereof. In the figure, a transistor Q5 connects the decoder logic circuit section and the buffer section,
The level at point f of the gate terminal of Q8 can be varied, and point f rises and falls in response to the movement of point a in the logic circuit section of the decoder.

That is, due to timing P1 being at a high level,
When point a rises, the level of point f also rises along with point a, helping precharge points b1 and b2. However, when the precharge period ends and the decoder selection period begins, the point a of all but one decoder (not shown) falls to a low level (dotted line in FIG. 6). At this time, since point f is commonly connected to all decoder circuits, the level of point f is lowered by being subtracted by point a of the other unselected decoder circuits. At this time, point a of the selected decoder maintains a high level (solid line in Figure 6), but since the level of point f remains low, the gate transistor Q5 of the selected decoder circuit is in an off state. becomes. Therefore, when φ2 is activated and becomes high level next time, the charge charged in the capacitor _C1 serves to raise the voltage at the gate b1 of the transistor Q6, and does not escape to any other place. Therefore, a sufficiently high level can be obtained at high speed at the output d1.
In this case, the level change at point f need not be large; for example, during the precharge period at point a, transistor Q5 is on, and during the period when a decoder is selected, the gate of the selected decoder is turned on. It is sufficient to have a level that can supply the gate voltage such that the transistor Q5 is in an off state. At this time, the gate transistors of other decoder circuits not selected are in a conductive state, but the conductive state is of course weaker than that during the precharge period.

In short, each gate transistor is connected to a signal source that can rise and fall according to the level of the unselected output a of the decoder circuit.

There are various methods to raise or lower the level of point f, but in the circuit shown in Figure 5, capacitive coupling C3, C is used between point f and point a.
3' is used. In this case, it is possible to actively insert a capacitor between the point f and the point a, but in reality, the transistors Q5 and Q8
The purpose can also be achieved by using capacitive coupling between the gate and the source terminal, drain terminal, gate channel, etc.

Using the circuit shown in Figure 5, the low level at point f is
It will never fall below a level that is V _TH below V _DD . However, as a method to obtain the level of point f,
There are other possibilities as well. In the configuration shown in FIG. 5, the potential at the gate of transistor Q5 does not become lower than "V _DD -V _TH ", which is insufficient in that the buffer circuit portion and the logic circuit portion are reliably cut off during buffer circuit operation. In addition, the rise in gate potential when transmitting the level at point a to point b is sufficient because point f is connected to many other decoder logic circuit outputs and the selected decoder is only one of them. It is also difficult to increase the potential to a level higher than the power supply potential.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and realize an improved transistor circuit by reliably controlling conduction between the output of the logic circuit section and the input of the buffer section.

The present invention will be explained below using FIG.

FIG. 7 shows one embodiment of the present invention. The main parts related to the decoder logic circuit section and buffer section are the fifth section.
Although the configuration is almost the same as that shown in the figure, the fall of the point f is ensured by synchronizing with φ2 by the transistor Q12. That is, the first role of the transistor Q5 is to quickly transmit the operation results of the logic circuit portion to the buffer circuit at the subsequent stage, and it is desirable that the impedance of the transistor Q5 be as low as possible. For this purpose,
It is desirable to make the transistor Q5 as large as possible or to make the potential of the gate electrode of the transistor Q5 as high as possible (in the case of N channel).
However, it is difficult to increase Q5 in circuits arranged in a narrow pitch within a memory chip, such as a decoder circuit.

The second role of the transistor Q5 is to reliably cut off the buffer circuit portion and the logic circuit portion during the buffer circuit operation. For this purpose, the potential of the gate electrode of transistor Q5 is required to be sufficiently low.

As described above, in order to reliably perform the first and second roles, in the present invention, a potential higher than the power supply voltage is applied to the gate electrode of the transistor Q5 when the logic circuit is operating, and a sufficiently lower potential is applied when the buffer circuit is operating. giving.

For the above example, the N channel
Although an IGFET is used, it goes without saying that a P-channel IGFET may also be used.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional decoder circuit,
Fig. 2 is an operating waveform diagram of the circuit in Fig. 1, Fig. 3 is a diagram showing another example of a conventional decoder circuit, Fig. 4 is an operating waveform diagram of the circuit in Fig. 3, and Fig. 5 is a diagram of the present invention. FIG. 6 is a diagram showing operating waveforms of the circuit in FIG. 5, and FIG. 7 is a circuit diagram showing an embodiment of the present invention. In the figure, Q1 to Q4 are transistors that constitute the decoder logic circuit section, and Q5 and Q8 are gate transistors.
Transistors Q6 and Q9 are decoder buffer transistors, and C1 and C2 are pulley strap capacitors.

Claims (1)

[Claims] 1 A first insulated gate field effect transistor whose drain (or source) is connected to an input terminal and whose source (or drain) receives an output; whose gate is connected to the output of the first transistor and whose drain (or source) ) a second insulated gate field effect transistor that outputs the first signal supplied to the source (or drain) to the source (or drain), and a control circuit that supplies the second signal to the gate of the first transistor, When the output of the first transistor is at a level that makes the second transistor conductive,
In the circuit for feeding back the output of the second transistor to the gate of the second transistor by means of a capacitance existing between the gate and the output of the second transistor, the control circuit controls each current between the power supplies. a load element and a third insulated gate field effect transistor connected in series, and boosting means connected to an intermediate connection point between the load element and the third transistor, the boosting means having one end connected to the third insulated gate field effect transistor; It has a capacitive element connected to the intermediate connection point and having the other end supplied with a third signal, and the third transistor is conductive when the first signal is generated and the second signal is at a low level. In the period before the first signal is generated, the third transistor is controlled to be non-conductive, and during this period, the third signal is increased to a value larger than the power supply potential. The second
A transistor circuit characterized in that it generates a signal.