JPH06100965B2 - Micro program controller - Google Patents

Description

The present invention relates to a micro program controller, and more particularly to a micro program controller most suitable for speeding up a microinstruction involving a branch.

[Description of Prior Art]

In the field of microcomputers, a microprogramming method in which various control timing information is stored in the control memory due to factors such as an increase in the capacity of the memory circuit and an improvement in the design technology of the logic circuit accompanying the progress of the integrated circuit technology. Is widely used, and detailed processing is realized by setting branch conditions of microflow and using conditional branch processing using these conditions in various places.

Among branch designations in a microprogram, there is one that designates execution of a corresponding microprogram flow at a bit position of "1" included in control data of 8 bits, 16 bits, or the like.

FIG. 5 shows an example of a conventional microprogram flow in which branch processing is designated by 8-bit control data. In this conventional example, as shown in FIG. 6, each bit of the 8-bit control data is set to the microprogram flow A, B, C, respectively.
It corresponds to D, E, F, G, H, and if one bit is in the set state, the microprogram flow corresponding to that bit is executed. That is, if the bit 0 is 1, the process A is executed, and if the bit 1 is 1, the process B is further executed. Therefore, when the 8-bit data is 11111111, A, B, C,
Executes all the processing of D, E, F, G, H, and when 00000000,
Does not execute any processing of A, B, C, D, E, F, G, and H.

FIG. 7 shows a block diagram of a conventional micro program control device for realizing this micro program flow.

The IR 102 is a register that holds an instruction code to be executed by this micro program control device, and an instruction code to be executed next is stored every time one instruction processing is completed under the control of an end micro order (hereinafter referred to as END) 104 described later. To be done.

The selector 100 is an address selector that selects either the contents of the IR 102 or the output of the micro ROM 101 itself as a read address of a control device (hereinafter referred to as a micro ROM) 101, which will be described later. At the timing of, the IR102 is selected, and thereafter, the output of the micro ROM 101 is selected. The selector 100 shifts to the next instruction processing in synchronization with the timing when one instruction processing is completed and the END 104 becomes active, and selects the first timing IR 102 again.

The micro ROM 101 is a control memory that holds timing information regarding a processing procedure unique to each instruction, and a read address is designated by the output of the select 100, and the output of the micro ROM 101 is used as it is as a micro order 111.
In addition, part of the output of the micro ROM 101 is
The read address information of 01 (hereinafter referred to as the next address) 106 is input to the selector 100 again.

The control data register 107 holds the control data of 8 bits in the conventional example and has a right shift function for 1 bit by the designation of the micro order 111. In this prior art example, the micro order for designating the right shift processing is not shown.

The least significant bit of the control data register 107 is control gate 1
Connected to 12.

The least significant bit of the next address 106 output from the micro ROM 101 and the branch order 113 output from the micro ROM 101 are connected to the control date 112, and the output of the control gate 112 is the least significant bit of the modified next address 106. Information is input to the selector 100.

FIG. 8 illustrates the address allocation of the processes A, B, C, D, E, F, G and H in the micro ROM 101 according to this embodiment.

The instruction data entry address contains the control data register
A check process of 107 least significant bits is set. As shown in the figure, the address location a0 whose least significant bit is 0 is right-shifted by 1 bit in the control data register 107, and the address location a1 whose least significant bit is 1 is the bit in the control data register 107. A micro flow for processing A corresponding to 0 is set, and in the following order,
1-bit right shift processing of the control data register 107 is performed for the address location b0 whose least significant bit is 0, and for processing B corresponding to bit 1 in the control data register 107 for the address location b1 whose least significant bit is 1. Microflow is set.

Next, the actual operation will be described with reference to the flowchart of FIG. 5 and the block of FIG.

However, in this conventional example, it is assumed that the necessary instruction code and 8-bit control data are stored in advance in the IR 102 and the control data register 107.

(1) Next address information 106a0 is output from the micro ROM 101 to determine whether the process A is executed. At the same time, the control gate 112 is enabled in synchronization with the timing at which the branch order 113 is activated, and confirmation processing is performed as to whether the least significant bit of the control data is 1 or 0. In the case of 0, since the control gate 112 logically ORs 0, the least significant bit remains 0, the address information a0 is input to the micro ROM 101, the process A is not executed, and the control data is right-shifted. Do. Further, the bit 1 of the 8-bit control data is moved to the lowermost position. In the case of 1, the least significant bit of the next address 106 is set by the control gate 112,
A1 is stored as the next address information 106 in the micro ROM 101.
Is input, the process moves to the execution of process A. Further, after the execution of the process A, the control data is right-shifted, and the bit 1 of the 8-bit control data is moved to the lowermost position.

(2) The branch order 113 is activated again, and it is confirmed whether the least significant bit of the right-shifted control data is 1 or 0 by the same method as (1). If zero, control gate 112
Since 0 is logically ORed by 0, the least significant bit remains 0 and the process B is not executed, the control data is right-shifted, and the bit 2 of the 8-bit control data is moved to the least significant. In the case of 1, the control gate 112 sets the least significant bit of the next address 106 to the set state, so that the processing B
Move on to. After the process B is executed, the control data is right-shifted, and the bit 2 of the 8-bit control data is moved to the lowermost position.

By repeating the above processing eight times, 8-bit control data is discriminated and the necessary microprogram flow is activated.

[Problems to be solved by the invention]

As described above, in the conventional micro program control device, the execution of each corresponding process is determined while checking the 8-bit control data bit by bit. That is, 8
Even if there is only one bit in the set state in the bit control data, all bits are checked one by one,
It causes a decrease in execution time.

In particular, when the processing time corresponding to each bit is relatively short, the check time of the control data in the total instruction processing becomes dominant, and the smaller the number of set bits in the control data is, the more the original data processing is performed. The ratio of the check time is higher than the time, which causes a large decrease in the overall processing efficiency.

[Purpose of the present invention]

An object of the present invention is to provide a micro program control device that solves the above drawbacks.

[Details of Differences from Prior Art of Invention]

A drawback of the conventional technique is that 8-bit control data is checked bit by bit to determine the execution of the corresponding processing. Therefore, the number of bits set in 8-bit control data is small. Even in that case, it was necessary to check all bits one by one.

The present invention is characterized by terminating the determination process for all bits and directly branching to the process corresponding to the bit position in the set state. Therefore, for example, when there are only two bits in the set state, Since the processing corresponding to each bit is executed to complete the series of instruction processing, the discrimination processing of all bits one by one becomes unnecessary, and a great improvement in the overall execution time is achieved.

[Means for solving problems]

A micro program control device according to the present invention relates to a micro program control device which reads a micro instruction from a control memory and processes an instruction, and stores branch information holding means for holding branch information of a microflow and contents of the branch information holding means. A branch information updating unit for updating is provided, and the read address of the control memory is designated by the content of the branch information holding unit in synchronization with a predetermined branch instruction output from the control memory, and at the same time, the branch is performed in synchronization with the predetermined branch instruction. A major feature is that the information updating means updates the contents of the branch information holding means.

[Embodiment 1] A first embodiment according to the present invention will be described with reference to FIG.

The selector 100 is a selector that selects either the content of the IR 102 as the read address of the micro ROM 101, the output of the micro ROM 101 itself, or the output of the micro address generation circuit 103 described later. In addition to selecting IR102, the indirect branch designation micro order (hereinafter referred to as IDB) 105
Is activated, the output of the micro address generation circuit 103 is selected. At other timings, the micro ROM1
Select the next address 106 which is 01 output.

The micro address generation circuit 103 includes a control data register 1
07 and logic gate group 108 are included.

Since the IR 102 and the micro ROM 101 have the same configuration as the conventional example, detailed description will be omitted.

Next, referring to FIG. 2, a more detailed block diagram of the micro address generation circuit 103 is shown.

The micro address generation circuit 103 includes a control data register 1
07 and logic gate group 108 are included, and the least significant bit set in control data register 107 can be cleared by the action of logic gate 108 in synchronization with the timing when IDB 105 becomes active.

The logic gate group 108 is a circuit that selects the bit on the most LSB side among the bits in the set state in the control data register 107, and is configured by the AND gate group 109.

In the control data register 107, the bit on the most LSB side among the bits in the set state is cleared under the control of the AND gate group 109 in synchronization with the timing when the IDB 105 becomes active.

FIG. 3 shows an example of a microprogram flow executed by the microprogram controller according to the present invention. In this embodiment, as in the conventional example, each bit of the 8-bit control data is a microprogram flow A, B, C, D, E, F, G, respectively.
Although it corresponds to H, it is not a method of determining the processing flow by discriminating the control data bit by bit, but directly branches to the processing flow corresponding to the bit in the set state.

Next, the operation will be described with reference to FIG. The IR 102 and the control data register 107 are assumed to store the instruction code and the control data in advance.

Control data register 1 in the micro address generation circuit 103
The logic bit 108 selects the least significant bit information in the set state from the control data set in 07. Subsequently, in synchronization with the timing when the IDB 105 becomes active, address information regarding instruction processing is input to the micro ROM 101 via the selector 100, and the processing corresponding to the least significant bit in the set state is activated.

At the same time, in synchronization with the timing when the IDB 105 becomes active, the least significant 1 bit in the set state in the control data register 107 in the micro address generation circuit 103 is cleared, and the least significant bit in the remaining set state bit group is cleared. One bit existing on the side is selected.

After completing the predetermined processing corresponding to the bit in the set state,
When the IDB 105 is activated again, the least significant 1 bit in the set state in the updated control data register 107 is selected and input as a read address to the micro ROM 101 via the selector 100,
The process corresponding to the next set bit is started.

At the same time, in synchronization with the same timing, the least significant 1 bit in the set state in the control data register in the micro address generation circuit 103 is cleared again and exists in the least significant side of the remaining set state bit group. 1 bit that is selected is in the selected state.

By repeating the above processing and clearing all the bits in the control data register 103, a series of instruction processing is completed. In addition, 00000 from the beginning in the control data register 103.
If 000 is set, the process immediately proceeds to the end processing.

Example-2 FIG. 4 shows a block diagram of Example-2.

The second embodiment has the same hardware configuration as that of the first embodiment except that the read address of the micro ROM 101 is designated by the micro program counter (hereinafter referred to as MPC) 110.

The MPC 110 selects the IR 102 in synchronization with the activation of the END 104 or the output of the micro address generation circuit 103 via the selector 100 in synchronization with the activation of the IDB 105, and the content is updated. . When both the END 104 and the IDB 105 are inactive, the MPC 110 increments the content each time execution of one microprogram step is completed.

Since the operation of the micro address generation circuit 103 is the same as that of the first embodiment, detailed description will be omitted.

In the second embodiment as well, it is not necessary to sequentially determine each bit for the bit determination, and the same effect as in the first embodiment can be obtained.

〔The invention's effect〕

As described above, in the microprogram controller according to the present invention, the execution of each corresponding process is not discriminated while checking the 8-bit control data bit by bit, as compared with the conventional microprogram controller. The process directly branches to the process corresponding to the bit that has been set. Therefore, even when the number of bits in the set state of 8-bit control data is small, the discrimination processing time resulting from the discrimination processing of the control bits can be reduced, and the total processing time can be greatly shortened.

In particular, even when the processing time corresponding to each bit is relatively short, the control data check time is not included at all, so even if the number of bits in the set state in the control data is small, the Only the data processing time is required, and the overall processing efficiency has been greatly improved, and the processing capacity can be greatly improved by adding a small amount of hardware, and the practical effect is extremely high.

[Brief description of drawings]

1 and 2 are block diagrams showing Embodiment-1 of the present invention, and FIG. 3 is a microprogram flow according to Embodiment-1 of the present invention. FIG. 4 is a block diagram showing an embodiment-2 of the present invention, and FIG. 5 is a microprogram flow in a conventional microprogram controller. FIG. 6 is a correspondence diagram between the control data and the processing actually executed. Figure 7 shows
The block diagram of the conventional micro program control apparatus. 8th
The figure is a conventional micro ROM address allocation diagram. 100 …… Selector, 101 …… Micro ROM, 102 …… IR, 10
3 ... Micro address generation circuit, 104 ... END signal, 105
... IDB signal, 106 ... next address, 107 ... control data register, 108 ... logic gate 109 ... AND gate group, 110 ... MPC, 112 ... control gate, 113 ... branch order.

Claims (1)

[Claims] 1. A plurality of first controls the execution of microinstructions.
Control information holding means for holding the control information and the second control information, control information detecting means for detecting and outputting the first control information located on the lowest side of the control information holding means, and the control information. A control memory for receiving the first control information on the lowermost side output from the detecting means and outputting the corresponding microinstruction, and the control information detecting means for storing the first control information on the lowermost side. Updating means for updating the first control information on the least significant side to the second control information and outputting the other first control information and second control information in response to the microinstruction when output And the control information detecting means detects and outputs the new first control information located on the lowest side of the updated control information holding means.