JPH06103169A - Read data prefetching mechanism for central arithmetic processor - Google Patents

Abstract

PURPOSE:To reduce the access frequency to a main storage and to improve the performance of a central arithmetic processor containing a cache by prefetching the read data based on the past access history. CONSTITUTION:An address monitoring part 9 is provided to decide the address continuity together with an address table 10 which stores the continuous addresses, a continuous address line 11 which is connected to the part 9 and the table 10, a priority control part 15 which controls the priority to leave the addresses in the table 10, a replacement request control part 16 which decides the reading destination of the read data and produced a request, and a red data buffer 17 which stores the data prefetched from a main storage 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read data prefetch mechanism for a central processing unit having a cache memory.

[0002]

2. Description of the Related Art A central processing unit having a conventional cache memory increases the cache hit rate by increasing the capacity of the cache memory,
There is a method of predicting that the next block on the address of the accessed block will be accessed by the CPU and prefetching it in the cache memory in advance.

[0003]

In the prior art, the performance was improved by increasing the cache hit rate and reducing the frequency of read access to the main storage device as described above, but the large capacity of the cache memory was used. There is always a problem with cost. In addition, the method of fetching the next block at the address of the block that has been cache-accessed into the cache memory in advance has a high probability that a read access will occur in the next block due to the locality of the main memory, but the next block If the read access does not occur, data that may have been valid may be replaced by replacement, which may rather deteriorate the performance.

Therefore, an object of the present invention is to provide a read data based on the past read access history without increasing the capacity of the cache memory and blindly fetching the next block into the cache memory in advance. By prefetching and storing in the buffer, the frequency of read access to the main storage device is reduced.

[0005]

SUMMARY OF THE INVENTION The present invention provides a read data prefetch for a central processing unit having a main memory and a cache memory connected to a main memory bus composed of address, data lines and control lines. ) An address monitoring unit that determines that the main memory read access accesses an address that is continuous with the address of the previous main memory read access and that the transfer unit block of the cache memory spans two or more blocks. B) An address register for storing a series of addresses determined by the address monitoring unit, a valid bit indicating the validity of the series of addresses, and a priority bit indicating a priority order for leaving the series of addresses in the address register. And an address table composed of (D) CPU LSI main memory read access is accepted, the read destination of read data is determined from the information of the address table, and ON / OFF of the valid bid of the address table is performed. And (E) when the read data corresponding to the series of addresses stored in the address register of the address table is read from the main storage device by burst read, And a read data buffer for storing.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is an address line for transmitting an address, 2 is a data line for transmitting data, 3 is a control line for transmitting main memory bus control information, for example, a transfer start signal, a response signal, a ready signal, a transfer end signal, etc. And the main memory bus 4 is composed of these. And the main memory 5,
The central processing unit 6 is connected to the main memory bus 4.

Next, the components of the central processing unit 6 will be described. Reference numeral 7 is a CPU LSI, and 8 is a cache memory. An address monitoring unit 9 is connected to the address line. 10 is an address table, which is a continuous address line 1
1 is connected to the address monitoring unit. The address table 10 includes priority bits 12, valid bids 13, and address registers 14. 1
Reference numeral 5 is a priority management unit, 16 is a replacement request management unit, and 17 is a read data buffer. Reference numeral 18 is a register number bit for storing the register number of the address register 14 in order to make the read data of the read data buffer 17 correspond to the address of the address register 14. 19 is a FIFO address table 10
, The top address register 20 in which the oldest address is stored is a table address register 20 in which the newest address is stored. Reference numeral 21 is mishit information indicating that a cache mishit has occurred.

FIG. 2 is a block diagram showing the details of the address monitoring unit. Reference numeral 22 is an A register for holding the address of the main memory read access one time before, and reference numeral 23 is a B register for fetching the address of the main memory read access this time.
24 is a C address buffer for temporarily storing addresses that may be sent to the address table 10, and 25 is B
It is an address comparator that compares the address of the register and the address of the A register and determines whether or not they are continuous and whether or not they span two blocks. 26 is a continuous flag indicating that the address is a continuous address, and 27 is a block flag indicating that the address spans two blocks.

FIG. 3 is a block diagram showing details of the priority management section. 28 is a table counter that counts how many addresses a group of consecutive addresses that the priority management unit is trying to check among consecutive addresses in the address table 10, and 29 is a group of consecutive addresses that is newly fetched It is a counter that counts whether or not it consists. Reference numeral 30 denotes an A priority register that stores the priority value of a group of consecutive addresses that the priority management unit is trying to check out of the group of consecutive addresses of the address table.
Reference numeral 31 is a B priority register indicating a priority value to be added to a group of consecutive addresses to be newly fetched. Three
Reference numeral 2 is a count comparator for comparing the numbers of the table counter 28 and the counter 29 to determine the priority value of the B priority register. 33 is a priority management unit.

Next, the operation of the embodiment of the present invention will be described.

(1) First, generation of continuous addresses will be described. The address monitoring unit 9 fetches the address into the B register 23 when the CPU LSI 7 issues a main memory read access request. The address of the previous main memory read access is fetched in the A register 22. Address comparator 25
At the same time that the address is taken into the B register 23
The address of the register 22 and the address of the B register 23 are compared to determine whether or not the addresses are continuous (adjacent) and whether or not the addresses are over two blocks.

(1-a) When the addresses are continuous and span two blocks, both the continuous flag 26 and the block flag 27 are turned on. The address of the A register 22 is stored in advance in the C address buffer 24, and when both flags are turned on, the address monitoring unit 9 causes the address of the C address buffer 24 and the B register 23 to be turned on.
Are written in this order to the address register 14 in the address table 10 through the continuous address line 11. When the address comparator 25 finishes the continuous determination and the block determination, the address monitoring unit 9 transfers the address of the B register 23 only to the A register 22 when the continuous flag 26 is ON.

When the main memory read access occurs again, the address monitoring unit 9 assigns the address to the B register 2 as in the previous time.
3, and the address comparator 25 performs continuous judgment. If the block flag 27 is already ON, the block determination is not performed and the block flag 27 is left ON as it is. If it is determined to be continuous, the address of the B register 23 is transferred to the A register 22 at the same time as writing to the address table 10 through the continuous address line 11. When it is determined that the addresses are discontinuous, the address comparator 25 turns off both the continuous flag 26 and the block flag 27. The address monitoring unit 9 sends the address of the B register 23 to the A register 22 and C
Move to address buffer 24.

(1-b) When the addresses are continuous and do not span two blocks, only the continuous flag 26 is turned ON. Since the address of the A register 22 is stored in the C address buffer 24 in advance, the address monitoring unit 9 transfers the address of the B register 23 to the A register 22 and the C address buffer 24 when only the continuous flag 26 is ON. Two addresses are stored in the C address buffer 24. When the main memory read access occurs again, the address monitoring unit 9 fetches the address into the B register 23 as in the previous case.

The address comparator 25 makes a continuous judgment and a block judgment. When the address is a continuous address and two blocks extend, the block flag 27 is turned on (1-
The same operation as in a) is performed. If it is a continuous address and the block does not span two, the same operation as the previous time is performed. When it is determined that the address is discontinuous, the address monitoring unit 9 turns off the continuous flag 26 to clear the contents of the C address buffer 24, and then transfers the address of the register 23 to the A register 22 and the C address buffer 24.

(1-c) If the addresses are not consecutive, the contents of the C address buffer 24 are cleared and then the address of the B register 23 is transferred to the A register 22 and the C address buffer 24. As described above, the address monitoring unit 9 writes a group of continuous addresses in the address register 14 in the address table 10 through the continuous address line 11.

(2) Next, priority management will be described. Address register 1 in address table 10
When a group of consecutive addresses is written in 4 and writing is completed by turning off the block flag 27, if the address register 14 is empty, the addresses are sequentially filled from the top address register 19. Go. If not empty, empty address register 1
The addresses are filled in order from the address register 14 closest to the top of No. 4. The priority management unit 15 writes the bit of the same polarity to the priority bit 12 for a group of consecutive addresses. Suppose here that "1" is written. Next, the block flag 27 is turned on again,
A group of addresses are written and the block flag 27 is set to OF.
When it becomes F, the addresses are sequentially filled from the address register 14 closest to the top among the vacant address registers 14 as in the previous time. Then, this time, a bit having a polarity opposite to that of the previous time, that is, "0" is written in the priority bit 12 for a group of consecutive addresses. The same is repeated thereafter.

When the address register 14 is filled with consecutive addresses and a group of consecutive addresses cannot be written, the priority management unit 15 refers to the priority bit 12 and continues with the written address of the top address register 17. Clear a group of consecutive addresses. Then, the other areas of the address register 14 are cleared by the cleared area.
All addresses are shifted to the top side all at once. Then, a vacant address register 14 on the tail side is filled with a group of consecutive addresses. This is repeated until writing becomes possible. As described above, the priority management unit 15
Manages the address of the address register 14.

(3) Next, the replacement request will be described. When the CPU LSI 7 issues a main memory read access request and hits the cache memory 8, a normal cache read hit cycle occurs, and the read data is read from the cache memory 8 to the CPU LSI 7. When a miss hit occurs in the cache memory 8, the replace request management unit 16 receives the miss hit information 21 and refers to the address table 10.

(3-a) When the main memory read access address exists in the address register 14 and the valid bit 13 is OFF, the replacement request management unit 16
Issues a request to the main memory bus 4 to burst read the read data corresponding to a group of consecutive addresses including the main memory read access address from the main memory device 5. The read data read from the main storage device 5 is stored in the read data buffer 17. The replace request management unit 16 writes the register number of the address register 14 in which the continuous address exists in order to establish the correspondence between the continuous address and the read data buffer 17, in the register number bit 18 where the corresponding read data is stored. .

Since the continuous address may move the address register 14 one after another, the register number in which the corresponding address exists is written in the register number bit 18 each time, and the correspondence between the address and the read data is managed.
When the read data is stored in the read data buffer 17 and the writing of the register number is completed, the replace request management unit 16 turns on the valid bit 13 of the continuous address in which the read data is taken. The replace request management unit 16 stores the read data for which the main memory read access request is made in the read data buffer 17, and at the same time, the CPU LSI 7
To the cache memory 8 for replacement.

(3-b) When the main memory read access address exists in the address register 14 and the valid bit 13 is ON, the replace request management unit 16 reads the corresponding read data from the read data buffer 17. , And then replaces it in the cache memory 8 at the same time.

(3-c) If the main memory read access address does not exist in the address register, the replace request management unit 16 performs a normal cache read mishit cycle to read the read data from the main memory device 5, and the CPULSI 7 Cache memory 8 at the same time as
To replace. Next, the operation of the priority management unit according to claim 2 which is an embodiment of the present invention will be described. The priority management unit 33 counts the number of addresses written in the address register 14 by the counter 29 at the same time when a group of consecutive addresses is written in the address register 14 in the address table 10. When the completion of writing is recognized by turning off the block flag 27, the priority bit 12 is read in order from the top address register 17, the priority value is written in the A priority register 30, and the same priority value is added. Priority bit 1
The number of 2 is counted by the table counter 28.

Then, the counter 29 is counted by the count comparator 32.
And the number of addresses of the table counter 28 are compared, and if they are equal or larger, the value of the B priority register 31 is left unchanged. Initially, "1" is set. If it is smaller, a value larger by “1” is added to the B priority register 31 depending on the priority of the A priority register 30. The sequence is repeated until the priority value of the priority bit 12 becomes "0". The priority value “0” of the priority bit 12 indicates that the address register 14 is empty.
The value of the B priority register 31 obtained last becomes the priority order. The value of the priority bit 12 is "1"
Has the highest priority, and the higher the value, the lower the priority.

When the address register 14 in the address table 10 becomes full, the address having the highest priority bit is cleared and the address is shifted to the top side by the empty area.

[0027]

As described above, according to the present invention, since read data is prefetched based on the history of main memory read access in the past, it is highly possible that the read data required by the CPU LSI is prefetched. That is, even with a small-capacity cache memory, it is possible to expect that the frequency of access to the main storage device is reduced and the performance of the central processing unit is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing details of an address monitoring unit shown in FIG.

FIG. 3 is a block diagram showing details of a priority management unit shown in FIG.

[Explanation of symbols]

 1 Address Line 2 Data Line 3 Control Line 4 Main Memory Bus 5 Main Memory 6 Central Processing Unit 7 CPULSI 8 Cache Memory 9 Address Monitor 10 Address Table 11 Continuous Address Line 12 Priority Bit 13 Valid Bit 14 Address Register 15 Priority Management Part 16 replace request management part 17 read data buffer 18 register number bit 19 top address register 20 tail address register 21 mishit information 22 A register 23 B register 24 C address buffer 25 address comparator 26 continuous flag 27 block flag 28 table Counter 29 Counter 30 A Priority Register 31 B Priority Register 32 Count Comparator 33 Priority Management Unit

Claims (2)

[Claims] 1. A read data prefetch mechanism of a central processing unit having a main memory device and a cache memory connected to a main memory bus composed of address lines, data lines and control lines, wherein (A) main memory read access Accesses an address that is continuous with the address of the previous main memory read access and determines that the transfer unit block of the cache memory straddles two or more blocks, and (B) the address monitoring An address composed of an address register for storing a series of addresses determined by the section, a valid bit indicating the validity of the series of addresses, and a priority bit indicating a priority order for leaving the series of addresses in the address register. A table and (C) the priority order in the FIF
Priority management part managed by O method, and (D) CP
(E) a replace request management unit that accepts the main memory read access of the ULSI, determines the read destination of the read data from the information of the address table, and further controls ON / OFF of the valid bid of the address table; A read data buffer that stores the read data when the read data corresponding to the series of addresses stored in the address register of the address table is read from the main storage device by burst read; Read data prefetch mechanism of central processing unit. 2. The central processing unit according to claim 1, further comprising a priority management unit that gives a higher priority to a larger address area of the series of addresses or to a newer one when the area size is the same. Read data prefetch mechanism.