JPH06103231A - Access equalization device for shared memory access circuit - Google Patents

Abstract

(57) [Summary] [Objective] In an exclusive control circuit using distributed arbitration of a memory shared between two control devices such as a control storage such as a magnetic disk control device or a semiconductor disk device, sharing of these is performed. The purpose is to equalize memory access. In a shared memory access circuit having at least two access means capable of accessing the shared memory and adjusting each access request, the arbitration circuits 101 and 104 and the shared memories of a plurality of levels having different priorities are provided. The signal sending means 103, 105 for outputting the access request signal and the weight detecting means 102, 106 for detecting waiting of low priority are provided. At the next access request, an access request signal with a high priority is output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exclusive control circuit using distributed arbitration of a memory shared between two control devices, such as a control storage device such as a magnetic disk control device or a semiconductor disk device. The present invention relates to the equalization of access to these shared memories.

[0002]

2. Description of the Related Art For example, a magnetic disk controller is shown in FIG.
The schematic structure is shown in FIG. Host CPU 4
The data sent from 1 is the magnetic disk device A ...
When writing to either N, the magnetic disk controller 4
Fill in via points 2 and 43.

The magnetic disk controller 42 is an MPU4.
4, a control memory 45, a memory 46, an interface control unit 47 and the like. The control memory 45 stores the control program, and the memory 46 stores the magnetic disk device A.
... Control information, data, etc. when writing data in N are written. The interface controller 47 controls the interface between the magnetic disk controller 42 and the magnetic disk devices A ... N.

The magnetic disk controller 43 is also constructed in the same manner as the magnetic disk controller 42, and has an MPU 48, a control memory 49, a memory 50, and an interface controller 51.
And so on.

The memories 46 and 50 are constructed so that they can be accessed by the MPUs 44 and 48 of the magnetic disk control devices 42 and 43, for example, when the MPU 44 writes the control information or data in the memory 46. ,
At the same time, it is written in the memory 50. Conversely, when the MPU 48 writes these in the memory 50, it also writes them in the memory 46 at the same time. This is to prevent the necessary data from being erased when a momentary power failure or the like occurs when these are written only in the memory of the magnetic disk control device side.

In this case, it is necessary to perform arbitration in order to prevent contention of access to the shared memories 46 and 50 based on the MPU 44 and the MPU 48.
The conventional shared memory control circuit is, as shown in FIG.
It used distributed arbitration.

In FIG. 4B, 55 and 56 are arbitration circuits, and the MPU 48 has a higher priority than the MPU 44, for example. Figure 4
In (B), as described above, when the MPU 44 accesses the memory 46, it simultaneously accesses the memory 50. When the MPU 48 accesses the memory 50, it also accesses the memory 46 at the same time. In these cases, the driver / receiver 57,
Access is made via 58 and 59. Therefore MP
When the access requests from the Us 44 and 48 contend with the shared memories 46 and 50, the arbitration circuits 55 and 56 give the usage right to the MPU 48 having a high priority.

[0008]

Therefore, when the access requests compete with each other, the conventional method has a problem that the processing time is always slower in the lower priority order. Therefore, an object of the present invention is to improve the bias of access times from MPUs in this way and to equalize the access times.

[0009]

In order to achieve the above-mentioned object, in the present invention, as shown in FIG.
The arbitration circuit 101, the weight detection circuit 102, and the signal transmission circuit 103 are provided on the 01 side, and the second MP
An arbitration circuit 104, a weight detection circuit 106, and a signal transmission circuit 105 are provided on the U202 side.

The signal transmission circuits 103 and 105 are both H level.
The level signal or the L level signal is selectively output. Then, access requests from both signal transmission circuits 103 and 105 are simultaneously made, and arbitration circuits 101 and 104 are sent.
When the arbitration is performed according to the above, and when the priority is kept low, the subsequent access request signal to the shared memory is changed to the H level signal having the higher priority. When the priority is high and the access is possible without waiting, the priority of the access request signal to the shared memory is returned to the original low L level signal. Therefore, when the access requests of the H level signal and the L level signal compete with each other, the H level signal has a higher priority, but when the access requests of the H level signal compete with each other, the preset order is followed.

[0011]

The operation when the second MPU 202 side is set to have a high priority in FIG. 1A will be described.

At time T ₁ in FIG. 1B, the first MP
When the U201 and the second MPU 202 simultaneously request access to the shared memory, the signal transmission circuits 103 and 105
Are the first access requests, respectively, and thus each output an L level signal. At this time, the second MPU 202
Since the priority of the side is high, the arbitration circuit 10
1 and 104 give the right to use to the request request signal RQ0 from the second MPU 202.

At this time, the arbitration circuit 101
Outputs the wait signal 156 "1", the weight detection circuit 102 outputs the switching instruction signal 161 "1" to the signal transmission circuit 1
Then, the signal transmission circuit 103 drops RQ1 and prepares to output the next request as an H level signal. On the other hand, since the arbitration circuit 104 outputs the wait signal 157 “0”, the weight detection circuit 106 sends the switching instruction signal 162 “0” to the signal sending circuit 105. As a result, the signal transmission circuit 105 continues the request request signal RQ0.

At time T ₂ in FIG. 1B, the first MP
When the U201 and the second MPU 202 make access requests to the shared memory at the same time, this time the signal transmission circuit 103 becomes H level.
Although the access request signal of the level is output, the signal transmission circuit 105 outputs the access request signal of the L level.
The arbitration circuits 101 and 104 are the first MPU2.
The usage right is given to the request request signal RQ1 from 01.

At this time, the arbitration circuit 104
Wait signal 157 "1" is output, the weight detection circuit 102 sends a switching instruction signal 162 "1" to the signal transmission circuit 105, which causes the signal transmission circuit 105 to drop RQ2 and send the next request to H. Prepare to output with a level signal. On the other hand, since the arbitration circuit 101 outputs the wait signal 156 “0”, the weight detection circuit 102 outputs the switching instruction signal 161 “0” to the signal transmission circuit 1.
Send to 03. As a result, the signal transmission circuit 103 continues the request request signal RQ1.

Next, at time T ₃ in FIG.
When the MPU 201 and the second MPU 202 again simultaneously request access to the shared memory, the signal transmission circuit 105 outputs the H level access request, but the signal transmission circuit 103 outputs the L level access request signal. Arbitration circuits 101 and 104 are the second MP
The usage right is given to the request request RQ2 from the U202.

At this time, since the arbitration circuit 101 outputs the wait signal 156 "1" as at time T ₁ , the weight detection circuit 102 outputs the switching instruction signal 161.
"1" is sent to the signal sending circuit 103, whereby the signal sending circuit 103 drops RQ3 and prepares to output the next request as an H level signal. On the other hand, since the arbitration circuit 104 outputs the wait signal 157 “0”, the weight detection circuit 106 outputs the switching instruction signal 162.
“0” is sent to the signal sending circuit 105. As a result, the signal transmission circuit 105 continues the request request signal RQ2.

At time T ₄ in FIG. 1B, when the first MPU 201 and the second MPU 202 again request access to the shared memory at the same time, the signal transmission circuit 103 outputs an H level access request signal. Since the signal transmission circuit 105 outputs the L level access request signal, the arbitration circuits 101 and 104 give the usage right to the request request RQ3 from the first MPU 201.

At this time, the arbitration circuit 104
Outputs "1" wait signal 157, because the arbitration circuit 101 outputs "0" wait signal 156, the control similar to the time T _2, is performed. By repeating this, the first MPU 201 and the second MPU 202 are made to wait alternately, and the access time to the shared memory is equalized. In FIG. 1B, the usage right is given to the request request marked with a circle.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a time chart showing its operating state.

In FIG. 2, the same symbols as in FIG. 1 indicate the same parts. 203 is a bus switching circuit, 204 is a shared memory, 20
Reference numeral 5 is a bus switching circuit, and 206 is a shared memory. The bus switching circuit 203 switches the access destination for the shared memory 204 to either the first MPU 201 or the second MPU 202. The shared memory 204 is the first MPU 20.
The shared memory on the first side, which is the first MPU 201 or the second M
It is accessed from any of the PUs 202.

The bus switching circuit 205 sets the access destination of the shared memory 206 to the first MPU 201 or the second MPU2.
It is switched to any of 02. Shared memory 20
6 is a shared memory on the side of the second MPU 202, which is the first MPU
It is accessed by either 201 or the second MPU 202.

Incidentally, these shared memories 204 and 206
Correspond to the memories 46 and 50 in FIG. 4, respectively. At time T ₀ in FIG. 3, the first MPU 201
When there is a write request from the shared memories 204 and 206 to the shared memories 204 and 206, the signal transmission circuit 103 in FIG. 2 outputs an L level access request signal, but the signal transmission circuit 105 outputs nothing. In 15
1 to 153 are “0”, and when viewed from the signals 151 to 154, “0001” is arbitration circuit 101, 10
4 is input. This is decoded by the arbitration circuit, and the arbitration circuit 101 outputs the competition signal 155 “0” and the wait signal 156 “0” to the weight detection circuit 102.

Accordingly, the weight detection circuit 102 outputs the stop signal 159 "0" and the switching instruction signal 161 "0". The arbitration circuit 101 also controls the bus switching circuit 203 to connect the address bus and data bus of the shared memory 204 to the first MPU 201.

Similarly, the arbitration circuit 104 is
This "0001" is decoded and the wait signal 157
The weight detection circuit 10 outputs “0” and the competition signal 158 “0”.
6 and outputs the address bus and data bus of the shared memory 206 to the bus switching circuit 205 as the first MPU2.
Switching control is performed so as to connect to 01. Further, in response to this, the weight detection circuit 106 outputs the stop signal 160 “0” and the switching instruction signal 162 “0”.

Next, at time T ₁ in FIG. 3, the first MPU
201 and the second MPU 202 simultaneously share the shared memory 204,
When the access request to 206 is made, the signal transmission circuit 10
3. The signal transmission circuit 105 outputs an L level signal. This causes signals 154 and 153 to be "1" respectively.
Then, the signals 151 and 152 become “0”, and the signals 151 to 1
As seen from 54, "0011" is the arbitration circuit 1
01 and 104 are input.

The arbitration circuit 101 decodes this, recognizes that the second MPU 202 has a priority order, and the bus switching circuit 20 for the shared memory 204.
3 is controlled to be switched to the second MPU 202 side, and the competition signal 155 “1” and the waiting signal 156 “1” are output to the weight detection circuit 102. As a result, the weight detection circuit 10
2 outputs a stop signal 159 “1” and a switching signal 161 “1” to the signal sending circuit 103, and then the first MPU 20.
It is prepared to output the H level signal when the access request from 1 is made.

Further, the arbitration circuit 104 decodes the above "0011" and outputs the second MPU 202 as well.
The bus switching circuit 205 for the shared memory 206 is controlled to be switched to the second MPU 202, and the competition signal 158 “1” and the wait signal 157 are recognized.
“0” is output to the weight detection circuit 106. As a result, the weight detection circuit 106 causes the stop signal 160 “0”,
The switching signal 162 “0” is output to the signal transmission circuit 105.

Then, at time T ₂ in FIG. 3, when the first MPU 201 and the second MPU 202 request access to the shared memories 204 and 206 at the same time again, the signal sending circuit 103 outputs the H level signal and the signal sending circuit 1
05 outputs an L level signal. This results in signal 152
And 153 become "1", and when viewed from the signals 151 to 154, "0110" is arbitration circuits 101 and 104.
Entered in.

The arbitration circuit 101 decodes this, recognizes that the first MPU 201 side has a priority order, and the bus switching circuit 20 for the shared memory 204.
3 is controlled to be switched to the first MPU 201 side, and the competition signal 155 “1” and the waiting signal 156 “0” are output to the weight detection circuit 102. As a result, the weight detection circuit 10
No. 2 sends a stop signal 159 “0” and a switching signal 161 “0” to the signal sending circuit 103, and prepares to output an L level signal when an access request is made from the first MPU 202 next.

Further, the arbitration circuit 104 decodes the "0110" and recognizes that the first MPU 201 side has the priority order, and controls the bus switching circuit 205 for the shared memory 206 to be switched to the first MPU 201 side, thereby competing signal 158. The wait detection circuit 106 outputs "1" and the wait signal 157 "1". As a result, the weight detection circuit 106 causes the stop signal 160 "1" and the switching signal 1
62 “1” is output to the signal transmission circuit 105. As a result, the weight detection circuit 106 outputs the stop signal “1” and the switching signal 162 “1” to the signal transmission circuit 105, and outputs the H level signal when the access request is made from the second MPU 202 next time. prepare.

Further, at time T ₃ in FIG. 3, the first MP
U201 and the second MPU202 are simultaneously shared memory 20
4 and 206, the signal transmission circuit 103 outputs the L level signal, and the signal transmission circuit 10
5 outputs an H level signal. This allows signals 151-
At 154, “1001” is input to the arbitration circuits 101 and 104.

The arbitration circuit 101 decodes this, recognizes that the second MPU 202 has a priority, and determines the bus switching circuit 20 for the shared memory 204.
3 is controlled to be switched to the second MPU 202 side, and the time T ₁
The same control as is performed.

Further, the arbitration circuit 104 decodes this "1001" and recognizes that the second MPU 202 side has priority, and controls the bus switching circuit 205 for the shared memory 206 to be switched to the second MPU 202 side. The same control as T ₁ is performed.

In this way, when the access to the shared memory competes with each other, the access is controlled so that the access can be alternately performed, so that the access is equalized.

[0036]

According to the present invention, even if the access priorities are tentatively set, the access priorities at the time of contention are alternately distributed, so that the access can be made evenly.
It is possible to improve the deviation of access time from a specific MPU.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the present invention.

FIG. 4 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 101 Arbitration circuit 102 Weight detection circuit 103 Signal transmission circuit 104 Arbitration circuit 105 Signal transmission circuit 106 Weight detection circuit 201 First MPU 202 Second MPU

Claims (1)

[Claims] 1. A shared memory access circuit, comprising at least two access means capable of accessing a shared memory, and adjusting each access request, the arbitration circuits (101), (104) having different priorities. Signal sending means (103), (105) for outputting shared memory access request signals of a plurality of levels
And wait detection means (102), (106) for detecting that a low priority is waited, and the next access request from the signal sending means (103), (105) due to being waited at the time of access conflict. An access equalization device for a shared memory access circuit, characterized in that it is configured to output an access request signal having a high priority at times.