JPH06105268B2 - Level detection circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a level detection circuit, and in particular, to improvement in temperature characteristic deterioration and detection sensitivity deterioration due to generation of an idling current in level detection of an input AC signal. The invention relates to a level detection circuit.

[Conventional technology]

The level detection circuit used to know the level of the input AC signal is used in many application fields such as radio, television, and communication equipment. This level detection circuit performs detection in the form of outputting a DC level proportional to the amplitude level of the input AC signal. Its detection function is:
Temperature characteristics and detection sensitivities are required according to the operational purpose of the applied equipment.

FIG. 2 is a circuit diagram showing a basic example of a conventional level detection circuit. In FIG. 2, the NPN transistors 2, 4, 5 and 6 and the resistor 3 form one diode detection circuit as a whole, and the PNP type transistors 9 and 11 together with the resistors 8 and 10 form a current mirror circuit. Further, the resistor 12 and the capacitor 13 form an output circuit which doubles as a smoothing circuit.

The AC signal input from input terminal 1 is an NPN transistor
It is diode-detected by 2,4,5,6 etc. and converted into direct current, and its output is smoothed by the output circuit consisting of resistor 12 and capacitor 13 through the current mirror circuit by PNP type transistors 9,11 etc. and output Supplied to terminal 14.

By the way, when the AC output is not applied to the input terminal 1, the detection output does not appear at the output terminal 14, but an unnecessary output due to the generation of an undesired idling current appears.

That is, even when no AC signal is applied to the input terminal 1, the base of the NPN transistor 2 is biased by the constant current source 7, the diode-coupled NPN transistors 4, 5 and 6, and the resistor 3. A direct current I _C shown in the following equation (1) flows through the collector of the NPN transistor 2. This I _C is the so-called idling current.

In the equation (1), R ₃ is the resistance value of the resistor 3, and V _BE2 , V _BE4 ,
V _BE5 and V _BE6 are base-emitter voltages of NPN transistors 2, 4, 5 and 6, respectively. The NPN-type transistor 2 collector current I _C is output to the resistor 12 via the PNP-type transistors 9 and 10 that are configured as a current mirror circuit, and the voltage V _O shown in the following equation (2) is generated.

V _O = I _C · R ₁₂ (2) In the equation (2), R ₁₂ is the resistance value of the resistor 12.

This voltage V _O is an undesired unnecessary output that appears at the output terminal 14 as a so-called idling voltage.

[Problems to be solved by the invention]

The conventional level detection circuit described above has an unnecessary output that is output even when the input signal is zero, a so-called idling voltage, in addition to the detected and smoothed DC voltage in proportion to the input AC signal. The output inevitably causes a decrease in detection sensitivity.

Further, there is a problem that such an idling voltage greatly varies depending on the environmental temperature in which the detection circuit is placed, and accordingly, the detection temperature characteristic that the detection sensitivity also changes is inevitably deteriorated.

An object of the present invention is to eliminate the above-mentioned drawbacks, to basically suppress unnecessary outputs other than the detection output due to an input AC signal, and to provide a level detection circuit in which temperature characteristic deterioration and detection sensitivity deterioration are remarkably improved. It is in.

[Means for solving problems]

The level detection circuit of the present invention includes a current mirror circuit having an input terminal and an output terminal, an output circuit connected to the output terminal of the current mirror circuit, and a rectified current of an input signal connected to the input terminal of the current mirror circuit. In a level detection circuit having a rectifier circuit that supplies an idling current to the input terminal of the current mirror circuit when there is no signal, and a current detection circuit of the unnecessary output suppressing circuit that generates the same current as the idling current. It is characterized in that it is connected to an input terminal to suppress the idling current from the rectifier circuit from flowing into the current mirror circuit.

〔Example〕

The present invention will now be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the level detection circuit of the present invention. In the circuit diagram of the embodiment shown in FIG. 1, only the portion indicated by the alternate long and short dash line is the unnecessary output generation suppressing means directly related to the present invention, and the other portions are exactly the same as the circuit configuration shown in FIG. Detailed description of the same contents will be omitted.

The unnecessary output generation suppression means shown by the one-dot chain line in FIG.
Type transistor 22, a diode-connected NPN type transistor 24, a circuit for generating an idling current for compensation composed of a resistor 23, and a current mirror circuit composed of PNP type transistors 25, 28 and resistors 26, 27. The above-described idling current for compensation is generated as the collector current of the NPN transistor 2 so as to cancel and compensate the effect of the idling current that occurs even when no AC signal is input.

When the AC signal is not applied to the input terminal 1, I _C shown in the equation (1) is generated in the collector of the NPN transistor 2. Similarly, the NPN transistor 22 is similarly biased by the constant current source 7, the NPN transistors 5, 6, 24 and the resistor 23, and the current I _CC shown by the following equation (3) flows.

In the equation (3), R ₂₃ is the resistance value of the resistor 23, and V _BE22 and V _BE24 are the base-emitter voltage of the NPN transistor. This I
_CC is output from the collector of the PNP type transistor 28 via the transistors of the PNP type transistors 25 and 28 having the current mirror configuration. I _CC can be easily set in the same way as I _C in advance, and I _CC = I _{C in} the embodiment of FIG.
As a result, the current mirror configuration PNP transistor 9,1
A bias current does not flow in 1 due to the effect of canceling two idling currents, and a collector current of the PNP type transistor 11 does not occur, so that an unnecessary output does not appear at the output terminal 14.

Next, when an AC signal is applied to the input terminal 1, the half-wave rectified current flows into the collector of the NPN type transistor 2, and this current is output via the PNP type transistors 9 and 11, and a smoothed output is obtained. It is possible to perform level detection, which is obtained at the output terminal 14 and thus only a DC voltage proportional to an AC signal is obtained.

In this way, by suppressing the generation of unnecessary output due to the idling current, it is possible to fundamentally eliminate the deterioration of the detection sensitivity due to the generation of unnecessary output and the deterioration of the temperature characteristics due to the fluctuation given to the unnecessary output by the environmental temperature conditions. You can

〔The invention's effect〕

As described above, according to the present invention, the provision of means for eliminating the generation of unwanted unnecessary output due to the idling current in the level detection circuit is fundamental to the deterioration of the detection sensitivity and the deterioration of the temperature characteristic due to the unnecessary output. The effect is that a level detection circuit that can be eliminated is realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a level detection circuit of the present invention, and FIG. 2 is a circuit diagram showing a basic example of a conventional level detection circuit. 1 …… Input terminal, 2,4,5,6,22,24 …… NPN type transistor, 7 …… Constant current source, 9,11,25,28 …… PNP type transistor, 3,8,10,12 , 23,26,27 …… Resistance, 13 …… Capacitor,
14 …… Output terminal.

Claims (1)

[Claims] 1. A current mirror circuit having an input terminal and an output terminal, an output circuit connected to an output terminal of the current mirror circuit, and a rectified current of an input signal connected to an input terminal of the current mirror circuit. In addition, in a level detection circuit including a rectifier circuit that supplies an idling current to the input end of the current mirror circuit when there is no signal, an unnecessary output suppressing circuit that generates the same current as the idling current is provided at the input end of the current mirror circuit. A level detection circuit, which is connected to suppress the idling current from the rectifier circuit from flowing into the current mirror circuit.