JPH06105771B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to an insulated gate transistor capable of retaining high density and good memory, and a semiconductor memory device using the same.

At present, a MOS field effect transistor (hereinafter referred to as a MOS FET), which is a constituent element, is often formed under the ordinary LSI (Large Scale Integrated Circuit) Si process as shown in FIG. In order to realize high speed operation, an n channel structure as shown in FIG. 1 is usually adopted. Since the p region 11 is a substrate and the two main electrodes are formed symmetrically in FIG. 1, the n ⁺ region 12 is used as the source and the n ⁺ region 13 is used as the drain for convenience. Reference numeral 14 is a gate which is a control electrode and is n ⁺ polysilicon in a usual process. Reference numeral 15 is a gate oxide film, 16 is a field oxide film, and 17 is a PSG film. 12 'and 13' are a source electrode and a drain electrode of Al or the like. Reference numeral 18 denotes a p ⁺ region, which is a channel stopper region for blocking a channel that is easily formed between the field oxide film and the p substrate 11. Originally, the gate oxide film 15 and the like may include a thin Si ₃ N ₄ film in a part thereof. The surface of FIG. 1 is usually provided with a passivation film.

A structure in which an insulating film is provided directly on one of the main electrode regions, for example, the drain region, of the MOS FET configured as shown in FIG. 1 and the electrode is provided through the insulating film, or the drain region A structure in which an electrode is formed on n ⁺ polysilicon and the electrode is provided on an oxide film formed by thinly oxidizing the surface of the polysilicon is a 1-transistor 1-capacitor d-RAM cell.

Experimental samples were prepared with the same parameters except for the channel length L (mask level) for two types of substrates and two types of gate oxide film thickness _Tox , and the retention time characteristics of the memory contents were examined. The results are shown below. The source region and drain region are provided by As ion implantation, and the depth x _J
Is about 0.5 μm. The acceleration voltage at that time is 100 kV. Channel doping is performed by ion implantation of boron (B). The gate width is 100 μm, the gate oxide film thickness _Tox is 500 μm and 1000 μm, and the p substrate low efficiency ρ _sub is 7 Ωc.
m and about 20 Ωcm.

The retention time characteristics were evaluated with the circuit configuration shown in FIG. 2 in which one end of the storage capacitor C _S of this d-RAM was grounded. In FIG. 2, 21 and 22 are word lines and bit lines, respectively, and 23
And 24 are a MOS FET (T ₁ ) and a storage capacitor (Cs), respectively. At the time of writing, the write voltage V _W is applied to the bit line 22 and V _G is applied to the word line 21. If MOS FET T ₁ is a channel, both V _W and V _G are positive voltages. When the positive voltage V _G is applied to the lead wire and T ₁ becomes conductive, the positive voltage V _W is applied to the bit line, so a current flows into the storage capacitor C _S , and C _S becomes almost V _W. Be charged. In this state,
Electrons flow out from the n ⁺ drain region 13, and the n ⁺ region 13 lacks electrons and is positively charged. Writing is completed when the bit line voltage is removed after returning the word line pulse to zero. In the memory holding state, it is not necessary to apply an external voltage to any terminal of the memory cell having the configuration shown in FIG. In this holding state, the n ⁺ region 13 lacks electrons and is positively charged,
Since it is in a reverse bias state with respect to the p-substrate 11, the stored contents will be stored for a long time.

The retention time characteristics thus measured are shown in FIGS. 3, 4 and 5 for three types of samples. These data were measured at room temperature operating conditions. V _G = 5V,
V _W = 5V. The holding time depends on the voltage stored in C _S.
It is defined when it becomes 1/4. The retention time is plotted against the run channel length L _eff . L _eff is about 0.5 μm shorter than the channel length determined by the mask. In the figure, ... means p substrate
The value of the substrate bias V _B applied to 11 is 0V, −1V, −2V, −4V
Is equivalent to Figure 3 shows T _OX = 1000Å, ρ _sub ＝
7 Ωcm sample, FIG. 4 shows the results of T _OX = 5000 Å, ρ _sub = 7 Ωcm, and FIG. 5 shows the results of T _OX = 500 Å, ρ _sub = 20 Ωcm. When L _eff is long, the retention time is as long as around 100 seconds, but when L _eff is short, the retention time is rapidly shortened. In the sample shown in FIG. 5, L _eff = 2.5 μm, which is already about 100 μsec even when V _B is added. The sample of FIG. 5 does not operate as a d-RAM unless L _eff = 3.5 μm or more. On the other hand, in the sample of FIG. 3, V _B = −4V
If so, the memory is sufficiently retained up to L _eff = 0.5 μm. However, even with this sample, when L _eff = 0.5 μm,
It can no longer be used for d-RAM. In the sample of FIG. 4, V _B = −4
Even for V, when L _eff = 1.5 μm, the holding time begins to decrease.

If the channel length is shortened in order to increase the density, the holding time will be drastically reduced at L = 1 μm (L _eff = 0.5 μm) and the D-RAM will not work.

An object of the present invention is to provide an insulated gate transistor that retains stored contents sufficiently even if the channel length is extremely short, a semiconductor memory and a logic circuit using the same.

First, the reason why the stored contents are rapidly erased when the channel becomes short as shown in FIGS. 3 to 5 will be explained.

As the channel length becomes shorter, the potential barrier, which has been blocking the flow of electrons between the source and drain until then, is reduced by the influence of the source and drain regions. In the long channel sample, the potential of the channel region is controlled by the gate voltage and the substrate voltage only, and the potential barrier height is controlled, but when the channel becomes short, it is also controlled by the source potential and the drain potential. In other words, the electrostatic induction effect that appears in the electrostatic inductive transistor (SIT) appears, and the current flows between the source and drain without applying the gate voltage.
Here, the current is called SIT current. In the sample of FIG. 3, the mask channel length L = 1 μm (execution channel length
The relationship between the drain current I _d and the drain voltage V _d of the sample with L _eff = 0.5 μm) is shown in FIG. The vertical axis is I _d and the horizontal axis is V _d . FIG. 6 shows that a current flows between the source and drain even though the gate voltage V _G = 0. Naturally, if the substrate bias V _B is increased negatively,
I _d becomes smaller. That is, even if V _G = 0, a current flows when a certain voltage is applied between the source and drain.

In d-RAM, in a state in which the voltage V _W is held written in the storage capacitor C _S, it is not being applied the voltage V _W between the source and the drain. Therefore, naturally, the current as shown in FIG. 6 flows, and the accumulated voltage is attenuated. The process of reducing the accumulated voltage due to the current flowing between the source and drain can be easily analyzed. Since the circuit is as shown in FIG. 7, the voltage stored in C _S is attenuated by the current flowing through MOS FET T ₁ . _{Assuming that} the voltage of C _S is V, the equation describing the voltage decay process is Is. t is time. As you can see from Figure 6,
The SIT current I _d changes almost exponentially with respect to the voltage. That is, it can be expressed as I _d = I _0e ^αV . I ₀ and α vary depending on the substrate bias V _B. The solution of equation (1) under the initial condition V (o) = V _W is Is. V (t) becomes 1 / γ of the write voltage. Time t
γ is Becomes The values calculated with γ = 4 and the measured values are shown in FIG. FIG. 8 plots the retention time against the substrate bias, V _B. The mark is the measured value, the + mark is the calculated value,
You can see that they are almost the same. That is, the attenuation of the accumulated voltage when the channel becomes short depends on the SIT current between the source and drain. Next, comparing FIG. 3 with FIG. 4, the retention characteristic in FIG. 4 is worse when the channel is shorter. That is, the thinner the gate oxide film pressure _{Tox, the} worse the retention characteristics. Let me briefly mention this.

As shown in FIG. 1, the gate of an n-channel MOS FET is usually formed of n ⁺ polysilicon in many cases. FIG. 9 shows a cross-sectional structure in the one-dimensional direction from the gate to the substrate. The thickness of the p substrate 11 is d. The dielectric constants of the gate oxide film and the p substrate are ε ₂ and ε ₁ , respectively. Board and
The formula that describes the potential distribution when _a reverse bias V _a (including the diffusion potential V _bi ) with the n ⁺ gate electrode is applied is V _a = V _o + V _s (4) Given in. V _o and V _s are voltages applied to the oxide film and the p substrate, respectively. N _A is the effective acceptor concentration of the p substrate. q is a unit charge. When the depletion layer width W and V _o in the p region are calculated from the equations (4) and (5), Becomes Also, the electric field strength in the gate oxide film and in the p region
E _o and E _s are Is. However, Which is the depletion layer width when the voltage V _a is applied to all p substrates.

FIG. 1 shows the potential distribution in the p substrate when changing _Tox . The vertical axis represents electric potential and the horizontal axis represents coordinates. Substrate bias V _B =
At 0, only the diffusion potential V _bi is applied. _Tox
When = 0, the curve is represented by, and has the same potential as the potential source of the p region of the interface. As the _Tox becomes thicker, the potential at the interface with the oxide film increases. _Tox = ∞, that is, when the oxide film is sufficiently thick, it becomes a constant line shown by a dotted line. That is, as _Tox becomes thinner, the potential of the interface approaches that of the source region. This means that electrons can easily enter the region where the potential is lowered from the source or drain and current can flow.

In order to shorten the channel, the gate oxide film thickness is necessarily made thin. This effect becomes more prominent.

In this way, when the channel is made short, the current between the source and the drain does not become so large unless a portion having a low potential is formed on the surface. The reason described above occurs because the gate electrode is made of n ⁺ polysilicon in the n-channel MOS FET. To overcome this difficulty, the gate electrode can be made of p ⁺ polysilicon. FIG. 11 shows the potential distribution just below the gate oxide film when the p ⁺ polysilicon gate electrode is used. The potential O indicates the potential of the source region. V _b1 ′ is the diffusion potential of the n ⁺ source region and the p ⁺ polysilicon region, which is about 1.0 to 1.1 V at room temperature. If the p substrate impurity density is about 1 × 10 ¹⁵ cm ^-3 , V
_b1' - _Vb1 is about 0.25V. In the case of p ⁺ polysilicon gates, the limit of thin _Tox is a curve, which becomes more so as _Tox becomes thicker. That is, _Tox
The potential at the SiO ₂ -pSi interface, which is thin, becomes high, making it difficult for electrons to flow. Sample of Figure 3, ie _Tox = 1000
Å, ρ _sub = 7 Ωcm channel-doped with p ⁺ polysilicon gate retention and relaxation, the third,
The retention time measured under the same conditions as in FIGS. 4 and 5 is shown in the curve of FIG. The retention time is plotted against the substrate bias. The channel length L was 1 μm, and the holding time was extremely short in FIG. When V _{B is set} to −4 V, L = 1 μm and L _eff = 0.5 μm, and a holding time of about 100 seconds can be obtained. This tendency becomes more remarkable as _Tox becomes thinner. Under the same conditions, the retention time of the n ⁺ polysilicon gate is 6 msec. It's a huge improvement. The curve in FIG. 12 is the result when platinum (Pt) was used for the gate electrode.

Of the present invention, the cross-sectional structure of the d-RAM cell of the p ⁺ polysilicon gate shown in FIG. 13. The numbers are written in correspondence with FIG. The numbers different from those in FIG. 1 will be described. 14 'is p ⁺ polysilicon. 13 ″ is n ⁺ polysilicon. 31 is a thin oxide film and 32 is an electrode such as Al. In this structure, 1
The storage capacitance is created by 3 ″ −31−32. In FIG. 13, the gate electrode 14 ′ is composed of only p ⁺ polysilicon, but the resistance of the word line is increased due to the high density of short channels. Is too large to affect the operation, p ⁺ polysilicon is provided on the gate oxide film and Pt is formed on it.
Is effective to reduce the resistance of the word line. A metal such as Mo or W may be further provided on Pt. Of course, also the W and Mo directly to the p ⁺ polysilicon p ⁺
It may be provided in polysilicon. In any case, a metal having a high melting point and not impeded by the subsequent high temperature process may be used. In the configuration of FIG. 13, it is also effective to provide ap ⁺ region adjacent to the n ⁺ region 13 in order to increase the storage capacity. The impurity density of the p ⁺ region adjacent to the n ⁺ region 13 may be set so that the breakdown phenomenon does not occur when the write voltage is accumulated. Often made to densities on the order of 10 ¹⁷ cm ^-3 .

The results of FIG. 12 were measured with the circuit configuration of FIG. 2, that is, the configuration in which one end of the storage capacitor, that is, 32, is grounded. This is the result of so-called depletion type operation in which electrons flow out from the n ⁺ region 13 and the lack of the amount of electrons is memorized. It goes without saying that the cell shown in FIG. 13 can be operated by a so-called storage type operation in which a positive voltage V _ss is applied to 32 to operate, as is normally done. When the temperature of the storage type operation is high, the holding time is shorter than that of the depletion type operation.

In the p ⁺ polysilicon gate n-channel MOS FET of the present invention, the potential barrier at the SiO ₂ -pSi interface is higher than that of the conventional n ⁺ polysilicon gate n-channel MOS FET. N ⁺ regions 12, 13
The depth x _j is gradually made shallower, but the SIT current may flow between the source and the drain not only in the vicinity of the interface but also due to internal conduction, which may deteriorate the retention time characteristic. In order to suppress this, it is effective to provide a p ⁺ region inside. For example, if the p ⁺ region is provided inside the n ⁺ regions 12 and 13 along the channel by the ion implantation, the internal potential barrier is increased and the SIT current is further reduced. An example of the structure is shown in FIG.

FIG. 14 (a) shows an example in which the p ⁺ region 33 reaches below the n ⁺ region 13, but the p region under 13 and the p region along the channel have the same impurity density. However, the area along the channel may be higher. n ⁺ region 12 and p ⁺ 33
It is desirable to be separated from each other. This is because the bit line capacitance is not increased. FIG. 14B shows an example in which the p ⁺ region 33 is provided only in the region along the channel.

Similar effects can .n ⁺ region 13 can also be realized by the structure of Figure 15 in which a p layer 11 "on the p ⁺ substrate 11 may be directly adjacent to the p ⁺ substrate 11 is a matter of course. It is preferable that the n ⁺ regions 12 are not adjacent to each other.

As shown in FIGS. 14 and 15, when the p ⁺ region is provided along the channel, the response of the channel potential distribution to the word line voltage becomes faster and the operation speed is improved. Of course, it is important to consider not to increase the bit line capacitance.

Furthermore, when the MOS transistor is shortened and the storage amount is reduced, the problem that carriers generated by α particle irradiation flow into the floating storage region to erase the memory is newly generated. The α-particle has the energy of MeV shown in the figure, and is considered to enter into Si about 10 to 15 μm. The most electron-all pairs are generated near the α particle stop in Si. Therefore, as shown in FIG. 14 (a), a drift electric field is generated in the substrate direction from the p ⁺ region 33 in which the p ⁺ region 33 is provided below the channel region or the accumulated n ⁺ region 13 and electrons generated in the substrate are generated. No longer flows into n ⁺ region 13,
Malfunction due to α particle irradiation is drastically reduced.

Exactly the same thing can be applied to a two-layer polysilicon d-RAM cell as shown in FIG.

41 is a p substrate, n ⁺ region 42 is a bit line region, 43 is low resistance polysilicon, 44 is a p ⁺ polysilicon gate, 45 is a gate oxide film, 46 field oxide film, and 47 is an oxide film. 48 is the p ⁺ region for the channel stopper. The storage capacitor C _s is, 43-
It consists of 45-41. 41 'is a substrate electrode. The signal is accumulated by the amount of electrons accumulated in the depletion layer formed under 43. It may be called an inversion layer.

Providing a p ⁺ region or p ⁺ substrate as in FIGS. 14 and 15 is also effective.

In the structure example of the d-RAM cell so far, the substrate electrode is provided on the entire surface, but it may not be provided on the entire surface. Also,
The surface may be further covered with a passivation film.

So far, we have described examples in which bit lines and storage capacitors are provided on the same plane, but exactly the same thing happens with VMOS and UMOS with notches, and VMOS structure and UMOS structure books. Of course, the d-RAM of the invention can also be constructed.

Although only the n-channel has been described, the same structure is effective for the p-channel in which the conductivity type is completely inverted. That is, any structure may be used as long as it has the same conductivity type high impurity density region as the channel provided directly on the gate insulating film. The thinner the gate insulating film, the more efficiently the voltage applied to the gate is applied to the channel region.
Therefore, in order to increase the conversion conductance,
It is desirable that the gate insulating film be as thin as possible so long as the breakdown voltage and other factors are allowed. By the way, if the gate electrode of the portion directly adjacent to the gate data is composed of a high-impurity density layer of the same conductivity type as the source region and the drain region, the potential of the channel adjacent to the gate insulating film decreases, and the source region Approach potential. Therefore, even if the gate voltage is set to zero, the channel cannot be sufficiently cut off, and a current flows between the source and drain. Moreover, this effect becomes remarkable as the channel length is shortened in order to increase the density. The structure of the present invention has such a structure that the SIT current between the source and the drain is sufficiently suppressed even in the short channel structure. The leak current between the source and the drain in the zero gate voltage state is so severe that it is in the d-RAM structure. Therefore, the application of the MOS FET of the present invention has been described so far only in the d-RAM. Although only one cell structure is shown in the figure, such cells are provided at the intersections of the matrix formed by the bit lines and the word lines, and the word lines are connected to the decoder and the bit lines are connected to the sense amplifier. That is why. The short channel structure increases the exchange conductance and accelerates the speed even in the logic circuit. The effect of leakage current when shutting off the elements used in the logic circuit is d-
Not as big as in RAM. However, if the leak current becomes too large, it tends to be difficult to obtain a clear difference between the high level and the low level of the output. Therefore, in a theoretical circuit of a MOS FET in which the channel length is about 1 μm or less, it is desirable to configure the gate in the same conductivity type region as the channel, although the process is complicated.

Examples are shown in FIGS.

FIG. 17 shows an inverter having a load of a MOS transistor T ₃ whose gate is directly connected to the source. T ₂ is the MOS of the present invention
It is a transistor. Since T ₃ is in a conductive state by directly connecting the gate and source, it is rather an MO of the conventional structure.
S-transistors are suitable. The high level is almost close to V _{DD because} T ₂ can be blocked sufficiently.

FIG. 18 shows that the gate of T ₅ has a constant potential V _GG (in some cases T ₅
It may be directly connected to the drain of)). T ₄ is the MOS transistor of the present invention.

FIG. 19 shows a complementary inverter. Both T ₆ and T ₇ are MOS transistors of the present invention. This CMOS configuration is a so-called ideal circuit configuration in which current flows only when switching is performed, and no current flows steadily. However, if this CMOS structure is composed of conventional MOS FETs and has a short channel, current will flow during steady state due to a large leakage current, increasing power consumption. But,
In the MOS transistor of the present invention, the leak current is suppressed to a sufficiently small level, so that the advantages of the CMOS structure can be realized even in a short-channel, high-density integrated circuit. further,
Since the gate capacitance for shortening the channel becomes smaller, the switching time becomes faster, and the advantages of the CMOS structure become more prominent. The CMOS structure using the MOS transistor of the present invention is extremely excellent in high speed and low power consumption characteristics. Based on the configuration of Fig. 17, Fig. 18, and Fig. 19,
NOR and NAND gates can be easily configured and static R
AM is similarly easy to configure.

The structure of the present invention is not limited to that described here. The conductivity type may be completely reversed. In short, it suffices that the high impurity concentration region of the conductivity type opposite to the source region is provided as at least a part of the gate electrode in direct contact with the gate insulating film.

Since the insulated gate transistor of the present invention can suppress the leak current at the time of interruption to be sufficiently small even in a short channel structure having an effective channel length of 1 μm or less, the effect is particularly remarkable when a d-RAM is constructed. Even if the effective channel length is 0.5 μm, it is possible to store and hold it sufficiently. In addition, when the CMOS structure is adopted, low power consumption and high speed are particularly emphasized by the short channel structure. As described above, the industrial value of the insulated gate transistor of the present invention and the integrated circuit using the same is extremely high.

The insulated gate transistor of the present invention, a memory using the same, and a logic circuit can be manufactured by the conventionally known crystal technique, lithography technique, oxidation technique, diffusion technique, CVD technique, vapor deposition technique, wiring technique, and the like.

[Brief description of drawings]

1 is a cross-sectional structure of a MOS FET, FIG. 2 is a circuit configuration of a d-RAM cell, FIGS. 3 to 5 are channel length dependences of retention time, FIG. 6 is I _{d to} V _d characteristics, and FIG. Fig. 7 is a circuit for analyzing retention characteristics, Fig. 8 is the substrate bias dependence of retention time, Fig. 9 is a cross-sectional structure, Fig. 10 is the potential distribution in the p-substrate just below the gate oxide film, and Fig. 11 is P ⁺ poly. Potential distribution directly below the gate oxide film when used as a silicon gate electrode, FIG. 12 shows holding in the structure of the present invention, FIGS. 13 to 16 show cross-sectional structural examples of the d-RAM cell of the present invention, FIG. FIG. 18 is an inverter using the insulated gate transistor of the present invention, and FIG. 19 is a complementary inverter circuit using the insulated gate transistor of the present invention.

 ─────────────────────────────────────────────────── --Continued from the front page (56) Reference JP-A-56-32757 (JP, A) JP-A-52-86084 (JP, A) JP-A-52-115668 (JP, A) JP-A-51- 114074 (JP, A) JP-A-50-8484 (JP, A) JP-A-55-156358 (JP, A) JP-B-48-15390 (JP, B1) Open technical report (Publication number 79-138)

Claims (2)

[Claims] 1. An inversion layer for accumulating signals formed near the surface of a first conductivity type semiconductor substrate (41), a bit line region (42) of a second conductivity type, the bit line region and the inversion layer. A channel region of the first conductivity type located between the channel region and the gate insulating film on the surface of the channel region and the inversion layer (4
5), the word line (44) formed on the gate insulating film, the low resistance wiring layer (43) located on the inversion layer on the gate insulating film, and the low resistance wiring layer. A semiconductor memory comprising a small amount of an upper insulating film (47) and a first conductivity type high impurity density buried region formed in a portion extending over the channel region inside the semiconductor substrate and a lower portion of the inversion layer. In the device, the inversion layer, the gate insulating film (45) and the low resistance wiring layer (43) constitute a storage capacitor, and at least the word line has a first capacitance.
It is a material composed of conductive type polycrystalline silicon and a refractory metal formed on the polycrystalline silicon, and the impurity density in the lower part of the channel region of the buried region is higher than the impurity density in the lower part of the inversion region. Is characterized in that a potential barrier is formed sufficiently high in the vicinity of the source region in the channel region to suppress the SIT current in a state where no voltage is applied, and a drift electric field is formed from the buried region toward the substrate. Semiconductor memory device. 2. A source region (12) and a drain region (13) of the second conductivity type, which are located near the surface of the first conductivity type semiconductor substrate (11), between the source region and the drain region, A channel region of one conductivity type, an insulated gate transistor in which a gate insulating film (15) and a gate electrode (14 ') are sequentially formed on the surface of the channel region, and a storage capacitor directly connected to the insulated gate transistor. In a semiconductor memory device having a source region as a bit line region and the gate electrode as a word line, at least the gate electrode is made of a first conductivity type polycrystalline silicon and a refractory metal formed on the first conductivity type polycrystalline silicon. At least a part of a region extending from the lower portion of the channel region to the lower portion of the drain region inside the semiconductor substrate adjacent to the channel region has a high conductivity with the first conductivity type. Embedded area of pure density (33)
Is provided to increase the impurity density of the buried region along the lower portion of the channel region higher than the impurity density of the buried region below the drain region, and the SIT is provided near the source region in the channel region without applying a gate voltage.
A semiconductor characterized in that a potential barrier is formed sufficiently high to suppress the current and that carriers generated by α particle irradiation at the drift electrode from the embedded region toward the substrate are prevented from flowing into the drain region. Storage device.