JPH0611047B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, and more particularly to an improvement for reducing the layout area thereof.

[Prior Art] FIG. 10 shows a layout example of a memory cell of a conventional 2-boat CMOS RAM using field effect transistors. FIG. 11 is a circuit diagram thereof, and FIG. 12 is a sectional view taken along the line YY 'in FIG. In FIG. 10, p ⁺ diffusion layer 100 and polysilicon line 1
The pMOS enhancement type transistors T ₁ and T ₂ are formed at the intersection of 01, and the nMOS enhancement type transistors T _{3 to} T ₈ are formed at the intersection of the n ⁺ diffusion layer 102 and the polysilicon line 101. The black square portions 104 in the figure are p ⁺ diffusion layers 100 and n ⁺ diffusion layers 102.
Alternatively, the polysilicon line 101 is a portion that is electrically joined to the metal layer (metal) 103 on the insulating film, and is called a contact hole.

In a CMOS transistor, it is necessary to make a pMOS transistor and an nMOS transistor on the same substrate.
For that purpose, as shown in FIG. 12, the other conductivity type, that is, a p-type Si substrate, that is, the p-well 106 is embedded in the n ^- Si substrate 105. In the FIG. 12, n for pMOS ^- p for an nMOS into the substrate ^- the portion (p- well) provided, an example is shown in which all of the nMOS transistor is made therein. In FIG. 10, the p-well portion is omitted. As is clear from FIG. 12, the cross-sectional structure is such that SiO ₂ is formed on the p ⁺ and n ⁺ diffusion layers 100 and 102.
The polysilicon layer 101 is arranged via the insulating film 107 such as the above, and the metal layer 103 is further arranged thereon via the insulating film 107. By connecting these via the contact holes 104, a layout pattern as shown in FIG. 10 is formed. Here, the minimum line widths of the p ⁺ and n ⁺ diffusion layers 100 and 102, the polysilicon layer 101, and the metal layer 103, the minimum distance between them, and the like are determined based on the layout rule. The layout pattern of FIG. 10 is an example of layout based on a standard CMOS layout rule, and λ in the drawing indicates a basic unit of length.

On the other hand, in addition to the Si substrate shown in FIG. 12, there is also a semiconductor integrated circuit in which a single crystal Si layer is formed on an insulating substrate. This is a structure using a so-called SOI (Silicon On Insulator) technology, and the sectional structure is the same as the structure shown in FIG. 12 except for the substrate. That is, the diffusion layers (p ⁺ , n
⁽⁺ Diffusion layer), a polysilicon layer is arranged via an insulating film, and a metal layer is further arranged thereon via an insulating film.

As another construction method using such an SOI structure,
A transistor configuration method as shown in the figure has been proposed.
Here, 110 is a Si substrate, 111 is a SiO ₂ insulating film, 112, 1
13 and 114 are a source, a drain and a channel region (diffusion layer). 115 and 116 are first and second polysilicon layers. 117 is a metal layer and 118 is a contact hole.

FIG. 13 shows an insulated gate field effect transistor having an SOI structure in which a low resistance region (first polysilicon) 115 for shielding a channel region is provided below a channel region 114 via an insulating film 111 (Japanese Patent Application No. No. 93521,
Hereinafter, a conventional configuration of an XMOS transistor) is shown.

FIG. 14 shows the XMOS transistor structure of FIG. 13 by a transistor symbol. The upper gate Vgu is shown by a solid line and the lower gate Vgl is shown by a broken line.
The XMOS transistor includes a low resistance region 1 for shielding the channel region under the channel region 114 via an insulating film 111.
The feature is that 15 is provided, and has the following advantages.

1) When used as a three-dimensional integrated circuit element, it has an effect of shielding electrical interference from elements or wirings in the upper and lower layers with two gates (Vgu, Vgl).

2) It has an effect of suppressing the short channel effect.

[Problems to be Solved] In the semiconductor integrated circuit, it is necessary to increase the number of wiring layers in order to reduce the layout area. Conventional Si
In the layout based on the substrate or the SOI structure, as described above, the diffusion layer (p ⁺ , n ⁺ diffusion layer) -polysilicon layer-metal layer. In such a conventional semiconductor integrated circuit, in order to increase the number of wiring layers,
A method is employed in which a metal layer (second metal layer) is further provided on the metal layer (first metal layer) via an insulating film. However, increasing the number of wiring layers by such a method results in a larger surface step toward the upper layer. Therefore, in the second metal layer, as compared with the wiring pattern of the first metal layer, The spacing must be large. Therefore, there is a problem in that the wiring efficiency is lowered toward the upper layer.

Therefore, an object of the present invention is to provide an XMO having the above advantages.
An object of the present invention is to provide a semiconductor integrated circuit intended to reduce the layout area by using S transistors.

[Means for Solving the Problems] In order to achieve such an object, the present invention forms a wiring pattern in the same layer as the channel region shield low resistance region using the same material as the channel region shield low resistance region. By doing so, a high-density semiconductor integrated circuit is provided.

[Operation] According to the configuration of the present invention as described above, in order to increase the number of wiring layers, instead of using the second metal layer as in the conventional configuration,
Since the same material (first polysilicon layer) as the low resistance region for the channel region shield is provided as the wiring layer, the above problems can be solved and the layout area can be reduced.

Embodiments Embodiments of the present invention will be described below with reference to the drawings. Although the XMOS transistor has been described as having a structure suitable for a three-dimensional integrated circuit element, the case where the present invention is applied to a two-dimensional integrated circuit will be described below to simplify the description. In order to obtain a three-dimensional integrated circuit structure, an SOI technique is used on the two-dimensional integrated circuit structure to form a single crystal Si layer, and a similar semiconductor integrated circuit structure is formed on the single crystal Si layer. Can be configured.

FIG. 1 shows an embodiment of the present invention, in which a layout example of a memory cell of a 2-port CMOS RAM similar to FIG. 10 is shown. In the figure, 21 is a p ⁺ diffusion layer, 22 is an n ⁺ diffusion layer, 23 is a first polysilicon layer, 24 is a second polysilicon layer, and 25 is a metal layer. 26 is a contact hole. Second
FIGS. a to 2d show layout patterns obtained by disassembling FIG. 1 for each layer. That is, FIG. 2a shows the first polysilicon layer 23, FIG. 2b shows the p ⁺ and n ⁺ diffusion layers 21 and 22, FIG. 2c shows the second polysilicon layer 24, and FIG. 2d shows the metal layer 25. is there. FIG. 3 is a circuit diagram of FIG. 1 and is represented by a transistor symbol similar to that of FIG. FIG. 4 shows a sectional structure of the structure of FIG. 1 taken along the line Y- ′.

The portion shown by the broken line in FIG. 1 is a wiring pattern using the same material (first polysilicon layer) as the low resistance region for channel region shield shown in FIG. 13, and corresponds to the layout pattern of FIG. 2a. To do. This portion is indicated by a broken line in the circuit diagram of FIG.

In FIG. 2a, of the first polysilicon layer 23 in the figure,
Wiring patterns other than those denoted by reference numerals 1, 2, 3, 4, 5, and 6 are for setting the potential of the lower gate (Vgl) peculiar to the XMOS to a constant potential, and the pMOS transistor (T ₁ , T ₂ ) is connected to V _DD , and nMOS transistors (T _{3 to} T ₈ ) are connected to V _SS . With this configuration, when three-dimensionalized,
Can shield electrical interference. Wiring patterns 1, 2,
3, 4, 5 and 6 show the idea of the present invention, which is effectively used as a wiring pattern and the layout area can be reduced. That is, the lower gate (Vg
There is no l). In the layout using the conventional insulated gate field effect transistor, since there is no wiring layer in the portion shown by the broken line in FIG. 1 (the layout pattern in FIG. 2a), the wiring portions 1, 2, 3, 4, 5, 6 is the diffusion layers 21 and 22
It is necessary to perform wiring in an upper wiring layer, that is, the second polysilicon layer 24 or the metal layer 25 in FIG. 1, and the layout area is increased only in the wiring portion. However, in the example of FIG. 1, as is apparent from the layout, the wiring portions 1 and 2 can be wired in the second polysilicon layer 24 without expanding the cell area. 5, 5 and 6 contribute to the reduction of the layout area.

In FIG. 1, a black square portion 26 in the drawing is a first polysilicon layer 23, p ⁺ and n ⁺ diffusion layers 21 and 22, and a second polysilicon layer 24 is a metal layer (metal) 25 electrically. The contact hole to be joined, and the white square portion 27 is a via hole for electrically connecting the first polysilicon layer 23 and the second polysilicon layer 24, and the double square portion 28 below the diagonal line.
Is a contact (buried contact) for electrically connecting the first polysilicon layer 23 and the p ⁺ and n ⁺ diffusion layers 21 and 22. First polysilicon layer 23, p ⁺ and n ⁺
The minimum line width of each of the diffusion layers 21 and 22, the second polysilicon layer 24, and the metal layer 25 and the minimum distance between them are determined based on the SOI layout rule. The layout pattern of FIG. 1 is an example of layout based on a standard SOI layout rule, and λ in the drawing indicates a basic unit of length.

Here, comparing the cell area of the conventional 2-port RAM shown in FIG. 10 with the cell area of FIG. 1 which is an embodiment of the present invention, (45.5λ × 47λ) / (38λ × 62.5λ) = 0.9, the cell area has been reduced by 10%. That is, the first
The layout area of the figure is the same as that of the conventional layout using the insulated gate field effect transistor having the SOI structure for the wiring portions 3, 4, 5 and 6 shown in FIGS. 1 and 2a, and the conventional Si substrate. Therefore, the layout area can be reduced by 10% compared to the layout using the field effect transistor. These are all made of the same material as the low resistance region for the channel region shield (first polysilicon layer).
This is the effect of providing as a wiring pattern.

This can also be explained as follows from the sectional view of FIG. In the conventional SOI structure or the cross-sectional structure of the layout using the Si substrate, as shown in FIG.
p ⁺ and n ⁺ diffusion layers 100 and 102-polysilicon layer 10
In the present invention, as shown in FIG. 4, the first polysilicon layer 23-p ⁺ and n ⁺ diffusion layers 21 and 22-the second polysilicon layer are formed. 24− is composed of the metal layer 25, and equivalently corresponds to the fact that the number of wiring layers is further increased. As a result, the layout area can be reduced, and a layout configuration can be realized in which the advantages of the XMOS described above are utilized as they are.

The XMOS transistor is physically one transistor as shown in FIGS. 13 and 14, but logically it can be considered that two transistors are connected in parallel. That is, the logical operation is the upper gate V
If either the gate potential of gu or the lower gate Vgl or the gate potential of both of them exceeds the threshold voltage, conduction occurs. By paying attention to this fact and effectively using both gates of the XMOS transistor, the layout area can be further reduced.

FIG. 5 shows a layout example of a D flip-flop as an embodiment of such a logic circuit. 6a to 6d show layout patterns obtained by disassembling FIG. 5 for each layer. That is, FIG. 6a shows the first polysilicon layer 23, and FIG. 6b shows the p ⁺ and n ⁺ diffusion layers 21 and
22, FIG. 6c is a second polysilicon layer 24, and FIG. 6d is a metal layer (metal) 25. FIG. 7 is a circuit diagram of FIG. FIG. 8 is a layout example of a conventional D flip-flop using a field effect transistor formed on a Si substrate, and FIG. 9 is a circuit diagram thereof.

A portion shown by a broken line in FIG. 5 is a wiring pattern made of the same material as the low resistance region for channel region shield shown in FIG. 13, that is, the first polysilicon layer 23.
It corresponds to the layout pattern in the figure. This part is the 7th
It is indicated by a broken line in the circuit diagram of the figure.

In FIG. 9, pMOS transistors T ₃ , T ₄ and T ₉ , T ₁₀ are portions in which two transistors are connected in parallel. This portion can be represented in an XMOS transistor as shown in FIG. That is, the transistors of T ₃ , T ₄ and T ₉ , T ₁₀ can be treated as one transistor in terms of layout area, and logically two transistors are connected in parallel, and the layout area can be reduced. Can be reduced.
In FIG. 7, the lower gates of the transistors other than T ₃ , T ₄ and T ₉ , T ₁₀ are connected to V _DD in the pMOS transistors (T ₁ , T ₅ , T ₁₁ ) and the nMOS
Transistor _{(T 2, T 6, T} 7, T 8, T 12, T 13,
At T ₁₄ ) it is connected to V _SS . With such a configuration, electrical interference can be shielded in the case of three-dimensionalization.

5 and 6a, the first polysilicon layer 23 in the figures
Among them, the wiring patterns denoted by reference numerals 7 and 8 are layout examples in which the lower gate is effectively used, and T ₃ and T ₁₀
The gate is wired by the first polysilicon layer, which contributes to the reduction of the layout area. Further, the wiring pattern indicated by reference numeral 9 in the first polysilicon layer 23 in the drawing is also wired by the first polysilicon layer, which contributes to the reduction of the layout area.

The layout pattern of FIG. 5 is an example laid out based on the standard SOI layout rule, and the layout pattern of FIG. 8 is an example laid out based on the standard CMOS layout rule. Each λ in the figure indicates a basic unit of length. Here, comparing the cell area of the conventional D flip-flop shown in FIG. 8 with the cell area of FIG. 5 which is an embodiment of the present invention,
(33λ × 61λ) / (44λ × 62λ) = 0.74, which is a 26% reduction in cell area. This is the effect of providing the same material (first polysilicon layer) as the wiring pattern for the low resistance region for the channel region shield.

[Effects of the Invention] As described in detail above, in the present invention, the wiring pattern is formed in the same layer as the channel region shield low resistance region using the same material as the first polysilicon layer forming the channel region shield low resistance region. By forming it, the layout area can be reduced. In particular, this layout area reduction effect becomes more remarkable as the wiring pattern becomes more complicated, that is, as the circuit becomes a large-scale integrated circuit, because the probability of wiring in the first polysilicon layer increases.

[Brief description of drawings]

FIG. 1 is a layout diagram of a memory cell of a 2-port CMOS RAM of the present invention. Figures 2a to 2d show the first
FIG. 2 is a layout pattern diagram obtained by disassembling the diagram for each layer, FIG. 2a being a first polysilicon layer, and FIG. 2b being p ⁺ and n.
⁺ Diffusion layer, FIG. 2c shows a second polysilicon layer, and FIG. 2d shows a metal layer. FIG. 3 is a circuit diagram of FIG. FIG. 4 is a sectional view taken along the line YY 'in FIG. FIG. 5 is a layout diagram of the D flip-flop of the present invention. 6a to 6d
FIG. 6 is a layout pattern diagram in which FIG. 5 is exploded for each layer. FIG. 6a is a first polysilicon layer, and FIG. 6b is p.
^{+ And} n ⁺ diffusion layers, FIG. 6c shows a second polysilicon layer,
FIG. 6d shows the respective metal layers. FIG. 7 is a circuit diagram of FIG. FIG. 8 is a layout diagram of a conventional D flip-flop, and FIG. 9 is a circuit diagram thereof. FIG. 10 is a layout diagram of a memory cell of a conventional 2-port CMOS RAM, and FIG. 11 is a circuit diagram thereof. FIG. 12 is a sectional view taken along the line YY 'in FIG. FIG. 13 is a sectional view of the structure of a conventional insulated gate field effect transistor, and FIG. 14 is a circuit diagram thereof. 1 to 9 ... First polysilicon layer 23 according to an embodiment of the present invention
Wiring pattern, 21 ... P ⁺ diffusion layer, 22 ... N ⁺ diffusion layer, 23
… First polysilicon layer, 24… Second polysilicon layer, 25…
Metal layer, 26 ... Contact hole, 27 ... Via hole, 28 ... Embedded contact.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784 9170-4M H01L 27/06 102 H

Claims (1)

[Claims] 1. A semiconductor integrated circuit using an insulated gate field effect transistor in which a low resistance region for shielding a channel region is provided below a channel region by using the same material as the low resistance region for shielding the channel region. A semiconductor integrated circuit having a wiring pattern arranged in the same layer as the channel region shield resistance region.