JPH06112191A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06112191A
JPH06112191A JP25794192A JP25794192A JPH06112191A JP H06112191 A JPH06112191 A JP H06112191A JP 25794192 A JP25794192 A JP 25794192A JP 25794192 A JP25794192 A JP 25794192A JP H06112191 A JPH06112191 A JP H06112191A
Authority
JP
Japan
Prior art keywords
film
semiconductor device
insulating film
interlayer insulating
sog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP25794192A
Other languages
Japanese (ja)
Inventor
Takashi Nagashima
隆 長嶋
Hideki Harada
秀樹 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Original Assignee
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyushu Fujitsu Electronics Ltd, Fujitsu Ltd filed Critical Kyushu Fujitsu Electronics Ltd
Priority to JP25794192A priority Critical patent/JPH06112191A/en
Publication of JPH06112191A publication Critical patent/JPH06112191A/en
Withdrawn legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

(57)【要約】 【目的】 半導体装置の導電層の間の層間絶縁膜或いは
導電層の表面の平坦化膜の改良に関し、テンシルストレ
スが大きくならず、配線層にダメージを与えない層間絶
縁膜或いは平坦化膜を具備する半導体装置の提供を目的
とする。 【構成】 導電層の間の層間絶縁膜或いは導電層の表面
の平坦化膜として、酸素含有率が30パーセント以上の雰
囲気中で焼成した、骨格中にシラザン結合を有するシリ
コン化合物材料からなる、コンプレッシブな膜ストレス
を有する絶縁膜を具備するように構成する。
(57) [Summary] [Object] Regarding improvement of an interlayer insulating film between conductive layers of a semiconductor device or a flattening film of the surface of the conductive layer, an interlayer insulation which does not increase tensile stress and damages a wiring layer. An object is to provide a semiconductor device having a film or a planarization film. [Composition] An interlayer insulating film between the conductive layers or a flattening film on the surface of the conductive layer is formed of a silicon compound material having a silazane bond in the skeleton, which is baked in an atmosphere having an oxygen content of 30% or more. It is configured to include an insulating film having a reductive film stress.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の導電層の
間の層間絶縁膜或いは導電層の表面の平坦化膜の改良に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in an interlayer insulating film between conductive layers of a semiconductor device or a flattening film on the surface of a conductive layer.

【0002】近年の半導体装置の構造の微細化・多層化
に伴い、半導体基板上に形成されたアスペクト比の高い
段差に絶縁膜を埋め込んで平坦にする技術に対する要求
が益々厳しくなっており、従来平坦化材料として用いら
れてきたシリコン・オン・グラス膜(以下、SOG膜と
略称する)は、平坦化を促進するために膜厚が厚くなる
傾向がある。
With the recent miniaturization and multi-layer structure of semiconductor devices, there has been an increasing demand for a technique for embedding an insulating film in a step having a high aspect ratio formed on a semiconductor substrate and flattening it. The silicon-on-glass film (hereinafter abbreviated as SOG film) that has been used as a planarizing material tends to have a large film thickness in order to promote planarization.

【0003】しかし、SOG膜を用いて下地の配線層の
間を埋め込んで平坦にする場合に、配線層の間隔が狭い
部分ではSOG膜の膜厚が厚くなっている。従来用いら
れているSOG膜のストレスはテンシルストレスであ
り、このSOG膜の膜厚が厚い部分では、配線層の上の
膜厚が薄い部分に比して、テンシルストレスが3倍以上
になっている。
However, when the underlying wiring layers are filled with the SOG film to make it flat, the SOG film is thicker in the portion where the spacing between the wiring layers is narrow. The stress of the SOG film conventionally used is tensile stress. Tensile stress is three times or more in the thick portion of the SOG film compared to the thin portion on the wiring layer. Has become.

【0004】一般に層間絶縁膜のストレスがコンプレッ
シブ或いは弱テンシルの場合には、配線層に与えるダメ
ージが少ないと言われているが、生産性の高い常圧CV
D法により形成した従来の絶縁膜はすべてテンシルスト
レスを有しているため、常圧CVD法により形成した従
来の常圧CVD膜と従来のSOG膜とを組み合わせると
強テンシルストレスを有する層間絶縁膜になるので配線
層に大きなダメージを与えている。
Generally, when the stress of the interlayer insulating film is compressive or weak tensile, it is said that the damage to the wiring layer is small.
Since all the conventional insulating films formed by the D method have tensile stress, the combination of the conventional atmospheric pressure CVD film formed by the atmospheric pressure CVD method and the conventional SOG film results in the interlayer having strong tensile stress. Since it becomes an insulating film, it seriously damages the wiring layer.

【0005】以上のような状況から、配線層にダメージ
を与えない層間絶縁膜を具備する半導体装置が要望され
ている。
Under the circumstances as described above, there is a demand for a semiconductor device having an interlayer insulating film which does not damage the wiring layer.

【0006】[0006]

【従来の技術】従来の半導体装置について図3〜図4に
より詳細に説明する。図3は従来の半導体装置を示す側
断面図、図4は従来の半導体装置の層間絶縁膜に用いる
SOGの構造式を示す図である。
2. Description of the Related Art A conventional semiconductor device will be described in detail with reference to FIGS. FIG. 3 is a side sectional view showing a conventional semiconductor device, and FIG. 4 is a diagram showing a structural formula of SOG used for an interlayer insulating film of the conventional semiconductor device.

【0007】従来の半導体装置の層間の平坦化に一般的
に用いられているSOGは、図4に示すような構造式を
有する、アルコキシシランをゾルゲル法により製造した
もので、焼成雰囲気が窒素雰囲気の場合でも、酸素含有
率が30%以下の雰囲気の場合でも、酸素含有率が30%以
上の雰囲気の場合でも、同様に1×109(dyne/cm2)程度
のテンシルストレスを有している。
The SOG generally used for flattening layers between layers of a conventional semiconductor device is an alkoxysilane produced by a sol-gel method having a structural formula as shown in FIG. 4, and a firing atmosphere is a nitrogen atmosphere. In the case of, the atmosphere having an oxygen content of 30% or less and the atmosphere of an oxygen content of 30% or more also have a tensile stress of about 1 × 10 9 (dyne / cm 2 ). ing.

【0008】このようなSOG膜を用いて下地の配線層
の間を埋め込んで平坦にする場合には、図3に示すよう
に半導体基板11の表面に配線層12を形成し、配線層12の
表面に生じている突起(ヒロック)を防止する突起防止
膜13を全面に形成した後、SOG膜14と常圧CVD 膜15と
を積層して層間絶縁膜を形成しているが、配線層12の間
隔が狭い部分ではSOG膜14の膜厚が厚くなり、テンシ
ルストレスが増大しているために配線層12の上面のSO
G膜14を厚膜化するのが困難になっている。
When such an SOG film is used to fill the space between the underlying wiring layers to make it flat, the wiring layer 12 is formed on the surface of the semiconductor substrate 11 as shown in FIG. After forming the protrusion prevention film 13 for preventing the protrusion (hillock) generated on the surface, the SOG film 14 and the atmospheric pressure CVD film 15 are laminated to form the interlayer insulating film. Since the SOG film 14 becomes thicker in the portion where the space between them is narrower and the tensile stress is increased, the SO on the upper surface of the wiring layer 12 is
It is difficult to make the G film 14 thick.

【0009】[0009]

【発明が解決しようとする課題】以上説明した従来の半
導体装置においては、層間絶縁膜や平坦化膜にテンシル
ストレスの大きなSOGを用いているから、テンシルス
トレスが増大するのでSOG膜を厚膜化するのが困難に
なっており、テンシルストレスが大きくなると層間絶縁
膜や平坦化膜に密着して形成されている配線層にテンシ
ルストレスが加わり断線する恐れがあるという問題点が
あった。
In the conventional semiconductor device described above, the SOG film having a large tensile stress is used for the interlayer insulating film and the flattening film. It is difficult to form a film, and if the tensile stress increases, there is a problem that tensile stress may be applied to the wiring layer that is formed in close contact with the interlayer insulating film and the planarization film, resulting in disconnection. It was

【0010】本発明は以上のような状況から、テンシル
ストレスが大きくならず、配線層にダメージを与えない
層間絶縁膜或いは平坦化膜を具備する半導体装置の提供
を目的としたものである。
Under the circumstances described above, the present invention has an object to provide a semiconductor device having an interlayer insulating film or a flattening film which does not increase the tensile stress and does not damage the wiring layer.

【0011】[0011]

【課題を解決するための手段】本発明の半導体装置は、
導電層の間の層間絶縁膜或いは導電層の表面の平坦化膜
として、酸素含有率が30パーセント以上の雰囲気中で焼
成した、骨格中にシラザン結合を有するシリコン化合物
材料からなる、コンプレッシブな膜ストレスを有する絶
縁膜を具備するように構成する。
The semiconductor device of the present invention comprises:
A compressive film made of a silicon compound material having a silazane bond in the skeleton, which is baked in an atmosphere having an oxygen content of 30% or more, as an interlayer insulating film between conductive layers or a flattening film on the surface of the conductive layer. It is configured to include an insulating film having stress.

【0012】[0012]

【作用】即ち本発明においては、コンプレッシブな膜ス
トレスを有する材料として図2に示すような構造式を有
する、骨格中にシラザン結合を有するSOGを用いるか
ら、このポリマー末端の水素(H) を酸化することによ
り膜が膨張してコンプレッシブな膜ストレスが発生す
る。
In the present invention, since SOG having a silazane bond in the skeleton, which has a structural formula as shown in FIG. 2, is used as a material having a compressive membrane stress, hydrogen (H) at the polymer end is used. Oxidation causes the membrane to swell and compressive membrane stress occurs.

【0013】本発明のシラザン結合を有するSOG膜を
種々の雰囲気内で焼成すると下記の表1に示すように窒
素雰囲気中や酸素含有率が30%以下の雰囲気中の場合に
は0.9 ×109 (dyne /cm2)のテンシルストレス値を有す
るが、酸素含有率が30%以上の雰囲気中の場合には−0.
5 ×109 (dyne /cm2)のコンプレッシブストレス値を有
するようになる。
When the SOG film having a silazane bond of the present invention is fired in various atmospheres, as shown in Table 1 below, it is 0.9 × 10 9 in a nitrogen atmosphere or an atmosphere having an oxygen content of 30% or less. It has a tensile stress value of (dyne / cm 2 ), but it is −0 in an atmosphere having an oxygen content of 30% or more.
It has a compressive stress value of 5 × 10 9 (dyne / cm 2 ).

【0014】[0014]

【表1】 [Table 1]

【0015】このようなシラザン結合を有するSOG膜
からなるSOG膜を導電層の間の層間絶縁膜或いは導電
層の表面の平坦化膜として用いると、ストレス値がマイ
ナスのコンプレッシブストレス値を有するようになるの
で、SOG膜を厚膜化することが可能となり、配線層に
テンシルストレスが加わり断線するのを防止することが
可能となる。
When an SOG film made of such SOG film having a silazane bond is used as an interlayer insulating film between the conductive layers or a flattening film on the surface of the conductive layer, the stress value seems to have a negative compressive stress value. Therefore, it becomes possible to increase the thickness of the SOG film, and it is possible to prevent disconnection due to tensile stress applied to the wiring layer.

【0016】[0016]

【実施例】以下図1により本発明の一実施例について詳
細に説明する。図1は本発明による一実施例の半導体装
置を示す側断面図、図2は本発明による一実施例の半導
体装置の層間絶縁膜に用いるシラザン結合を有するSO
Gの構造式を示す図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to FIG. 1 is a side sectional view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is an SO having a silazane bond used for an interlayer insulating film of the semiconductor device according to an embodiment of the present invention.
It is a figure which shows the structural formula of G.

【0017】本発明による一実施例の半導体装置の層間
の平坦化に用いる材料は、図2に示すような構造式を有
する、シラザン結合を有するSOGで、作用において説
明したように、焼成雰囲気が窒素雰囲気中の場合及び酸
素含有率が30%以下の雰囲気中の場合には従来のSOG
と同様な 0.9×109(dyne/cm2)程度のテンシルストレス
を有しているが、酸素含有率が30%以上の雰囲気中の場
合にはマイナス0.5 ×109 (dyne /cm2)のコンプレッシ
ブストレス値を有するようになる。
The material used for planarizing the layers of the semiconductor device of one embodiment according to the present invention is SOG having a silazane bond having a structural formula as shown in FIG. Conventional SOG in a nitrogen atmosphere and in an atmosphere with an oxygen content of 30% or less
It has a tensile stress of about 0.9 × 10 9 (dyne / cm 2 ) similar to the above, but minus 0.5 × 10 9 (dyne / cm 2 ) in an atmosphere with an oxygen content of 30% or more. To have a compressive stress value of.

【0018】このようなシラザン結合を有するSOG膜
を用いて下地の配線層2の間を埋め込んで平坦にする場
合には、図1に示すように半導体基板1の表面に配線層
2を形成し、突起防止膜3を全面に形成した後、SOG
膜4と常圧CVD 膜5とを積層して層間絶縁膜を形成して
いるが、SOG膜4がコンプレッシブストレス値を有し
ているので、SOG膜4の膜厚を全体的に厚くして配線
層2の間隔が狭い部分でSOG膜4の膜厚が厚くなって
もテンシルストレスが増大することがなくなり、層間絶
縁膜や平坦化膜に密着して形成されている配線層にテン
シルストレスが加わり断線することがなくなる。
When the SOG film having such a silazane bond is used to fill the space between the underlying wiring layers 2 to make it flat, the wiring layer 2 is formed on the surface of the semiconductor substrate 1 as shown in FIG. After forming the protrusion prevention film 3 on the entire surface, SOG
The film 4 and the atmospheric pressure CVD film 5 are laminated to form an interlayer insulating film. However, since the SOG film 4 has a compressive stress value, the thickness of the SOG film 4 is increased as a whole. Therefore, even if the thickness of the SOG film 4 is increased in the portion where the distance between the wiring layers 2 is narrow, the tensile stress does not increase, and the tensile stress is not applied to the wiring layer formed in close contact with the interlayer insulating film or the flattening film. The sill stress is applied and the wire will not break.

【0019】[0019]

【発明の効果】以上の説明から明らかなように、本発明
によれば極めて簡単な材料の選択によりコンプレッシブ
ストレス値を有する層間絶縁膜を備えた半導体装置を製
造することが可能となる利点があり、著しい経済的及
び、信頼性向上の効果が期待できる半導体装置の提供が
可能である。
As is apparent from the above description, according to the present invention, it is possible to manufacture a semiconductor device having an interlayer insulating film having a compressive stress value by selecting an extremely simple material. Therefore, it is possible to provide a semiconductor device which can be expected to have a remarkable economic effect and reliability improvement effect.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明による一実施例の半導体装置を示す側
断面図
FIG. 1 is a side sectional view showing a semiconductor device according to an embodiment of the present invention.

【図2】 本発明による一実施例の半導体装置の層間絶
縁膜に用いるシラザン結合を有するSOGの構造式を示
す図
FIG. 2 is a diagram showing a structural formula of an SOG having a silazane bond used for an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.

【図3】 従来の半導体装置を示す側断面図FIG. 3 is a side sectional view showing a conventional semiconductor device.

【図4】 従来の半導体装置の層間絶縁膜に用いるSO
Gの構造式を示す図
FIG. 4 SO used for an interlayer insulating film of a conventional semiconductor device
Diagram showing the structural formula of G

【符号の説明】[Explanation of symbols]

1は半導体基板、2は配線層、3は突起防止膜、4はS
OG膜、5は常圧CVD 膜、
1 is a semiconductor substrate, 2 is a wiring layer, 3 is a protrusion prevention film, 4 is S
OG film, 5 is a normal pressure CVD film,

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/90 P 7514−4M ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 21/90 P 7514-4M

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 導電層の間の層間絶縁膜或いは導電層の
表面の平坦化膜として、酸素含有率が30パーセント以上
の雰囲気中で焼成した、骨格中にシラザン結合を有する
シリコン化合物材料からなる、コンプレッシブな膜スト
レスを有する絶縁膜を具備することを特徴とする半導体
装置。
1. A silicon compound material having a silazane bond in the skeleton, which is fired in an atmosphere having an oxygen content of 30% or more, as an interlayer insulating film between conductive layers or a flattening film on the surface of the conductive layers. A semiconductor device comprising an insulating film having a compressive film stress.
JP25794192A 1992-09-28 1992-09-28 Semiconductor device Withdrawn JPH06112191A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25794192A JPH06112191A (en) 1992-09-28 1992-09-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25794192A JPH06112191A (en) 1992-09-28 1992-09-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH06112191A true JPH06112191A (en) 1994-04-22

Family

ID=17313339

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25794192A Withdrawn JPH06112191A (en) 1992-09-28 1992-09-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH06112191A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19630342A1 (en) * 1995-08-23 1997-02-27 Mitsubishi Electric Corp Manufacturing method for semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19630342A1 (en) * 1995-08-23 1997-02-27 Mitsubishi Electric Corp Manufacturing method for semiconductor device
US5976626A (en) * 1995-08-23 1999-11-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing thereof
DE19630342C2 (en) * 1995-08-23 2003-06-18 Mitsubishi Electric Corp Manufacturing method of an insulating intermediate layer on a semiconductor substrate

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