JPH06113311A - Digital convergence device - Google Patents

Abstract

(57) [Abstract] [Purpose] In a device for correcting the convergence of a color television receiver, a digital convergence device capable of solving the screen disturbance when the convergence correction data is in an abnormal state and stably operating is provided. The purpose is to provide. [Arrangement] An abnormality in the convergence correction data is detected in the abnormality detection circuit 35 by UNLOCK of the PLL, destruction of the reference data of the frame memory, comparison of the calculation results between the scanning lines, and the video signal is stopped, and the analog correction data is set to 0V. By switching and controlling the D / A reference voltage to 0 V and controlling the convergence correction data to be in a non-correction state when the data is abnormal, stable and high-definition convergence correction can be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital convergence device for correcting the convergence of a color television receiver.

[0002]

2. Description of the Related Art Generally, in a projection type color image receiving apparatus for enlarging and projecting in a screen by using three projection tubes which emit three primary colors, the incident angles of the projection tubes with respect to the screen are different in each projection tube. Therefore, color shift occurs on the screen. The superposition of these three primary colors, or so-called convergence, takes a method in which a convergence correction waveform is created in an analog manner in synchronization with the horizontal and vertical scanning periods, and the size and shape of this waveform are adjusted for adjustment. However, there is a problem in terms of convergence accuracy. Therefore, as a method capable of supporting various signals and having high convergence accuracy, for example, Japanese Patent Laid-Open No.
A digital convergence device disclosed in Japanese Patent Laid-Open No. 130288 has been proposed.

The conventional digital convergence device will be described below. FIG. 6 shows a block diagram of a conventional digital convergence device. This displays a convergence correction pattern such as a crosshatch pattern (shown in FIG. 7) on the screen, digitally writes the convergence correction amount data for each adjustment point into the frame memory, and reads this data D A / A conversion is performed to perform convergence correction.

In FIG. 6, 5 is a read address control unit, 6 is a crosshatch generator, 7 is a video circuit, 8 is a write address control unit, 12 is a control panel, 11 is a reversible counter, 9 is a multiplexer, and 10 is 1 Frame memory, 18 is a register, 29 is a vertical adjustment point processing unit, 14 is a D / A conversion circuit, 15 is a low-pass filter (hereinafter, LP
F), 26 is a scanning line number detection unit, 27 is an adjustment point number setting unit, 28 is a coefficient calculation unit, 16 is an output amplification unit, and 30 is a deflection circuit.

Next, the operation will be described. First,
A horizontal / vertical cycle pulse synchronized with the deflection current cycle is applied to the sync signal input terminal 32 as a sync signal, thereby driving the read address controller 5. The crosshatch generator 6 is driven by using the pulse from the read address controller 5, and the video circuit 7 projects a crosshatch pattern on the projection screen. On the other hand, upon receiving the synchronization signal 32, the address key of the control panel 12 is used to specify a cross point (for example, A in FIG. 7) at a position where convergence correction is required, and the position address is set in the write address control unit 8. Next, the correction amount is written in the one-frame memory 10 through the data reversible counter 11 while looking at the screen with the data write key of the color to be corrected, for example, the red data write key provided on the control panel 12. Usually, the writing in the 1-frame memory 10 is switched and controlled by the multiplexer 9 so as to be performed in the blanking period of the video signal. Therefore, reading is not impaired.

In this way, the same operation is performed at each adjustment point. Next, to read the 1-frame memory 10,
The read address control unit 5 reads out each adjustment point position on the screen, and the read address control unit 5
The vertical adjustment point processing unit 29 performs correction amount processing between the adjustment points in the vertical scanning direction via the register 18 driven by. In order to deal with various signal sources, it is necessary to perform the inter-adjustment point processing according to the number of scanning lines. Therefore, the input synchronization signal 32 is supplied to the scanning line number detection unit 26, detects the number of scanning lines in one field, and is added to the adjustment point number setting unit 27. The number-of-adjustment-points setting unit 27 obtains the number of scan lines N of N = M / (L + 1) number of adjustment points from the number M of scanning lines in one field and the number L of adjustment points in the vertical direction. Added to. In addition to the write address control unit 8 and the read address control unit 5, the operation is switched every N lines.

The output of the vertical adjustment point processing unit 29 which operates as described above is input to the D / A conversion circuit 14, where a signal converted into an analog amount is obtained. The signal between the adjustment points in the horizontal direction is smoothed by the low pass filter (LPF) 15 for the correction amount of the adjustment points in each row, amplified by the output amplification section 16, and then supplied to the convergence yoke 17. Further, the detection signal from the scanning line number detection unit 26 is applied to the deflection circuit 30 as a system switching signal to switch the deflection amplitude and frequency. In this way, each signal source is corrected independently for each adjustment point.

[0008]

However, in the above-mentioned conventional configuration, although the convergence adjustment can be accurately adjusted for each signal source, the correction data is generated because the correction waveform is generated digitally. When an abnormality occurs in the display, a correction waveform having no correlation in the vertical direction is output and the screen is considerably disturbed.

The present invention solves the above-mentioned conventional problems, and an object thereof is to detect an abnormality in correction data and mute a video signal. Further, it aims at suppressing the disturbance of the screen by making the digital convergence correction uncorrected.

[0010]

In order to solve the above-mentioned problems, the digital convergence apparatus of the present invention generates a plurality of convergence adjustment points horizontally and vertically on the screen of a color television receiver to display a cursor. Means for inputting the correction data of each adjustment point in the screen and digitally storing the convergence correction amount of each adjustment point, and a synchronization for inputting the correction data from the storage means to the receiver. Means for reading in synchronization with a signal, means for amplifying the read correction data and supplying it to the correction coil, means for detecting an abnormality in the correction data, and means for muting the video signal by the abnormality detection circuit. It is equipped with.

The present invention further comprises means for generating a plurality of convergence adjustment points in the horizontal and vertical directions on the screen of a color television receiver and displaying the cursor, and inputting correction data for each adjustment point in the screen, Means for digitally storing the convergence correction amount at each adjustment point, means for reading the correction data from the storage means in synchronization with a synchronization signal input to the receiver, and digitally for the read correction data. -Analog conversion (D / A conversion) means, means for amplifying the correction data converted into the analog signal and supplying it to the correction coil, means for detecting an abnormality in the correction data, and the abnormality detection circuit It is provided with a means for switching the analog correction data to 0V.

Further, means for generating a plurality of convergence adjustment points in the horizontal and vertical directions on the screen of the color television receiver and displaying the cursor, and correction data of each adjustment point in the screen are input to input each adjustment point. Means for digitally storing the convergence correction amount, means for reading the correction data from the storage means in synchronization with a synchronization signal input to the receiver, and D / for the read correction data.
A conversion means, amplification means for amplifying the correction data converted into the analog signal and supplying it to the correction coil, means for detecting an abnormality in the correction data, and a reference for the digital-analog conversion by the abnormality detection circuit. It is provided with means for setting the potential to 0V.

[0013]

With the above construction, when the abnormality of the digital convergence correction data is detected, the video signal is muted, the screen is stopped and the image is not displayed, and the analog correction data is set to 0.
By switching to V for no correction of the converter correction, and by setting the reference voltage of the D / A conversion unit to 0 V for no correction of the converter, it is possible to suppress the disturbance of the screen when the correction data is abnormal and to stabilize the correction. Correction can be realized.

[0014]

(Embodiment 1) A first embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1, 2 and 3 are block diagrams of a digital convergence device according to the first embodiment of the present invention.
A block diagram of the main part abnormality detection circuit and a relational diagram of correction data and scanning lines are shown. In FIG. 1, 33 is an address control unit for controlling reading and writing of memory,
Is a vertical operation circuit for performing an operation between adjustment points in the vertical direction, 35 is an abnormality detection circuit for detecting an abnormality in correction data,
A video mute signal generator 36 generates a mute signal for the video signal when the correction data is abnormal. In FIG. 1, components that operate in the same manner as in FIG. 6 of the conventional embodiment are designated by the same reference numerals and description thereof will be omitted.

The operation of the thus constructed digital convergence apparatus of this embodiment will be described below. The address control unit 33 receives the synchronization signal from the synchronization signal input terminal 32, synchronizes the address signal of the input synchronization signal with the frame memory 10, and the crosshatch generation unit 6
For example, a cross hatch pattern (not shown) of 13 rows in the horizontal direction and 9 columns in the vertical direction is generated and displayed on the screen. The frame memory 10 stores data at the intersections of the crosshatch signals. The data from the frame memory 10 is supplied to the vertical direction arithmetic circuit 34, and correction data corresponding to each scanning line between the adjustment points not stored in the frame memory 10 is created. Vertical arithmetic circuit 34
The calculated data from is sent to the abnormality detection circuit 35 and the D / A conversion circuit 14 and converted into an analog amount by the D / A conversion circuit 14 to create a correction waveform. The analog waveform is LPF1.
5, the correction data is smoothed in the horizontal direction. The smoothed data from the LPF 15 is supplied to the amplifier circuit 16 for driving the convergence yoke 17, and the current is amplified. When an abnormality occurs in the correction data or the like, the abnormality detection circuit 35 detects the abnormality in the correction data,
A video mute signal is output from the video mute signal generator to a video processor (not shown) to mute the video signal.
In this way, the disturbance of the screen when the digital convergence correction data is abnormal can be solved by muting the video signal.

Next, the abnormality detection circuit 35 will be described in detail with reference to the block diagram of FIG. In FIG. 2, 37 is a phase locked roof (hereinafter referred to as PLL).
UNLOCK detection circuit, 38 is a frame memory data detection circuit, and 39 is an operation data detection circuit. PLL
The UNLOCK detection circuit 37 outputs an abnormality detection signal when the synchronization signal 32 of the address control unit 33 and the PLL of the address generation unit are in the UNLOCK state. At this time, the output of the correction data is not synchronized with the video signal, so that it is output randomly and the screen is disturbed. Further, the frame memory data detection circuit 38
Detects whether the correction data written in the frame memory has been destroyed by static electricity or the like, and outputs an abnormality detection signal if it has been destroyed. The frame memory detection circuit 3
In 8 operations, a constant value other than the correction data area is written in the frame memory 10 during the vertical blanking period so as not to impair the reading of the correction data, and then the written data reading is always performed during the vertical blanking period. If the data is rewritten, it is determined that the correction data has been destroyed and an abnormality detection signal is output. In addition, the calculation data detection circuit samples the correction data calculation results of the adjustment points in the same column for each vertical line and compares the calculation result data of the upper and lower lines. It is determined that there is a fault and an abnormality detection signal is output. Further, the waveform diagram of FIG. 3 is used as a diagram for explaining the calculation data of the calculation data detection circuit. Assuming that the correction data of the adjustment points A and B shown in FIG. 7 are a and b, the correction data is the correction data in the vertical scanning direction between the adjustment points in the vertical adjustment point processing unit 28 as described in the conventional example. Since the calculation is performed by the linear approximation processing as shown in FIG. 3, the correction amounts of the upper and lower scanning lines have a strong correlation, and assuming that the number of scanning lines between the adjustment points is N, the correction data of the upper and lower scanning lines is calculated. The difference is “(ba) / N”, and the difference between the upper and lower vertical line correction data does not exceed a certain value.

From the above, if even one of the three abnormality detection signals is input to the video mute signal generator, it is determined that the correction data is abnormal and the video signal is muted and the video is stopped.

As described above, according to the present embodiment, when the correction data is in an abnormal state, it is possible to suppress the disturbance of the screen due to the output correction data of the digital converter and suppress it, and it is possible to realize a highly accurate digital convergence correction with stable operation. .

(Embodiment 2) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a block diagram of a digital convergence device according to the second embodiment of the present invention. In FIG. 4, the difference from the first embodiment is that when the correction data is abnormal, the correction data converted into the analog amount is switched to 0 V and the correction data is uncorrected. Reference numeral 41 is a multiplexer for switching between the correction data converted into an analog amount and ground (hereinafter referred to as GND), and 40 is a multiplexer control unit for switching the multiplexer when the correction data is abnormal. In FIG. 4, components operating in the same manner as in FIG. 1 and FIG. 6 of the conventional embodiment are designated by the same reference numerals and the description thereof will be omitted.

The operation of the thus constructed digital convergence apparatus of this embodiment will be described below. Here, the operation of the correction data abnormality detection circuit 35 is the same as that of the first embodiment, and will be omitted. As in the first embodiment, when an abnormality occurs in the Convert correction data or the like, the correction data abnormality detection circuit 35 detects the abnormality, and the multiplexer control unit 40 controls the multiplexer 41 based on the detection result.
By switching the analog correction data that has passed through F15 to GND, the convergence correction is forced to a non-correction state, and the disturbance of the screen is suppressed.

(Embodiment 3) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 is a block diagram of a digital convergence device according to the third embodiment of the present invention. In FIG. 5, the difference from the second embodiment is that when the correction data is abnormal, D
This is a point of controlling the reference voltage of the / A converter. 42 is a D / A for setting the reference voltage of the D / A to 0 V when the correction data is abnormal.
It is a reference voltage control unit. Note that in FIG. 5, the elements that operate in the same manner as in FIG. 1 and FIG. 6 of the conventional embodiment are denoted by the same reference numerals and the description thereof will be omitted.

The operation of the thus constructed digital convergence apparatus of this embodiment will be described below. Here, the operation of the correction data abnormality detection circuit 35 is the same as that of the first embodiment, and will be omitted. Further, as in the case of the first embodiment, when an abnormality occurs in the Conver correction data or the like, the correction data abnormality detection circuit 35 detects the abnormality, and D / D based on the detection result.
The A reference voltage control unit 42 sets the D / A reference voltage to 0V.
By controlling to, the correction data which is the output of the D / A conversion unit is forced to 0V even if abnormal correction data is input to the D / A conversion unit, and the convergence correction is set to the non-correction state. Suppress the disorder.

In each of the first, second and third embodiments, the projection type color image receiver has been described for easy understanding, but it is also effective for the shadow mask type direct view type image receiver. Needless to say.

[0027]

As described above, according to the present invention,
When abnormal correction data is output, the disturbance of the screen can be suppressed by muting the video signal, so that the correction data can be stabilized and highly accurate correction can be realized.

Further, when the PLL is in the UNLOCK state, it is possible to avoid a situation in which random addresses are output, correction data having no correlation is output and the screen is disturbed, and when the data in the frame memory is rewritten. In addition, the disturbance of the screen can be suppressed, and the disturbance of the screen can be suppressed even when an abnormal state is found in the vertical calculation unit, the correction data can be stabilized, and highly accurate correction can be realized.

As described above, according to the present invention, when abnormal correction data is output, the disturbance of the screen can be suppressed by muting the video signal, so that the correction data can be stabilized and highly accurate. Can be corrected.

Further, according to the present invention, when abnormal correction data is output, the disturbance of the screen can be suppressed by switching the correction data to the non-correction data, so that the correction data can be stabilized and highly accurate correction can be realized. it can.

Further, according to the present invention, when abnormal correction data is output, the reference voltage at the time of D / A conversion of the correction data is set to 0 V to make the correction data uncorrected, thereby disturbing the screen. Since it can be suppressed, the correction data can be stabilized, and highly accurate correction can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital convergence device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of an abnormality detection circuit in the digital convergence device according to the first embodiment of the present invention.

FIG. 3 is a block diagram of an abnormality detection circuit in the digital convergence device according to the first embodiment of the present invention.

FIG. 4 is a block diagram of a digital convergence device according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a digital convergence device according to a third embodiment of the present invention.

FIG. 6 is a block diagram of a conventional digital convergence device.

FIG. 7 is a display screen diagram for explaining the operation of a conventional digital convergence device.

[Explanation of symbols]

 6 Crosshatch Generator 10 Frame Memory 14 D / A Converter (Digital / Analog Converter) 15 LPF 16 Amplification Circuit 17 Convergence Yoke 32 Sync Signal 33 Address Generator 34 Vertical Operation Circuit 35 Abnormality Detection Circuit 36 Video Mute Signal Generation Circuit 37 PLL UNLOCK Detection Circuit 38 Frame Memory Data Detection Circuit 39 Operation Data Detection Circuit 40 Multiplexer Control Section 41 Multiplexer 42 D / A Reference Voltage Control Section

Claims (6)

[Claims] 1. A means for generating a plurality of convergence adjustment points in the horizontal and vertical directions on the screen of a color television receiver and displaying the cursor, and correction data for each adjustment point in the screen are input, and each adjustment point is input. Means for digitally storing the convergence correction amount, means for reading the correction data from the storage means in synchronization with a synchronization signal input to the receiver, and amplification and correction for the read correction data. A digital convergence device comprising: means for supplying a coil for use; means for detecting an abnormality in correction data; and means for muting a video signal by the abnormality detection circuit. 2. The abnormality detection means is phase locked
The digital convergence apparatus according to claim 1, wherein the loop-unlock detection is performed. 3. The digital convergence device according to claim 1, wherein the abnormality detecting means is adapted to detect the correction data of the memory serving as the storage means. 4. The digital convergence device according to claim 1, wherein the abnormality detecting means is adapted to detect a difference between correction data of scanning lines which continue in a vertical direction. 5. A means for generating a plurality of convergence adjustment points in the horizontal and vertical directions on the screen of a color television receiver and displaying the cursor, and correction data for each adjustment point on the screen are input, and each adjustment point is input. Means for digitally storing the convergence correction amount, means for reading the correction data from the storage means in synchronization with a synchronization signal input to the receiver, and digital-analog conversion of the read correction data. Means for amplifying the correction data converted into the analog signal and supplying the correction data to the correction coil, a means for detecting an abnormality in the correction data, and the correction data converted into the analog signal by the abnormality detection circuit. A digital convergence device provided with a means for switching to 0V. 6. A means for generating a plurality of convergence adjustment points in the horizontal and vertical directions on the screen of a color television receiver and displaying the cursor, and inputting correction data for each adjustment point in the screen and inputting each adjustment point. Means for digitally storing the convergence correction amount, means for reading the correction data from the storage means in synchronization with a synchronization signal input to the receiver, and digital-analog conversion of the read correction data. Means for amplifying the correction data converted into the analog signal and supplying it to the correction coil, a means for detecting an abnormality in the correction data, and a reference potential for the digital-analog conversion by the abnormality detection circuit. 0
A digital convergence device having means for setting V.