JPH0611486Y2 - Reset status detection circuit - Google Patents

Description

[Detailed Description of the Invention] (Industrial field of application) The present invention is a test for connecting to a control circuit under test when a control circuit such as an electronic logic control circuit, which is generally used, is prototyped or tested. The present invention relates to a reset detection circuit included in a part of an apparatus, and more particularly to a reset state detection circuit capable of storing a reset occurrence location by distinguishing between a control circuit inside and outside regarding a reset operation.

(Prior Art) Conventionally, a control circuit to be tested by connecting to an automatic measuring device or the like has a built-in central processing unit (CPU) and the like, and most of them have a reset 11 at power-on as shown in FIG. , C
Reset generator circuit 1 for PU runaway prevention reset, etc.
I have two and thirteen. It also has a reset input terminal RSI so that it can be reset from the outside. Further, when a reset is applied to the control circuit, a reset output terminal RSO is provided so that the external related equipment can be reset.

When performing a test by connecting to such a control circuit, there are various demands such as distinction of the place where the reset cause occurs. Therefore, the circuit 1 that combines the outputs of the internal reset circuit into one.
5 and an internal reset output terminal RST for taking out its output to the outside.

(Problems to be solved by the invention) As described above, in the conventional test apparatus, when the panel of the control circuit as described above is tested, whether or not the reset is due to the inside of the panel or the outside There is a problem that I do not know even if I want to know if it is from the source. In addition, it is very effective for studying the operation if the inside and outside are recorded. Further, during the test of the control logic circuit panel, if it is desired to perform different operations by the internal reset and the external reset, it is necessary to determine which of the resets is to be transmitted to the logic circuit by some method. Further, in order to directly input the recorded reset output signal to another circuit, it may be necessary to freely control the output signal. Some of them are provided with the internal reset output terminal RST shown in FIG. 2 in order to cope with such a demand, but this is not enough, and it is not necessary to incorporate a circuit which satisfies the above demand into the panel itself. It was necessary and often wasted when it came to actual operation later, so there was a problem such as waste.

The purpose of the present invention is to solve such a problem and to know whether the reset operation of the control circuit is performed by the internal reset or the external reset in the test device connected to the control circuit. It is an object of the present invention to provide a reset path detection circuit capable of performing the above.

(Means for Solving the Problems) In order to achieve the above object, the reset path detection circuit of the present invention is connected to a control circuit to be tested having a reset input terminal (RSI) and a reset output terminal (RSO). In the reset state detection circuit, a unique reset circuit 7 for sending a reset signal to the control circuit, an output of the reset circuit 7 connected to a reset input terminal (RSI) of the control circuit, and a reset output terminal of the control circuit Two outputs of the (RSO) are used as two inputs, and when a signal is applied to the two inputs at the same time, it is determined that a reset pulse is input from the outside of the control circuit, and the control of the two inputs is performed. Circuit reset output terminal (R
SO)) is provided in the control circuit to determine that a reset pulse has occurred, and a storage means for storing the result of the determination.

Further, the discriminating means is a flip-flop 1 with a reset terminal.
The reset terminal R ₁ is provided with the output of the reset circuit 7, and the clock terminal (CK) is provided with the signal of the reset output terminal (RSO) of the control circuit being inverted, and the storage means is the set terminal and the reset terminal. The output of the flip-flop with reset terminal 1 is given to the data terminal D ₂ of the flip-flop with lock 2 and its clock terminal CK ₂
The reset output terminal (RSO) signal of the control circuit is applied to the.

(Example) Next, this invention is demonstrated with reference to drawings.

FIG. 1 is a circuit explanatory view showing a circuit of an embodiment according to the present invention together with a relevant portion of a logic circuit of a control circuit to be tested.

FIG. 2 is a circuit diagram showing a conventional reset state detection circuit.

FIG. 3 is a timing chart showing the operation of the circuit of the embodiment shown in FIG.

In FIG. 1, a part left from X ... X shown by a dotted line in the drawing shows a part of a logic panel of a control circuit to be tested, and a part right from Y ... Y is included in the test apparatus. 3 shows a reset state detection circuit of the embodiment.

In the figure, a flip-flop 1 with reset terminal (hereinafter referred to as the first FF) 1 is used to determine whether the reset pulse is generated inside the control circuit (logic panel) or the reset pulse from the outside. _A high potential (hereinafter referred to as "H") is always applied to ₁ and the reset terminal R ₁ is connected to the output of the reset circuit 7 inside the test apparatus. Also, the first FF1
The clock terminal CK ₁ is connected to the reset output terminal RSO of the logic panel from the input terminal 8 via the notch circuit 3.

A flip-flop (hereinafter, referred to as a second FF) 2 with a set terminal and a reset terminal in the figure stores the contents of the output terminal Q ₁ of the _first FF ₁ , and the data terminal D ₂ is the first FF.
1 is connected to the output terminal Q ₁ . The clock terminal CK ₂ is connected to the input terminal 8.

The output of a NAND circuit 4 which receives two signals, a chip select signal (hereinafter referred to as a CS signal) CS from a control circuit and a data signal (hereinafter referred to as a DA signal), at a set terminal S ₂ of the _second FF2. Is given, and the reset terminal R
A notch circuit 6 for inputting CS signal and DA signal to ₂
The output of the NAND circuit 5 which receives the output of the above is given.

Reference numeral 9 is a reset output terminal for applying the output of the reset circuit 7 to the logic panel for resetting.
Is an output terminal for taking out the Q ₂ output of the _second FF ₂ to the outside and recording it in the recording device, or for controlling other related equipment.

Next, the operation of this embodiment will be described.

For example, when a negative pulse is output as a reset signal from the reset circuit 7 of the test apparatus, the 1FF1 is reset, the terminals Q ₁ is a lower potential (hereinafter, referred to as "L".). At the same time, the negative pulse of the reset circuit 7 is the output terminal 9 of the test equipment and the input terminal RS of the logic panel.
Since it is given to the input terminal 8 of the test apparatus through I, the not-nor circuit 14 and the output terminal RSO of the logic panel, this is inverted by the not circuit 3 and given to the clock terminal CK ₁ of the _first FF1. At the same time, the second FF
Since the signal of the input terminal 8 is given to the clock terminal CK ₂ of No. 2 as it is, the second FF ₂ reads the Q ₁ output of the first FF ₁ at the rising of the waveform when the reset is released and the Q ₂ output of the _second FF ₂ becomes “L”. "It becomes.

The waveform of each part when the reset pulse is applied from the reset circuit 7 is shown between the times t _{0 and} t ₁ in FIG. Further, when a reset pulse is generated in the reset circuits 11 and 12 in the logic panel of the control circuit, the input terminal 8 of the test apparatus is output through the output terminal RSO of the logic panel.
To the reset terminal R ₁ of the _first FF1 and the reset pulse is not applied to the reset terminal R ₁ of the _first FF1 and remains at "H". The Q1 output of the _first FF1 becomes "H", and then the second FF2 reads the output Q1 of the _first FF1 at the rising edge of the waveform of the output terminal RSO and the output Q2 of the _second FF2 becomes "H".

The situation when the reset pulse occurs inside the logic panel is shown at times t _{1 to} t ₂ in FIG.

Thus, the Q ₂ output of the _second FF2 becomes "L" when the reset pulse is given from the outside of the control circuit, and becomes "H" when the reset pulse is generated from the inside,
From any one of the next to the occurrence of the reset pulse, the second
FF2 holds and stores the state.

Therefore, the Q ₂ output of the _second FF ₂ can be recorded in an external recording device, or can be used as a control signal for resetting other devices.

Further, in the circuit of the present embodiment, the AND circuit 4 which receives the chip select signal CS and the control data signal DA of the control circuit as input.
₂ is input to the set terminal S ₂ of the _second FF2, and the output of the AND circuit 5 which receives two signals of the DA signal inverted by the not circuit 6 and the CS signal is input to the reset terminal R ₂ of the _second FF2. when the pulse is given as Yotsute CS signal to be an input, the the first 2FF2 by excisional Q ₂ output if the DA signal is "H" at the "H", then the DA signal is "L" If so, the second FF2 can be reset and the Q ₂ output can be made "L". Therefore advance the timing of on the basis of the integrated DA signal to the program CS signal Q ₂ 'output "H", "L" freely changed, control of other equipment taken out Q ₂ output from the output terminal 10 to the outside Can be used for

(Effect of the Invention) As described above, the present invention takes two signals, that is, the reset input signal and the reset output signal of the control circuit to be tested, as long as the two signals have the reset pulse at the same time.
The reset pulse is generated outside the control circuit, and when there is a reset pulse only in the reset output signal of the control circuit, it has a means for judging that the reset pulse is generated internally, Moreover, by having a means for storing the contents, it is possible to determine whether the reset of the control circuit is the reset caused by the inside or the reset caused by the outside. There is an effect that it can be taken out as an output and recorded externally, and can also be used for controlling other related equipment.

In the above embodiment, when the CS signal and the DA signal from the control circuit are added, a circuit for freely changing the stored contents of the storing means is added, so that the reset of the control circuit is Independent control signals that are not related to each other can be output, and there is an effect that a versatile control signal convenient for various tests can be obtained.

[Brief description of drawings]

FIG. 1 is an explanatory circuit diagram showing a circuit of an embodiment of the present invention connected to a control circuit. FIG. 2 is a circuit diagram showing a part of a control circuit train tested by the embodiment shown in FIG. FIG. 3 is a timing chart showing the circuit operation of the embodiment of FIG. 1 ... flip-flop with reset terminal (1st FF) 2 ... set terminal, flip-flop with reset terminal (2nd FF) 3, 6 ... note circuit 4, 5 ... NAND circuit 7, 11, 12, 13 ... reset circuit 8 ... Input terminal 9 ... Reset output terminal of tester 10 ... Output terminal 14, 15 ... Not-nor circuit

Claims (2)

[Scope of utility model registration request] 1. A reset state detection circuit having a reset input terminal and a reset output terminal, the reset state detection circuit being connected to a control circuit to be tested, and a unique reset circuit for sending a reset signal to the control circuit; The output of the reset circuit connected to the reset input terminal of the circuit and the output of the reset output terminal of the control circuit are two inputs, and a case where a signal is applied to the two inputs at the same time of the control circuit Determining means for determining that a reset pulse has been input from the outside, and determining that a reset pulse has occurred inside the control circuit when a signal input from only the reset output terminal of the control circuit among the two inputs meets. And a storage unit for storing the result of the determination, wherein the determination unit is a reset of a flip-flop with a reset terminal. Providing an output of said own reset circuit preparative terminal, a reset state detection circuit, characterized in that providing inverts the signal at the reset output terminal of the control circuit to the clock terminal. 2. The storage means is configured such that an output of the flip-flop with a reset terminal is given to a data terminal of a flip-flop with a set terminal and a reset terminal, and a reset output terminal signal of the control circuit is given to its clock terminal. The reset state detection circuit according to claim 1, characterized in that the utility model is registered.