JPH0612254A - Information processor - Google Patents

Abstract

PURPOSE:To provide the information processor arbitrarily delaying the execution speed of a system by inserting an idle cycle to an instruction execution cycle. CONSTITUTION:This processor is provided with a CPU 1, first means 3 synchronized with a clock generator 2 of clocks supplied to this CPU 1 so as to generate the signal of prescribed time width in the prescribed cycle set in advance by using a frequency dividing ratio setter 31 and a frequency divider 32, and second means 4 composed of first and second flip-flops 41 and 42 and a NAND gate 43 to insert the idle cycle to the processing cycle of the CPU 1 based on the output signal of this first means 3 and by temporarily stopping the instruction execution sequence of the CPU 1, the execution speed of the system is delayed just for prescribed time. Further, either of or both of the cycle and time width of the signal generated by the first means 3 are set by a third means 5 composed of a trigger circuit 51, count value setter 52 and counter 53.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a function of delaying the processing speed of a CPU section.

[0002]

2. Description of the Related Art A conventional (not shown) information processing apparatus is a C
In order to delay the processing speed of PU, the clock frequency given to this CPU is changed, or when a peripheral device with a slow speed is used, it is waited by software and CPU processing is temporarily stopped. Was being done.

However, if the clock frequency given to the CPU is changed, it may be necessary to change the design of the timing circuit of the CPU, or if software is required, change the software. I need.

Further, in the conventional method of waiting for time by using the wait function of the CPU, the CPU is waited at that timing only when the I / O access with the slow access time is performed. Therefore, there is a drawback that the execution speed of the information processing apparatus, that is, the system cannot be arbitrarily delayed.

Therefore, description will be given below in accordance with an actual example.

First, what is meant by "arbitrarily slowing down the execution speed of the information processing apparatus or system regardless of the instruction execution sequence of the CPU" will be described.

As is well known, in a microprocessor system, the system performance (processing speed) is the same as C
When the PU and the same program are executed, it depends on the frequency of the clock at which the system is operating.

That is, in a general microprocessor (for example, μPD780C), the execution sequence of the program fetches one instruction from the memory, decodes the type of the instruction inside the CPU, and provides a corresponding processing function to it. Repeat the cycle of subsequent executions.

Further, one instruction execution sequence consists of several bus cycles.
Each bus cycle performs one simple operation. Therefore, the system is continuously executing and operating by combining these bus cycles (for example, memory read access).

For example, looking at the basic bus cycle when the CPU is the μPD780C, this basic bus cycle consists of five types of bus cycles, and one instruction always starts with the first instruction fetch cycle.

After that, the bus cycle that occurs subsequently differs depending on the type of the instruction fetched into the CPU.

Alternatively, depending on the instruction, after the instruction execution is completed only in this instruction fetch cycle,
In some cases, the next instruction fetch cycle occurs.

Therefore, what can be said here is that the sequence of bus cycles generated depending on the type of instruction execution is uniformly determined.

In such a system, when a specific application program is executed, the system clock frequencies are the same, and if the executed programs are the same, the processing is completed in the same time. be able to.

Under these circumstances, the processing speed of the microprocessor used in the personal computer system is increasing year by year.

The mechanism for improving the performance makes it possible to operate at a higher clock frequency than the following a).

B) The number of clock cycles for executing one instruction is reduced. There are two types.

In recent years, the system has also been designed to operate at its maximum speed following the improvement in the performance of such microprocessors.

However, depending on the application, inconvenience may occur if the processing speed is simply increased.

For example, some application programs are better as the execution speed is faster, such as business software, and some are not usable when the execution speed is changed, such as game software. (When it becomes faster, it becomes impossible to operate the action game and the like.) In this case, a means for lowering the processing speed of the system to the level before the performance improvement by some method is required, and the following means can be considered.

1) A mode for lowering the clock frequency of the microprocessor is provided.

This is mainly conceivable in the case of a) of the above performance improvement, in which the clock frequency has a mode,
It has a mode of operating at the same clock frequency as before the performance improvement.

2) Two microprocessors themselves are provided (duplication of CPU).

This is mainly conceivable in the case of b) of the above performance improvement, and since the instruction execution sequence itself is shortened, the microprocessor before improvement is installed in the system, and the microprocessor is installed. It is used by switching.

However, these methods have a problem that the system scale is increased due to high cost and duplication of the CPU, and when two types of CPU clocks are supported, two types of timing designs are required. .

On the other hand, in a general microprocessor, D
In order to give the right to use the MA transfer or the external bus master, an idle cycle between one bus cycle and a bus cycle that occurs thereafter (a data and address bus is normally used in a cycle in which no CPU is operating) Many of them have a function of floating and inserting a control signal output from the CPU).

Generally, this function is called "bus request function".
Alternatively, it is called "hold function".

This "bus request function (hold function)" can be operated by inputting a bus request signal (hold request signal) to a bus request terminal (hold terminal) provided in the microprocessor.

Therefore, by using such a "bus request function (hold function)", an idle cycle can be inserted between the bus cycles, and without changing the clock frequency. Instruction execution time can be increased.

For example, when controlling the processing speed of the system using such a "bus request function (hold function)", the control method is to make the average operating speed of the system as close as possible before performance improvement. As the bus request signal (hold request signal), a signal that is active for a fixed period of time is generated, and this signal is input.

As a result, in the system, an idle cycle of a fixed number of clocks is inserted between bus cycles at fixed intervals.
The execution speed of the system can be reduced accordingly.

In a practical example, in order to reduce the processing speed by 20%, a bus request signal (hold) is inserted so that an idle cycle of 20 clocks is inserted for 100 clocks of the total number of instruction execution bus cycles. A request signal) may be generated.

[0033]

SUMMARY OF THE INVENTION The present invention focuses on the "bus request function (hold function)" of this microprocessor, and inputs the signal as described above to the information processing apparatus or system. It is intended to slow down the operating speed of, and thereby realizes compatibility with the system before performance improvement.

As a result, when the "bus request function (hold function)" is used as in the present invention, an idle cycle is inserted between bus cycles, but at other timings (for example, Since the clock cycle time etc. are not changed, the design is easy, and there is no need to duplicate the CPU, and cost increase can be minimized.

Therefore, in order to solve the above-mentioned problems, an object of the present invention is to change the idle cycle at any time and at any time without changing the peripheral circuit or software of the CPU unit to the instruction execution bus of the CPU. By inserting into the cycle regardless of the instruction execution sequence of the CPU part,
An object is to provide an information processing device capable of arbitrarily delaying the execution speed of the system.

[0036]

In order to solve the above problems, an information processing apparatus according to the present invention includes a CPU and a CPU.
A first means for generating a signal having a predetermined time width in a predetermined cycle, which is synchronized with a clock supplied to the CPU, and the CPU based on the output signal of the first means.
And a second means for inserting an idle cycle into the processing cycle of 1., and by temporarily suspending the instruction execution sequence of the CPU, the execution speed of the system is delayed by a predetermined time.

The information processing apparatus of the present invention is the first
And a third means for setting either one or both of the period and time width of the signal generated by the means.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An information processing apparatus according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a time chart of the information processing apparatus according to the embodiment of the present invention.

3 to 7 show a general CPU (μPD78
It is a time chart which shows the basic bus cycle of 0C).

FIG. 8 shows a general CPU (μPD780
9 is a time chart showing a bus request / bus acknowledge cycle operation (insertion operation of an idle cycle) of C).

An information processing apparatus according to one embodiment of the present invention is
As shown in FIG. 1, 1 is a bus request signal input terminal 6
And a CPU provided with a bus acknowledge signal output terminal 7,
Is a clock generator, 3 is a frequency division ratio setter 31 and a frequency divider 32
And a first flip-flop 4
1st and 2nd flip-flop 42 and NAND gate 43
And a third means 5 having a trigger circuit 51, a count value setting device 52 and a counter 53.

Further, 101 is a bus acknowledge signal, 1
02 is a clock signal, 131 is a frequency division ratio setting signal, 132
Is a divided clock signal, 141 is a bus request signal, 1
42 is a flip-flop output signal, 143 is a NAND gate output signal, 151 is a trigger signal, 152 is a count value setting signal, and 153 is a counter output signal.

Next, the operation of the information processing apparatus according to the embodiment of the present invention will be described with reference to FIGS.

The clock generator 2 of the information processing apparatus according to the embodiment of the present invention uses the operation clock signal 102 of the CPU 1.
Are continuously generated, and the CPU 1 is operating at this clock rate.

This clock signal 102 is also used by the frequency divider 3
2 is also input, and the frequency divider 32 is the frequency division ratio setter 31
With the division ratio setting signal 131 output from the clock signal 1
02 is divided and a divided clock signal 132 is output. (In one embodiment of the present invention, it is shown in FIG. 2 that the division ratio is set to divide by 16.) The divided clock signal 132 is input to the clock input CK of the first flip-flop 41. In addition, the first flip-flop 41
Data input is connected to GND, the bus request signal 141 (active low) is output from the output Q of the first flip-flop 41 to the bus request signal input terminal of the CPU 1 at the rising edge timing of the divided clock signal 132. 6 is input.

On the other hand, the CPU 1 to which the bus request signal 141 is input recognizes the bus request signal 141 at the timing shown in FIG. 8, and immediately after the completion of the currently executed basic bus cycle, the idle cycle starts to be inserted.
At the same time, the bus acknowledge signal (active low)
101 is output from the bus acknowledge signal output terminal 7 of the CPU 1.

The bus acknowledge signal (active low) 101 is input to the trigger circuit 51, and the trigger signal synchronized with the falling edge of the bus acknowledge signal 101 (active low) is input by using the clock signal 102 which is input at the same time. 151 is input to the counter 53, the counter 53 is reset, and at the same time, the counting operation is started.

The counter 53 counts the clock signal 102 up to the count value set based on the count value setting signal 152 output from the count value setting unit 52,
As shown in FIG. 2, a counter output signal 153 that is at a low level is output until a predetermined counting operation is completed after the trigger signal 151 is input. (In the present embodiment, the count value is shown in FIG. 2 as having 5 clocks set by the count value setting unit 52.) The counter output signal 153 is input to the data input D of the second flip-flop 42. An inverted signal is output from the output XQ of the second flip-flop 42 in synchronization with the rising edge of the clock signal 102 that is input and applied to the clock input CK of the second flip-flop 42.

Further, the counter output signal 153 and the second flip-flop output signal 142 are input to the 2-input NAND gate 43 to take the NAND logic, and as shown in FIG. 2, the timing when the counter 53 completes the count. It becomes the NAND gate output signal 143 (strobe signal) output at.

The NAND gate output signal 143 (strobe signal) is input to the preset PR of the first flip-flop 41, and the first flip-flow 41 is preset at this timing to inactivate the bus request signal 141 (high level). To

When the bus request signal 141 becomes inactive, the CPU 1 recognizes it at the rising edge of the clock and restarts the instruction execution from the next clock cycle, and the insertion of the idle cycle is completed accordingly. Bus acknowledge signal 1 to indicate that
01 also becomes inactive. (Actually, the bus acknowledge signal 101 becomes inactive half a clock before the instruction execution cycle is started.) The bus acknowledge signal 101 is input to the trigger circuit 51, but the trigger circuit 51 causes the bus acknowledge signal 101 to be input. Since it does not operate at the rising edge of, the trigger signal is not generated at this timing.

As described above, a series of operations in which the idle cycle is inserted occurs, and thereafter the instruction execution is started again. Since this operation occurs at each rising edge of the divided clock, the idle cycle is inserted. The cycle is the same as the cycle of the divided clock signal 132.

The clock value into which the idle cycle is inserted by one operation depends on the count value of the counter 53. (In one embodiment of the present invention, the count value is 5 clocks, and the number of idle cycles inserted is 7 clocks.) The difference between the count value of the counter 53 and the number of idle cycles inserted is the bus request. This is because it takes 2 clocks after the signal 141 becomes inactive until the CPU 1 recognizes it and actually starts executing the instruction.

In such an embodiment of the present invention, an idle cycle of 7 clocks is inserted in a cycle of 16 clocks regardless of the instruction execution sequence.
The operating speed of the system can be reduced by about 44%.

As a result, by using the "bus request function (hold function)" as in the embodiment of the present invention, the idle cycle is inserted at an arbitrary period and at an arbitrary time to control the operating speed of the system. Therefore, the idle cycle is only inserted and there is no need to change other timings (such as clock cycle time), which simplifies the design and eliminates the need for CPU duplication, which minimizes cost increase. You can keep it to the limit.

In the embodiment of the present invention, the frequency division ratio of the clock that determines the cycle for inserting the idle cycle and the count value of the clock that determines the insertion time are respectively set to the frequency division ratio setter 31 and the count value setter 52. However, these setting devices may be set in the application software in advance before being activated by the CPU 1, or may be manually set by a switch or the like, and fixed values are given. But it's okay.

In the basic bus cycle of the μPD780C which is a general CPU, as shown in FIGS. 3 to 7, the CPU repeatedly executes an instruction execution bus cycle starting from the instruction fetch cycle shown in FIG. 3 to execute an instruction. .

On the other hand, μPD780 which is a general CPU
In the bus request operation of C, as shown in FIG. 8, when the bus request signal (BUSRQ) becomes active (low level), an idle cycle (TX cycle) is inserted between the bus cycles. It is shown that.

At this time, the CPU outputs a signal (bus acknowledge signal) indicating that the CPU has received the bus request signal and entered the idle cycle.

[0062]

As described above, according to the information processing apparatus of the present invention, the processing speed of the CPU can be arbitrarily delayed without changing the peripheral circuit or software of the CPU.
This has the effect of arbitrarily changing the system execution speed.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a time chart of the information processing apparatus according to the embodiment of the present invention.

FIG. 3 is a time chart showing a basic bus cycle of a general CPU.

FIG. 4 is a time chart showing a basic bus cycle of a general CPU.

FIG. 5 is a time chart showing a basic bus cycle of a general CPU.

FIG. 6 is a time chart showing a basic bus cycle of a general CPU.

FIG. 7 is a time chart showing a basic bus cycle of a general CPU.

FIG. 8 is a time chart showing a bus request / bus acknowledge cycle operation (insertion operation of an idle cycle) of a general CPU.

[Explanation of symbols]

 1 CPU 2 Clock (Clock Generator) 3 First Means 4 Second Means 5 Third Means 6 CPU (Bus Request Signal Input Terminal) 7 CPU (Bus Acknowledge Signal Output Terminal) 31 First Means (Division) Ratio setter) 32 1st means (frequency divider) 41 2nd means (1st flip-flop) 42 2nd means (2nd flip-flop) 43 2nd means (NAND gate) 51 3rd Means (trigger circuit) 52 Third means (count value setting device) 53 Third means (counter) 101 CPU (bus acknowledge signal) 102 Clock (clock signal) 131 First means (dividing ratio setting signal) 132 first means (divided clock signal) 141 second means (bus request signal) 142 second means (flip-flop output signal) 143 second means (NAND gate output signal) 151 Third means (trigger signal) 152 Third means (count value setting signal) 153 Third means (counter output signal)

Claims (2)

[Claims] 1. A CPU, a first means for generating a signal synchronized with a clock supplied to the CPU and having a predetermined time width at a predetermined cycle, and an output of the first means. A second means for inserting an idle cycle into the processing cycle of the CPU based on a signal, and temporarily suspending the instruction execution sequence of the CPU,
An information processing apparatus, wherein the execution speed of the system is delayed by a predetermined time. 2. A third means for setting either one or both of the period and time width of the signal generated by the first means.
The information processing apparatus according to claim 1, further comprising: