JPH0612260A - Interrupt processing method and apparatus - Google Patents

Abstract

(57) [Summary] [Purpose] Improve the interrupt processing efficiency for interrupts with multiple types of procedures by recognizing and registering the next interrupt when processing the interrupt currently occurring. It is an object of the present invention to provide an interrupt processing method and device capable of performing the above. [Structure] For a plurality of types of interrupts in which the interrupt generation order is determined, the interrupt generation order is stored in an interrupt order table 8, and the information stored in the table 8 is referred to Recognize the interrupt that occurs next to the current interrupt process. Then, the recognized processing address for the next interrupt that occurs is set in the interrupt table 2
Register with. As a result, when the next interrupt occurs, the interrupt processing is automatically started from the processing address corresponding to the interrupt.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is
The present invention relates to an interrupt processing method and device for branching to an address corresponding to the interrupt and performing interrupt processing.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a conventional interrupt processing system.

In FIG. 4, 401 is a CPU (central processing unit), 402 is an interrupt table provided in the memory 403, and 404 is an apparatus interrupt processing unit for the external device 406 provided in the interrupt table 402 of the memory 403. is there. An external device 406 generates an external interrupt to the CPU 401. When an external interrupt 407 is generated from the external device 406 in this state, the interrupt table 402 is pointed to by the register of the CPU 401. 412
Indicates the entry with the interrupt number “2” in the interrupt table 402, and this entry 412 points to the device interrupt processing unit 404. This state is indicated by an arrow 413.

Here, the processing procedure for the external interrupt 407 generated from the external device 406 will be described. Now, when the external device 406 generates an external interrupt 407 to the CPU 401 due to I / O completion or the like, the CPU 401 outputs the instruction being executed. After stopping, the register in the CPU 401 is referred to and the address of the interrupt table 402 is obtained as indicated by 411. Then, the CPU 401 uses the external interrupt 4
The interrupt number associated with No. 07 (or the interrupt number automatically generated by the CPU 401 by the external interrupt 407) is recognized, and the corresponding number (No. 2 in this description) is used as an index to make the entry 41 of the interrupt table 402.
Ask for 2. Thus, the address of the device interrupt processing unit 404 registered in this entry 412 (4 in FIG.
(Indicated by 13), and execution of the program is transferred to this address.

As a result, control is transferred to the device interrupt processing unit 404, and the external interrupt 40 generated from the external device 406 is generated.
7 will be processed by the device interrupt processing unit 404. After the device interrupt processing unit 404 processes the external interrupt 407 in this way, the CPU 401 executes the interrupt return instruction, so that the CPU 401 returns to the time when the external interrupt 407 occurred and executes the instruction stopped there.

A case where a floppy disk drive is used as the external device 406 will be described below. When the CPU 401 reads from this disk drive, three commands, a seek command, a read command, and a status read command, are sequentially sent from the CPU 401 to the external device 4
Issued on 06. In this case, external interrupts corresponding to these three commands are sequentially generated. Here, these interrupts are the same external device 4
Since these are generated from 06, one interrupt processing unit 404 processes these interrupts. This processing procedure is shown in the flowchart of FIG.

Next, description will be made with reference to the flowchart of FIG. The time point when the external interrupt occurs and the control is transferred by the CPU 401 is shown in step S501. First, in step S502, it is checked whether the interrupt cause is a seek command interrupt. If it is a seek command, the process advances to step S504 to perform seek interrupt processing. On the other hand, in step S502, if the cause of the interrupt is not a seek command interrupt, the process advances to step S503 to determine whether the command is a read command. If the cause of the interrupt is an interrupt due to a read command in step S503, the flow advances to step S505 to perform a read interrupt process. If the cause of the interrupt is not the read command interrupt in step S503, then step S506 is executed and the status
Perform read interrupt processing. Thus, step S504
When the execution of steps S506 to S506 is completed, the process proceeds to step S507, and a return instruction from an interrupt is executed.

[0008]

As described above, in the above-mentioned conventional example, when a plurality of types of interrupts are generated from the same external device, the CPU always inquires the type of the interrupt in the external interrupt processing, and the type of the interrupt. Had to judge. For this reason, it takes a long time to execute the external interrupt processing, and the efficiency of the interrupt processing cannot be improved.

The present invention has been made in view of the above-mentioned conventional example, and recognizes and registers the interrupt which will occur next during the processing of the interrupt which is currently occurring, so that the interrupts having a plurality of types of procedures can be determined. On the other hand, it is an object of the present invention to provide an interrupt processing method and device capable of improving interrupt processing efficiency.

[0010]

In order to achieve the above object, the interrupt processing device of the present invention has the following configuration.
That is, it is an interrupt processing device that performs interrupt processing by referring to an address registered in the interrupt table for an interrupt that has occurred. A storage unit that stores the order of occurrence, a recognition unit that refers to the storage unit to recognize an interrupt that occurs next to the current interrupt process, and an interrupt that occurs next that is recognized by the recognition unit Registration means for registering the processing address in the interrupt table.

In order to achieve the above object, the interrupt processing method of the present invention comprises the following steps. In other words, it is an interrupt processing method that performs interrupt processing by referring to the address registered in the interrupt table for the generated interrupt. The step of storing the occurrence order of the interrupt, the step of recognizing the interrupt that occurs next when the interrupt occurs, the step of registering the processing address of the interrupt that occurs next in the interrupt table, The occurrence of
Referring to the interrupt table, determining a processing start address, and executing an interrupt corresponding to the generated interrupt.

[0012]

With the above configuration, for a plurality of types of interrupts in which the interrupt generation order is determined, the interrupt generation order is stored, and the stored information is referred to to determine the next interrupt processing. Recognize interrupts that occur at. Then, it operates so as to register the recognized processing address for the next interrupt that occurs in the interrupt table. As a result, when an interrupt occurs, the interrupt processing is automatically started from the processing address corresponding to the interrupt.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram showing the structure of the interrupt processing device of this embodiment. In FIG. 1, 1 is a CPU and 2 is an interrupt table provided in the memory 3. 52 and 53
Indicates the address pointed to by the entry 22 in the interrupt table 2, and the address 52 is the device interrupt A processing unit 42.
Is specified, and the address 53 is the device interrupt B processing unit 4
3 is specified. Reference numeral 8 is an interrupt sequence table, and the device interrupt A processing unit 42 refers to the interrupt sequence table 8 so that, for example, interrupt A is followed by interrupt B.
Can be known to occur. Similarly, the device interrupt B processing unit 43 can know that the interrupt A occurs next to the interrupt B, for example, by referring to the interrupt sequential table 8. As described above, the interrupt sequence table 8 is a table for knowing the address of the interrupt processing unit that processes the interrupt.

Reference numeral 9 is an interrupt table registering unit, in which the device interrupt A processing unit 42 or the device interrupt B processing unit 43 reads the address of the interrupt processing unit for the next interrupt which is read from the interrupt sequence table 8 and corresponds to the interrupt number. It is created by registering it in the entry 22 of the interrupt table 2. As a result, the interrupt table registration unit 9 stores the entry address corresponding to the interrupt that will occur next.

Here, a processing procedure for the external interrupt 7 generated from the external device 6 will be shown. The external device 6 is used here.
The external interrupts 7 from 7 are generated in the order of interrupt type A and interrupt type B. Further, it is assumed that the address indicated by 52, that is, the address of the device interrupt A processing unit 42 is set as the entry 22 of the interrupt table 2 as an initial value.

When the external device 6 now generates an external interrupt 7 (interrupt A), the CPU 1 stops the instruction being executed,
The interrupt address 11 is output based on the value of the register in the CPU 1. As a result, the external interrupt 7 (or the interrupt number automatically generated by the CPU 1 by the external interrupt 7) is recognized, and this interrupt number (2 in this embodiment) is used as an index in the interrupt table 2. Request the entry 22 therein. Next, the device interrupt A processing unit 4 registered in this entry 22
The address 2 (indicated by 52 in FIG. 1) is taken out, and the processing shifts to this address. As a result, the interrupt type A of the external interrupt 7 is processed by the device interrupt A processing unit 42. Thus, the device interrupt A processing unit 42
After processing the type A of the external interrupt 7, by referring to the interrupt order table 8, it is possible to know that the interrupt type B occurs next to the interrupt type A. As a result, the address of the device interrupt B processing unit 43 that is the type B interrupt processing is obtained, and the interrupt table registration unit 9 is called.

The interrupt table registration unit 9 registers the address 53 of the type-B interrupt process, which occurs next in the process, in the entry 22 of the interrupt table 2 and returns to the device interrupt A process unit 42. After that, the device interrupt A processing unit 42 executes an interrupt return instruction. Thus, CP
When U401 executes the interrupt return instruction, external interrupt 7
The instruction stopped when the type A occurs is executed.

When a type B of the external interrupt 7 is generated from the external device 6 thereafter, the device interrupt B process indicated by the address registered in the entry 22 of the interrupt table 2 (53 in FIG. 1) is performed by the same procedure as described above. Control is transferred to the part 43. The device interrupt B processing unit 43 uses the external interrupt B
After processing the above, referring to the interrupt order table 8 in the same manner as described above, if it is found that the interrupt type A occurs next to the interrupt type B, for example, the device interrupt A processing unit 42
The interrupt table registration unit 9 is requested to register the address in the entry 22 of the interrupt table 2.

As a result, the interrupt table registration unit 9 adds the device interrupt A processing unit 42 to the entry 22 of the interrupt table.
1 is registered (52 in FIG. 1), and the process returns to the device interrupt B processing unit 43. The device interrupt B processing unit 43 executes an interrupt return instruction. When the CPU 401 executes this interrupt return instruction, it executes the instruction stopped when the external interrupt type B occurs.

FIG. 3 shows the interrupt sequence table 8 in this embodiment.
It is a figure which shows an example.

In FIG. 3, when an interrupt of type A occurs, the type of the interrupt that occurs next time is registered as B, and the device interrupt B processing unit 43 is used as the address of the interrupt processing unit that occurs next. The address of is registered. Similarly, for the type B of interrupt that occurred,
The type of interrupt that occurs next is A, and the address of the interrupt A processing unit 42 is registered.

Here, a case where a floppy disk drive is taken as an example of the external device 6 will be described as in the case of the conventional example. For read access to this drive, three commands, a seek command, a read command, and a status read command, are sequentially processed by the CPU 1.
Is issued to the external device 6, and interrupts are sequentially generated for these three commands. In the present embodiment, three interrupt processing units of different types are provided for these three interrupts. However, since the processing of each interrupt processing unit differs only in the interrupt processing for each interrupt type, a seek interrupt is used here. The processing procedure for is described below. This is shown in the flowchart of FIG.

Next, the flowchart of FIG. 2 will be described.

The time point at which control is transferred by the CPU 1 when an external interrupt is generated is indicated by step S1. Here, control is transferred by a seek interrupt. Next, in step S2, the seek interrupt process is performed. Next, in step S3, the interrupt sequence table 8 is referenced to know that the interrupt that will occur next is a read interrupt, and the address of the interrupt processing unit is obtained. Next, in step S4, the interrupt table registration unit 9 is activated, and the address of the interrupt processing unit obtained in step S3 is registered in that entry of the interrupt table 2. Then step S
In step 5, a return instruction (return instruction) from the interrupt is executed. As a result, when a read interrupt occurs thereafter, the process moves to the address indicated by the entry registered by the interrupt table registration unit 9, and the corresponding read interrupt processing unit executes it.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can also be applied to the case where it is achieved by supplying a system or apparatus with a program for executing the processing defined in the present invention.

As described above, according to the present embodiment, when a plurality of types of interrupts from the same external device occur in a predetermined order, each of these interrupt processes recognizes the type of interrupt that occurs next. , The address of the interrupt processing unit that occurs next can be registered in the interrupt table. This eliminates the need for the process of determining the type of the interrupt when the interrupt occurs, so that the extra overhead can be eliminated and the processing efficiency of the interrupt process can be improved.

[0028]

As described above, according to the present invention, when an interrupt that is currently occurring is processed and the interrupt that occurs next is recognized and registered, it is possible to deal with interrupts for which a plurality of types of procedures have been determined. This has the effect of improving the interrupt processing efficiency.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration of an interrupt processing device of the present embodiment.

FIG. 2 is a flowchart showing seek interrupt processing in the interrupt processing device of the present embodiment.

FIG. 3 is a diagram showing an example of data registered in an interrupt sequence table of this embodiment.

FIG. 4 is a conceptual diagram showing a configuration of a conventional interrupt processing device.

FIG. 5 is a flowchart showing interrupt processing in a conventional interrupt processing device.

[Explanation of symbols]

 1 CPU 2 Interrupt Table 3 Memory 6 External Device 7 External Interrupt 8 Interrupt Sequence Table 9 Interrupt Table Registration Unit 11 Interrupt Address 22 Interrupt Table Entry 42 Device Interrupt Type A Processing Unit 43 Device Interrupt Type B Processing Unit

Claims (2)

[Claims] 1. An interrupt processing device for performing an interrupt process by referring to an address registered in an interrupt table for an interrupt that has occurred, and for a plurality of types of interrupts in which the interrupt generation order is determined, A storage unit that stores the order of occurrence of the interrupt, a recognition unit that refers to the storage unit and recognizes an interrupt that occurs next to the current interrupt process, and a next generation that is recognized by the recognition unit. An interrupt processing device for registering a processing address for the interrupt to be registered in the interrupt table. 2. An interrupt processing method for performing interrupt processing by referring to an address registered in an interrupt table for an interrupt that has occurred, and for a plurality of types of interrupts in which the interrupt generation order is predetermined. , A step of storing the interrupt generation order, a step of recognizing the interrupt which occurs next by referring to the generation order when the interrupt occurs, and a step of registering the processing address of the interrupt which occurs next in the interrupt table And, when an interrupt occurs, referring to the interrupt table, determining the processing start address, and executing an interrupt corresponding to the generated interrupt, the interrupt processing method.