JPH0612319A - Microprocessor system - Google Patents

Abstract

(57) [Abstract] [Purpose] A microprocessor system can be obtained at low cost and at high speed by making the cycle of the microprocessor variable by a micro instruction. [Structure] A cycle of a cycle circuit 10 is changed by setting / resetting a latch 14 by a micro instruction.
When the latch 14 is 0, the low-speed ROM 4 is accessed, and when the latch 14 is "1", the high-speed RAM 5 is accessed. [Effect] It is possible to obtain a high-speed processor system that takes advantage of the high speed of the RAM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a low cost and high speed microprocessor system.

[0002]

BACKGROUND OF THE INVENTION Computer peripherals often incorporate a microprocessor system to control the device. The microprocessor system has several configurations, one of which is as follows.

A microprogram for controlling the device is stored in a low-priced non-volatile memory such as a floppy disk, and the microprogram is loaded from the non-volatile memory into a high-speed RAM when the power of the device is turned on. After the loading is completed, the microprocessor sequentially reads the microcode from the high speed RAM and executes the microprogram for controlling the device. High-speed RA from non-volatile memory
There is a ROM for loading the microprogram into the M, and the loading processing microprogram is stored in this ROM.

When the power of the device is turned on, the microprocessor sequentially reads the microcode from the ROM, executes the microprogram loading process from the non-volatile memory to the high-speed RAM, and controls the device loaded in the high-speed RAM after the loading is completed. Run a microprogram.

Considering the processing speed of the microprocessor system, one microprocessor is used as the ROM.
Alternatively, since the microcode is read from the RAM, it can be seen that the processing speed depends on the slower access speed of the ROM and the RAM. In general, RAM, especially SRAM, can be accessed at high speed, whereas ROM requires twice to three times as much access time as SRAM, and is particularly low-priced EPR.
OM requires about 5 times as much access time as SRAM.

Further, in the computer peripheral device, the load processing at the time of turning on the power supply is not required to have high speed. This is because the program load time of the peripheral device is very small and neglected with respect to the program load time of the central processing unit. On the contrary, in the device control after the completion of loading, the processor system is required to perform high-speed processing. This is because the processing capacity of the processor system greatly affects the processing capacity of the peripheral devices.

This means that the microprocessor system needs low-speed processing when executing the microprogram stored in the ROM, but requires high-speed processing when executing the microprogram stored in the RAM.

A known example of low cost and high speed processing of a microprocessor system is JP-A-2-230350.

[0009]

The object of the present invention is to provide RO
An object of the present invention is to provide a low-cost and high-speed microprocessor system that takes advantage of the high speed of RAM regardless of the low speed of M.

[0010]

As means for achieving this object, a RAM or RO is provided by a microprogram instruction.
Make the access time to M variable.

[0011]

As a result, a program that does not require high-speed processing such as when loading a program can be stored in a low-priced ROM, and a program that requires high-speed processing such as a device control microprogram can be stored in high-speed RAM. One microprocessor can execute these two types of programs.

[0012]

EXAMPLE An example of the present invention will be described with reference to FIGS. FIG. 1 shows the configuration of the microprocessor system of the present invention. The microprocessor 1 is connected to the floppy disk 3 via the floppy disk controller 2,
The floppy disk 3 stores a device control microprogram. Also, the microprocessor 1 is 64K
It is connected to a high-speed RAM 5 of W and a low-speed low-cost ROM 4 of 4 KW, and the ROM 4 includes a floppy disk 3 to RA.
A microprogram for loading the device control microprogram into M5 is stored. Further, in order for the microprocessor 1 to read the microcode in the ROM 4, it takes four times as long as the reading time of the microcode in the RAM 5. In addition, in the microprocessor 1,
A cycle circuit 10 for instructing the cycle of the microprocessor 1 and a 16-bit address counter 11 for instructing the ROM 4 or the RAM 5 of a micro program address.
And the address decoding circuit 12 for selecting the ROM 4 when the upper 4 bits of the address counter 11 is (0) ₁₆ o'clock (1) ₁₆ to (F) ₁₆ o'clock, the ROM 4 or the RAM
5 includes an instruction decoding circuit 13 for decoding the microcode read from the memory 5, and a latch 14 for instructing a cycle time. The latch 14 can be set / reset by a microinstruction.

FIG. 2 shows a cycle of the microprocessor 1. The microprocessor 1 has two cycles,
This cycle is switched by the state of the latch 14. When the state of the latch 14 is "0", it operates in cycle 2 and "1"
At that time, it operates in cycle 1. In cycle 1, instruction read time a is short, so RAM5 is accessible, but ROM4
Can not access. Since the instruction read time a in cycle 2 is four times the instruction read time in cycle 1, RAM 5 and ROM 4 can be accessed.

The process from the power-on of the device to the high-speed processing of the microprocessor utilizing the high speed of the RAM 5 is as follows. Address counter 1 when the device power is turned on
1 indicates the address 0, and the latch 14 is set to the "0" state. At this time, the address decoding circuit 12 is the ROM 4
Is selected, the cycle circuit 10 operates in cycle 2.
The microprocessor 1 loads the device control microprogram stored in the floppy disk 3 into the RAM 5 via the floppy disk control circuit 2 in accordance with the microcode sequentially read from the ROM 4. The load operation program address (0 ×××) is of course to be executed by the address _16. After loading is completed, jump to _16th program address (1000). Since the value of the address counter 11 becomes (1000) ₁₆ , the address decoding circuit 12 selects the RAM 5. If an instruction code for setting the latch 14 to "1" is entered at the address (1000) _16th , the device control microprogram loaded into the RAM 5 will be executed in the high speed processing of cycle 1.

[0015]

According to the present invention, a low cost and high speed microprocessor system can be provided. According to the embodiment, the speed is twice as high as that of the conventional microprocessor system.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a microprocessor system of the present invention.

FIG. 2 is a diagram showing a microprocessor cycle of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Microprocessor, 10 ... Cycle circuit, 11 ... Address counter, 12 ... Address decode circuit, 14 ... Cycle switching latch, 3 ... Floppy disk, 4 ... ROM, 5 ... High speed RAM.

Claims (1)

[Claims] 1. A microprocessor and a non-volatile memory for storing a micro program, a high-speed RAM for storing a micro program for executing instructions by the microprocessor, and a micro-memory from the non-volatile memory to the high-speed RAM when power is turned on. A microprocessor system comprising a low-speed ROM for storing a microprogram for loading a program, characterized in that the cycle time of the microprocessor can be varied by a microprogram instruction.