JPH0612337A - Memory module and computer using the same - Google Patents

Abstract

PURPOSE:To share memory modules and decrease the number of memories in use by mounting a memory module in a connector for memory extension regardless of whether or not a parity check on a computer is made. CONSTITUTION:In the memory module, a parity generator 41 which generates a parity bit according to data read out of the DRAMs 31 or 38 of tan memory module is provided, and when data are read out from outside, the data are outputted while a correct parity bit is added corresponding to the read data. Therefore, a DRAM for storing the parity bit can be omitted from this memory module, which is usable regardless of the function for the parity check of the computer having the connector for memory extension.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory module and a computer using the same, and more particularly to a memory module attachable to a memory expansion connector which is designed to handle error detection data of data written in the memory, and The present invention relates to a computer in which a memory module that does not store error detection data can be attached to a memory expansion connector having such specifications.

[0002]

2. Description of the Related Art Conventionally, in a memory used for a computer, particularly a semiconductor memory that can be read and written,
In order to ensure the reliability of the written data, a structure is added in which information such as parity and checksum is added. Taking parity as an example, the processor (hereinafter, CPU
The data bus that connects the memory and the memory is provided with a parity generator that takes in the data and generates parity. This parity generator normally generates 1-bit parity data for 8-bit data. The memory has a 9-bit configuration, and when 8-bit data is written, the parity data generated by the parity generator is written at the 9th bit. When the width of the data bus is large, parity data is added every 8 bits. For example, the bus width is 1
In the case of 6 bits and 32 bits, the data including the parity bit becomes 18 bits and 36 bits, respectively.

On the other hand, when reading the data, the parity of the 9-bit data is checked, and if the parity does not have the evenness defined at the time of writing, a certain measure is taken as a parity error. By the way, there are various ways of thinking about the method of ensuring the reliability of the contents of the memory, and there are various methods such as those that are processed as a serious error and those that are processed as a minor error. According to the former idea, the data includes an instruction executed by the CPU, and if a parity error occurs, it is considered that there is a risk of runaway, and the operation of the CPU is immediately stopped. On the other hand, when only simple data is stored, there is an idea that no special measures such as CPU stop are taken. These are determined by the nature of the computer incorporating the memory system, the purpose of use, and the like.

[0004]

However, a computer equipped with an expansion slot for expanding the memory capacity is of a type that exchanges this parity check signal with the memory module connected to the expansion connector. Some of them have a configuration in which a parity check is not performed, which has been a problem in making the memory modules common. That is, if it is designed according to the former, the memory for parity check becomes useless when it is mounted on the latter, and conversely, if it is configured without the memory for parity check, it can be used for the computer for performing parity check. I can't.

In recent years, the reliability of semiconductor memories has improved and the possibility of parity errors has become extremely low. Even when it can be determined that a memory module does not require parity check, parity check is important. Often you have to use expensive memory, considering the possibility of installing it in a computer with an old design,
Not only the cost reduction but also the resource saving and the energy saving have been problems.

The present invention has been made in order to solve the above problems and to provide a memory module capable of flexibly coping with the configuration of parity check and a computer using the same, and has the following configuration.

[0007]

As illustrated in FIG. 1, a memory module of the present invention is connected to a memory extension connector M1 having a signal line configured so that at least data can be read from a processor inside a computer. A memory module for receiving the signal for reading the data stored in the memory via the memory expansion connector M1, and generating the error detection data according to the data read from the memory. The gist is to include the error detection data generating means M2.

On the other hand, the computer of the present invention includes a processor for performing a logical operation, an internal memory for storing at least data related to the processing of the processor, a memory expansion connector to which a memory module can be attached, the internal memory or When writing data to a memory module attached to the memory expansion connector, error detection data output means for generating data for error detection according to the data and outputting the data, and reading data from the internal memory A computer provided with data determination means for reading the error detection data stored at the time of writing in association with the data and determining the certainty of the read data from the data and the error detection data. Therefore, the expansion connector is connected to the memory module by the processor. At the time of writing the data, an error data output signal line for outputting the error detection data generated by the error detection data output means is connected, and further, when the data stored in the memory module is read out. The gist is that an error detection data generation unit is provided that generates the error detection data according to the data read from the memory module and outputs the error detection data to the data determination unit.

[0009]

In the memory module of the present invention configured as described above, when the signal for reading the data stored in the memory is received via the memory expansion connector M1, the error detection data generating means M2 is operated from the memory. Error detection data is generated according to the read data. Therefore, this memory module is
Even if it is connected to the memory expansion connector M1 configured to detect an error, it can be used as it is.

On the other hand, in the computer of the present invention, the memory module is attached to the memory expansion connector, and the error detection data output means and the data judgment means are provided inside the computer, and the internal memory and the memory expansion memory are provided. It is possible to judge the certainty of the data written to the memory module mounted on the connector. An error data output signal line for outputting error detection data generated by the error detection data output means is connected to the memory expansion connector, and the memory expansion connector is mounted on the memory expansion connector. The memory module does not utilize this signal. On the other hand, when reading data from the memory module, the error detection data generation means generates error detection data according to the data read from the memory module and outputs it to the data determination means. Therefore, even without having a memory for storing error detection data, the memory module can be mounted and used in a computer that determines the accuracy of data.

Although the error detection data generating means is preferably provided on the memory module, it may be incorporated into another expansion slot of the computer or an internal connector directly connected to the bus. Also,
As the error detection data, in addition to parity data, various known data such as checksum, harmonic code, cyclic redundancy code (CRC) can be used.

[0012]

Preferred embodiments of the present invention will be described below in order to further clarify the structure and operation of the present invention described above. FIG. 2 shows a memory module 1 as an example.
Is a schematic configuration diagram showing the internal configuration of the computer 5 attached to the extension connector 3, and FIG. 3 is a block diagram showing the internal configuration of the memory module 1.

As shown in the figure, inside the computer 5, a well-known CPU 11, ROM 12, RAM 14,
An image controller 18, which outputs image data to the liquid crystal display 16, a parity controller 20, and the like are provided. The CPU 11, the ROM 12, and the like are connected to each other by an internal bus 22 including an address signal line, a data signal line, and a control signal line. The computer 5 has an architecture with a data bus width of 16 bits and an address bus width of 24 bits. The RAM 14 is composed of 18 dynamic RAMs of 1 bit × 1 mega. These dynamic memories form a low-order byte and a high-order byte in groups of eight, respectively.
The AM is used for storing one parity bit for each set. Note that the roles of these elements inside the computer are well known, so description thereof will be omitted here.

The parity controller 20 includes a memory 14
Corresponding to the internal configuration {(8 + 1) × 2 sets}, two sets of the same configurations for checking the evenness of the number of bits of value 1 in the 9-bit data are provided. For example, TTL74LS280 manufactured by Texas Instruments Incorporated can be used as the element for checking the evenness. 9
Considering the bit as a unit, the 8-bit input terminals A to H of the device are the upper byte or the lower byte of the internal data bus, and the 1-bit input terminal I is the data output of the parity check memory provided in the RAM 14. It is connected to terminal O. The element that checks for oddness is
When the RAM 14 is read from or written to, the total number of bits of 8 bits output to the data bus and 1 bit of parity data is 9 bits, and the number of bits of value 1 included in the data is counted. The output ODD has a high level when the number is O.

Therefore, the parity controller 20 and the RAM when the internal RAM 14 is accessed
Data exchange with 14 is as follows. When Writing Data to RAM 14 When writing data from the CPU 11, the write address output by the CPU 11 is time-divided into upper and lower order and output to the address bus. At the same time when the address signal is established, the data to be written in the RAM 14 is output onto the data bus, and the write enable signal / WE which permits the writing of the data in the RAM 14 is also activated (low level). At this time, input I for parity
Since no data is output from the CPU 11, the input I is maintained at the low level. The elements in the parity controller 20 receiving the 8-bit data D0 to D7, D8 to D15 output to the data bus and the data to the terminal I are based on the evenness of the number of bits of the value 1 included in the data. The output ODD is determined to be low level (parity = even) or high level (parity = odd). The content of the output ODD is written in the parity memory of the RAM 14.

When data is read from the RAM 14, when the CPU 11 reads data from the RAM 14, C
The read address output by the PU is time-divided into upper and lower parts and output to the address bus. This address signal is RA
When a predetermined time elapses while the write enable signal / WE applied to M14 is disabled, RAM1
The data of the corresponding address is read from the memory device of No. 4 and output to the data bus. This address signal is R
Since it is also given to the parity memory of the AM 14, 1-bit data for parity is also read at the same time and output to the input terminal I of the parity controller 20. In the parity memory, the value 0 is written for even parity and the value 1 is written for odd parity when writing data. Therefore, the entire 9 bits including this parity data (1 bit) The even-oddness of the data at will result in even parity being maintained. Therefore, the output ODD of the parity controller 20 is kept at the low level when the data is read from the RAM 14 unless there is a parity error. As described above, the parity controller 2
Since 0 has two sets of the above configurations, 16-bit data (1 word) is subjected to the same processing for each upper byte and lower byte.

When data is read from the RAM 14 and a bit error occurs in the data in the RAM 14 due to a soft error or the like, the parity of the data in the RAM 14 in 8-bit units may be an odd number. The output ODD of the parity controller 20 becomes high level. The output ODD is connected to the interrupt input terminal INT of the CPU 11 through the AND gate 24, and the other input terminal of the AND gate 24 is connected to the write enable signal / WE. RAM14
When reading data from, write enable signal /
Since WE is kept in the disabled state (high level), the CPU 11 can know the occurrence of the parity error by the interrupt request.

The parity check on the RAM 14 which is the internal memory of the computer 5 has been described above. Next, a parity check in the memory module 1 connected to the memory expansion connector 3 will be described. FIG. 3 is a block diagram schematically showing the internal structure of the memory module 1. The width of the data bus of the memory module 1 is 16 bits, but since the upper byte and the lower byte have substantially the same configuration, only the configuration of the lower byte data D0 to D7 will be described here.
Although the upper byte has the same configuration, its illustration and description are omitted.

The memory module 1 includes eight dynamic RAMs 31 to 38 for lower bytes, a multiplexer 40 for time division of address signals, a parity generator 41, and two octal line buffers 4.
4, 45, etc. are provided. 8 dynamic R
The AMs 31 to 38 are well-known ones having a configuration of 1 bit × 1 megabit and are connected in parallel to eight multiplexed output buses of the multiplexer 40, so that 1
It constitutes a megabyte memory space. A signal obtained by decoding a higher-order signal of an address that determines allocation of the memory module 1 to the memory space of the entire computer 5 is also connected to the memory module 1, but is not shown.

The octal line buffers 44 and 45 are D
It controls the connection between the data input terminals Din and output terminals Dout of the RAMs 31 to 38 and the data buses D0 to D7. For convenience of understanding, only the write enable signal / WE from the CPU 11 causes the gate G
Are shown as being controlled. That is, the DRAM 31
When the write enable signal / WE is at the low level at the time of writing the data to the to 38, the output of the octal line buffer 44 becomes the enable state,
Data buses D0 to D7 are DRAMs 31 to 38
The data input terminals Din are connected to each other. On the other hand, when the data is read from the DRAMs 31 to 38 and the write enable signal / WE is at the high level, the write enable signal / WE is output to the inverter 4
Since the gate terminal G of 45 is controlled by the signal inverted at 8, the output of the octal line buffer 45 is enabled, and D0 to D7 of the data bus are D
The data output terminals Dout of the RAMs 31 to 38 are connected.

The data output terminals Dout of the DRAMs 31 to 38 are connected to the input terminals A to H of the parity generator 41 together with the octal line buffer 45, and the output ODD of the parity generator 41 is added as a parity check signal PC for extension. It is output to the connector 3. In this embodiment, the parity check signal PC is connected to the input terminal I of the parity controller 20. Therefore, the parity of the data read from the memory module 1 is checked by the parity controller 20 together with the parity check signal PC.

In the case of a normal memory module, since it has a memory for storing parity therein, the data of the parity check is read together with the data when the data is read, and the parity controller 20 checks the evenness of the data. Is done. When the evenness of the data is not correctly maintained, the CPU 11 is notified of the parity error by the interrupt INT, as in the case of reading the data from the RAM 14 which is the internal memory.

On the other hand, in the memory module 1 of this embodiment, when data is written from the CPU 11, the parity data output from the parity controller 20 is ignored. On the other hand, when data is read from the memory module 1 by the CPU 11, the parity generator 41 generates parity data according to the data read from the DRAMs 31 to 38, and performs parity check in accordance with the output of the data. Signal P
Output as C. The parity controller 20 checks whether the read data and the parity check signal PC are even or odd.

Here, the parity check signal PC is
Since it is generated according to the data read at that time,
The evenness and oddness of the data and the parity check signal PC are always correct. Therefore, the parity controller 20 cannot detect a parity error.

As described above, according to the memory module 1 of the present embodiment, the memory module 1 can be attached to the extension connector 3 of the computer 5 for performing the parity check,
It is not necessary to provide an extra memory for storing the parity data. Since one bit of parity data is usually provided for 8-bit data, the memory can be reduced to 8/9 as compared with the conventional memory module. Therefore, it is possible to eliminate the waste of memory in applications where the parity check is not required. Further, the computer to be mounted can be used equally regardless of whether the memory module mounted in the memory expansion connector is configured to perform a parity check or not.

On the other hand, in the case of writing data in the computer 5 using the memory module 1, conventionally, the data to be written is established on the data bus, and the parity generator generates the parity data accordingly. The data cannot be written to memory until after. On the other hand, in the memory module 1 of the embodiment, since it is not necessary to write the parity data, the data can be written in the memory immediately after the data is established in the data bus. When the bus configuration is such that an acknowledge signal ACK is returned from the slave side in data transmission / reception, this configuration in which parity data is not written in the memory directly contributes to shortening the data writing time.

The embodiment of the present invention has been described above.
The present invention is not limited to these embodiments at all, and is, for example, a configuration in which another error correction code such as a harmonic code is added, a configuration in which a memory module incorporating a ROM is applied, and an external storage device using a flash memory. The configuration applied to the memory module, the parity generator 41 is provided outside the memory module 1 (for example,
External storage device for storing data in a file format, such as a hard disk, in which the memory module is provided with another extension connector of the computer 5 or an adapter or the like interposed between the extension connector 3 and the memory module 1) It is needless to say that the present invention can be implemented in various modes without departing from the scope of the present invention, such as the configuration described above.

[0028]

As described above, the memory module of the present invention has the excellent effect that it does not require a memory for storing parity data, although it can be attached to an extension connector of a computer for performing a parity check. Therefore, it is possible to share the memory module and contribute to resource saving and energy saving. Also,
In a computer using this memory module, the time required to write data to the memory module can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a basic configuration of a memory module of the present invention.

FIG. 2 is a schematic configuration diagram of a computer in which a memory module 1 according to an embodiment of the present invention is attached to an extension connector 3.

FIG. 3 is a block diagram showing an internal configuration of a memory module 1 of the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory module 3 ... Expansion connector 5 ... Computer 11 ... CPU 12 ... ROM 14 ... RAM 16 ... CRT 18 ... CRTC 20 ... Parity controller 22 ... Internal bus 24 ... AND gate 31 to 38 ... DRAM 40 ... Multiplexer 41 … Parity generator 44… Octal line buffer

Claims (2)

[Claims] 1. A memory module connected to a memory extension connector having a signal line configured to enable at least data reading from a processor inside a computer, wherein a signal for reading data stored in the memory is sent to the memory. A memory module comprising error detection data generation means for generating error detection data according to the data read from the memory when received via the extension connector. 2. A processor for performing a logical operation, an internal memory for storing at least data related to processing of the processor, a memory expansion connector to which a memory module can be attached, and the internal memory or the memory expansion connector. When writing data to the mounted memory module, error detection data output means for generating data for error detection according to the data and outputting it, and when reading the data from the internal memory, are associated with the data. A computer provided with a data judgment unit for reading the error detection data stored at the time of writing and judging the certainty of the read data from the data and the error detection data, When the processor writes data to the memory module, the error The error data output signal line for outputting the data for error detection generated by the output data output means is connected, and further, when the data stored in the memory module is read, the error data output signal line is read from the memory module. A computer provided with error detection data generation means for generating the error detection data according to data and outputting it to the data determination means.