JPH06132300A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing a semiconductor device by which a manufacturing process of a MOS transistor is simplified and thereby the manufacturing time is shortened. CONSTITUTION:A gate 5 is formed on a silicon substrate 1. Then, the gate is offset from its side wall and an n<+> region 9 is formed in the semiconductor substrate. After activating the n<+> region 9, an n<-> region 10 is formed between the side wall and the n<+> region 9. In this method for manufacturing a semiconductor device, polysilicon 7 is deposited on the whole surface after formation of the gate 5 and then an n<+> region 9 is formed by implanting n<+> ions and after that, the polysilicon 7 on the surface is removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing method, and more particularly to a MOS transistor manufacturing method.

[0002]

2. Description of the Related Art MOS transistors are DRAM, SR
It is a semiconductor device which is used in a very wide range such as used as a single memory such as AM, and is shown in FIG.
It is manufactured by the method shown in the process chart.

That is, in this conventional manufacturing method, a semiconductor substrate forming step, an impurity implanting step, a gate forming step, a lyoxide side step, a polysilicon depositing step, a side wall spacer forming step, an n ⁺ region forming step, and a polysilicon removing step. , N ⁺ region activation process, n ⁻ region formation process, n
^- each step area activation step are carried out sequentially.

In the semiconductor substrate forming process, the so-called
A semiconductor substrate such as a silicon substrate is formed. In a subsequent impurity implantation step, for example, boron (B), boron fluoride (B)
Impurity for controlling threshold value such as F ₂ ) is implanted into a predetermined position of the semiconductor wafer. In the gate forming step, FIG.
As shown in FIG. 4, after forming the gate oxide film 102 on the portion of the semiconductor substrate 101 into which the threshold controlling impurities are implanted, the polysilicon 103 and the silicon oxide film 104 are deposited to obtain a predetermined gate length. Thus, the gate 105 is formed by dry etching.

In the lyoxide process, as shown in FIG. 4B, an oxide film 106 is formed on the gate side wall by lyoxide such as thermal oxidation.

Thereafter, non-doped polysilicon 107 is deposited in the polysilicon deposition step, and non-doped polysilicon 107 is etched by dry etching in the sidewall spacer formation step, as shown in FIG.
Sidewall spacers 108 are formed on the side walls of the gate.

In the n ⁺ region forming step, as shown in FIG. 4D, for example, arsenic (As) is ion-implanted to form n ⁺ regions 109 corresponding to the source and drain.

After that, the side wall spacers 107 are removed by dry etching, and a heat treatment is applied in the n ⁺ region activating step to activate the n ⁺ regions (arsenic implantation regions) 109. Then, as shown in FIG. As shown, p − ions are implanted in the n ⁻ region forming step to form the n ⁻ region 110, and
In the n ⁻ region activation step, heat treatment is applied to activate the n ⁻ region 110.

According to this conventional method, the activation of the n ⁺ regions 109 n ^- is performed before p ion implantation into regions 110, the activation of the n ⁺ region 109 can be sufficiently performed,
The junction leak current can be reduced. Further, since the damage of arsenic implantation is recovered by activating n ⁺ region 109, there is no possibility that the diffusion of p ions is accelerated by the damage of arsenic implantation when activating the p ions implanted later. . As a result, the shallow n ⁻ region 110 is formed, and the short channel effect of the transistor can be suppressed low.

[0010]

By the way, in recent years, LS
As the integration of semiconductor devices such as I and VLSI is advanced, the manufacturing process of these semiconductor devices becomes complicated and the manufacturing period is becoming longer. Therefore, it is desired to simplify the manufacturing process of the components of the semiconductor device such as the MOS transistor as much as possible to shorten the manufacturing period.

In view of the above circumstances, it is an object of the present invention to provide a method of manufacturing a semiconductor device, which simplifies the manufacturing process of a MOS transistor and shortens the manufacturing period thereof.

[0012]

According to the present invention, a gate is formed on a semiconductor substrate, an n ⁺ region is formed in the semiconductor substrate by being offset from a gate side wall, the n ⁺ region is activated, and then the n ⁺ region is activated. In a method of manufacturing a semiconductor device in which an n ⁻ region is formed in an offset region, in order to achieve the above object,
After the gate is formed, polysilicon is deposited over the entire surface, n ⁺ ions are implanted to form an n ⁺ region, and thereafter, the polysilicon layer on the surface is removed.

[0013]

When the polysilicon is deposited over the entire surface after forming the gate, the polysilicon is adhered to the side wall of the gate over a predetermined thickness. Then, when n ⁺ ions are implanted, polysilicon is present in the region corresponding to the conventional sidewall spacer in the vicinity of the gate sidewall, and the implanted n ⁺ ions do not reach the semiconductor substrate in this region. An n ⁺ region is formed in a region offset from the gate sidewall of the. That is, the dry etching process for forming the sidewall spacers after depositing the polysilicon can be omitted. Also, n ⁺
By removing the polysilicon after forming the region, activation of the n ⁺ region is possible.

After forming the n ⁺ region, the polysilicon on the surface is removed by, for example, dry etching. This process time is the time required to remove the polysilicon deposited on the gate and near the gate sidewall. Almost the same, which does not increase the process time.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be specifically described below with reference to FIGS.

As shown in FIG. 1, in a method of manufacturing a semiconductor device according to an embodiment of the present invention, a semiconductor substrate forming step, an impurity implanting step, a gate forming step, a lyoxide side step, a polysilicon depositing step, an n ⁺ region. Forming step, polysilicon removing step, n ⁺ area activating step, n ⁻ area forming step, n
^- each step area activation step are carried out sequentially.

In the semiconductor substrate forming step, a p-type silicon substrate having a plane orientation <111> is formed by a known method.

In the subsequent step of implanting impurities, p-type impurities for threshold control such as boron (B) and boron fluoride (BF ₂ ) are added in an amount of 50 to 100 KeV and 1 to 5E12 cm ^-2.
Is injected into the silicon substrate.

In the gate forming step, as shown in FIG. 2A, after forming the gate oxide film 2 on the surface of the silicon substrate 1, the gate electrode polysilicon 3 having a thickness of 2000 to 4000 .ANG. A silicon oxide film 4 having a thickness of 2000 to 4000 Å is sequentially deposited, and the polysilicon 3 and the silicon oxide film 4 are etched by dry etching to form a gate 5 having a predetermined gate length.

Further, in the lyoxide process, as shown in FIG. 2B, an oxide film 6 having a film thickness of 100 to 300 Å is formed on the sidewall of the gate by lyoxide such as thermal oxidation.

Thereafter, in the polysilicon deposition step, as shown in FIG.
As shown in (c), the non-doped polysilicon 7 is applied to the entire surface of the silicon substrate 1 and the gate 5 by 500 to 15
It is deposited to a thickness of 00Å to form a polysilicon side wall 8 having a predetermined thickness on the gate side wall.

In the n ⁺ region forming step, As ions are introduced into the non-doped polysilicon 7 from 100 to 500 KeV,
Inject at 5-10E15 cm ^-2 . In this n ⁺ region forming step, the polysilicon sidewall 8 near the gate sidewall is formed.
As in the conventional region where the sidewall spacer is present, the implanted As ions do not reach the silicon substrate 1 at a certain position, so that the n ⁺ region 9 is formed in the region offset from the gate sidewall in the silicon substrate 1.

In the subsequent polysilicon removing step, as shown in FIG.
As shown in (d), isotropic dry etching removes all the polysilicon 7 deposited over the entire surface of the silicon substrate 1 and the gate 5. The dry etching conditions are CF ₄ : 300 to 400 SCCM,
O ₂ : 50 to 100 SCCM, 1 Pa, 3 to 5 W / cm
²

The process time of this polysilicon removal process is
It is almost the same as the conventional polysilicon removal process, that is, the time required to remove the sidewall spacers 108 deposited near the gate sidewalls, and therefore the process time is not lengthened.

Further, thereafter, each step of an n ⁺ region activating step, an n ⁻ area forming step, and an n ⁻ area activating step is sequentially performed by a known method. That is, heat treatment is performed at 900 ° C. for 30 minutes to activate the n ⁺ region, and then, as shown in FIG.
As shown in (e), p ion implantation is performed to form an n ⁻ region 10 between the gate sidewall and the n ⁺ region, and heat treatment is performed at 900 ° C. for 30 minutes as necessary to remove the n ⁻ region. Activated.

As can be seen by comparing FIGS. 1 and 3,
According to this method, the conventional polysilicon deposition process and n
^Since the step of forming the sidewall spacer by dry etching between the ⁺ region formation step is omitted,
The manufacturing process is simplified and the manufacturing period can be shortened.

[0027]

As described above, according to the present invention,
Since the step of forming the sidewall spacers by dry etching between the polysilicon deposition step and the n ⁺ region forming step is omitted, the manufacturing process is simplified,
The manufacturing period can be shortened.

[Brief description of drawings]

FIG. 1 is a process drawing of the present invention.

FIG. 2 is a cross-sectional view schematically illustrating the main steps of the present invention.

FIG. 3 is a process diagram of a conventional example.

FIG. 4 is a cross-sectional view for schematically explaining the main steps of a conventional example.

[Explanation of sign]

1 silicon substrate 5 gate 7 of polysilicon 9 n ⁺ region 10 n ^- region

Claims (1)

[Claims] 1. A gate is formed on a semiconductor substrate, an n ⁺ region is formed in the semiconductor substrate by offsetting it from the gate sidewall, and the n ⁺ region is activated, and then the gate sidewall is provided between the n + region. In a method of manufacturing a semiconductor device in which an n ⁻ region is formed in a substrate, a gate is formed, polysilicon is deposited over the entire surface, and then n ⁺ ions are implanted to form an n ⁺ region. A method for manufacturing a semiconductor device, comprising: