JPS63257231A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form source and drain diffused layer characterized by less leakage currents in forming a sidewall, by removing a part other than the side surface of a gate electrode at the final stage of reactive ion etching. CONSTITUTION:A channel stopper 102 of a p-type impurity diffused layer and a field oxide film 103 are formed in an inactive region of a p-type silicon substrate 101. Then a gate oxide film 105a is formed in an active region. Then, a gate electrode 104, a thin oxide film 105b, and an n<-> impurity diffused layer 106 are formed. Then, an oxide film 107 and a nitride film 108 are grown. Thereafter, another part is removed so that the nitride film 108 is made to remain on the side surface of the gate electrode 104. Then, the thin oxide film 105b is removed by wet etching. At this time, since the nitride film 108, which remains on the side surface of the gate electrode 104, is not etched, the width as a sidewall is made to remain sufficiently. Then, an n<+> impurity diffused layer, an interlayer insulating film 111 and an Al electrode 112 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that includes a step of forming a sidewall on the side surface of a gate electrode of an insulated gate field effect transistor. It is something.

[Conventional technology]

Insulated gate field effect transistor (hereinafter referred to as MO8FET)
With the shortening of the channel (hereinafter referred to as "sidewall") or the silicidation of the gate electrode and source/drain diffusion layer, it is necessary to form sidewalls (hereinafter referred to as "sidewalls") of an insulating film on the side surfaces of the gate electrode.

Therefore, the conventional method for forming this sidewall is as follows:
After the gate electrode is formed, one type of insulating film is grown by CVD or the like, and the insulating film is removed by anisotropic etching, leaving sidewalls of the insulating film on the sides of the gate electrode.

[Problem that the invention seeks to solve]

The above-mentioned conventional game Nl! In the method of forming sidewalls on the extreme side surfaces, the etching rate for the anisotropic etching of the film grown in advance on the side surfaces of the gate electrode and the film grown subsequently is the main factor, so this difference within the wafer plane is Due to variations in the etching rate of directional etching, the shape of the formed sidewall may not be uniform.
Furthermore, in the worst case, the film grown on the side surfaces would also be etched, resulting in no sidewalls being formed.Also, reactive ion etching is generally used as the anisotropic etching described above; At the final stage of etching, the surface of the semiconductor substrate corresponding to the source/drain diffusion layer region is exposed to the etching atmosphere, which may cause the semiconductor substrate to be etched, contaminated, or defective. The disadvantage is that the leakage current increases.

An object of the present invention is to form a source/drain diffusion layer with low leakage current without damaging the semiconductor substrate surface corresponding to the source/drain diffusion layer region in forming a sidewall of an insulated gate field effect transistor. It is an object of the present invention to provide a method for manufacturing a semiconductor device, in which the width of the sidewall can be formed with high precision, and the characteristics of the MO8FET can be sufficiently controlled.

[Means to solve all problems]

The method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device having an insulated gate field effect transistor, in which a gate electrode is formed on a semiconductor substrate, and then a thin first insulating layer is formed on the surface of the semiconductor substrate and the surface of the gate electrode. a step of forming a second insulating film on the thin first insulating film; a step of forming a third insulating film on the second insulating film; a step of selectively removing portions of the third insulating film other than those located on the side surfaces of the gate electrode; and a step of selectively removing the second and third insulating films remaining in the thin first insulating film. and a step of selectively removing portions other than those covered by the etching by wet etching.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(f) are longitudinal sectional views of a semiconductor device shown in a process step for explaining one embodiment of the present invention.

First, as shown in FIG. 1(a), a channel stopper 102 of a p-type impurity diffusion layer and a field oxide film 103 are formed in an inactive region of a semiconductor substrate, for example, a p-type silicon substrate 101.
form. Next, a thin oxide film (gate oxide film) of about 300A is formed in the active region by thermal oxidation, for example, and polycrystalline silicon with n-type impurities diffused over the entire surface is grown. A gate electrode 104 is formed by etching, and a thin oxide film 105b of about 200 Å is formed by thermal oxidation, for example, on the surface of the gate electrode 104 and the surface of the substrate corresponding to the source/drain diffusion layer. Next, an n''' impurity diffusion layer 106 is formed by implanting ions of, for example, phosphorus at lXl0''am.

Next, as shown in FIG. 1(b), an oxide film 107 is grown on the entire surface by, for example, the CVD method, and on top of that, the oxide film 107 is grown by, for example, the CVD method.
A silicon nitride film 108 is grown by method D.

Next, as shown in FIG. 1C, other portions are selectively removed by anisotropic etching so as to leave the nitride film 10B on the side surfaces of the gate electrode 104. At this time, the oxide film 107 immediately below the nitride layer 108 is also dry etched at the same time.
The oxide film 105b located further below is left.

Next, as shown in FIG. 1(d), for example,
The remaining oxide film 105b left by hydrofluoric acid is removed by wet etching. At this time, the nitride film 108 remaining on the side surfaces of the gate electrode 104 is not etched, so that a sufficient width as a sidewall is left.

Next, as shown in FIG. 1(e), arsenic ions are implanted to form an n impurity diffusion layer 11 (l).

Next, as shown in FIG. 1(f), an interlayer insulating film 111 and an aluminum electrode 112 are formed and completed according to a normal process.

FIGS. 2(a) to 2(C) are longitudinal cross-sectional views of a semiconductor device shown in order of steps to explain another embodiment of the present invention.

First, after going through the processes up to FIG. 1(d), a pn+ impurity diffusion layer 110 is formed by ion-implanting arsenic.

Thereafter, as shown in FIG. 2(a), titanium 1l13'e is grown on the entire surface by, for example, sputtering.

Next, as shown in FIG. 2(b), silicidation is performed by heat treatment at, for example, 600° C. in a nitrogen atmosphere.

At this time, only the surface of the gate electrode 104 and the surface of the source/drain diffusion layer are silicided in a self-aligned manner to form a titanium silicide film 114.

Thereafter, as shown in FIG. 2(C), a glabellar insulating film 111 and an aluminum electrode 112 are formed and completed according to a normal process.

〔Effect of the invention〕

As explained above, in the present invention, in the final stage of conventional reactive ion etching in sidewall formation, parts other than the side surfaces of the gate electrode (for example, parts corresponding to the source/drain diffusion layer regions) are wetted. Since the etching is removed by etching, there is no damage to the semiconductor substrate surface corresponding to the source/drain diffusion layer region.
Source/drain diffusion layers with low leakage current can be formed.

In addition, in the wet egg, since a nitride film with a small etching rate is used on the side surface of the gate electrode in the present invention, the width of the sidewall can be precisely controlled by controlling the thickness of the oxide film located under the nitride film. It can be formed well and the characteristics of the MOSFET can be sufficiently controlled.

As described above, the present invention provides a highly reliable semiconductor device with an improved degree of integration.

[Brief explanation of drawings]

1(a) to 1(f) are longitudinal sectional views of a semiconductor device shown in order of steps to explain one embodiment of the present invention, and FIG. 2(a)
) to (C) are vertical cross-sectional views of main steps of a semiconductor device shown in order of steps to explain other embodiments of the present invention. 101... P-type silicon substrate, 102-'°゛° channel stopper, 1o3°°°'' field oxide film, 104... gate electrode, 105a-b,
109...Thin oxide film, 106°""' n-
Impurity diffusion layer, 107...CVD oxide film, 10
8...Nitride film, 110...N- impurity diffusion layer, 111...Interlayer insulating film, 112...
...Aluminum electrode, 113...Titanium film, 114...Titanium silicide film. Agent: Susumu Uchihara, patent attorney: r::':,
,) 7 Ugly 121' No. 10 Fig. 2

Claims (2)

[Claims] (1) In a method of manufacturing a semiconductor device having an insulated gate field effect transistor, after forming a gate electrode on a semiconductor substrate, forming a thin first insulating film on the surface of the semiconductor substrate and the surface of the gate electrode; , a step of forming a second insulating film on the thin first insulating film, a step of forming a third insulating film on the second insulating film, and a step of forming the second and third insulating films.
selectively removing a portion of the insulating film other than those located on the side surfaces of the gate electrode; A method for manufacturing a semiconductor device, comprising the step of selectively removing a portion other than a portion by wet etching. (2) The second insulating film is an oxide film formed by a CVD method or a sputtering method, and the third insulating film is an oxide film formed by a CVD method or a sputtering method.
The method of manufacturing a semiconductor device according to claim 1, wherein the nitride film is formed by a method or a sputtering method.