JPH0614060A - Buffer management method - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a buffer management method capable of realizing large-scale address translation using a small-scale table. [Structure] In a buffer management system in which data of a plurality of information blocks to which the same address is assigned is stored in the same block of the buffer memory 1 and managed, a plurality of areas including a certain number of blocks are set in the buffer memory. ,
One of the areas of the buffer memory 1 is designated in correspondence with a part of the address given to the information block, and the relative position in the area of the block in which the data is to be stored is designated in correspondence with the other portion of the address. Is specified. Therefore, the block of buffer memory that stores data is buffered based on the partial address data of the information block.
A first table for specifying one area of the memory, and a second table for specifying the relative position from the head position of the area specified by the first table to the block based on the address data of the other part of the information block. It depends on the table. By sharing the functions between the two tables in this manner, the scale of the table can be small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a management system for storing and managing data transferred by fixed-length information blocks such as packets and cells in a buffer area on a memory such as a communication controller, and particularly to a small scale. The management table is used for management.

[0002]

2. Description of the Related Art In a communication control device of a system in which data is divided into fixed-length information blocks such as packets and cells to be transferred / exchanged, data divided into a plurality of information blocks is stored in a memory in the course of its operation. It is temporarily stored in the buffer area and managed.

Since a conventional communication control device manages a buffer of data, as shown in FIG. 3, a memory 1 having a buffer area and an input port 2 for inputting a packet are provided.
A first and second address buses 51 and 52 for respectively transmitting two types of address information of the packet, and an address conversion unit 3 for converting the address information of the packet into an address of a memory in which the packet is stored, A buffer management unit 4 for managing the data storage status of the memory,
An address bus 5 for transmitting an address on the memory where data is stored, and a data bus for transmitting packet data
And a bus 6.

The buffer area in the memory 1 is divided into a plurality of unit areas, and this unit area (called a block) has a fixed length in advance so that an information unit of the maximum length handled by this apparatus can be stored. It is set.

Packets input to the input port 2 include
A fixed-length address is given, and a series of data generated from the same information source arrives at the input port 2 as a packet group having the same address. In addition, the first packet of the packet group generated from a series of data,
The identification information (head packet identifier) indicating that it is the head is added. A series of these data are continuously stored in the same block on the memory 1.

The address of the packet is defined by two kinds of values displayed in different areas of the packet, for example, a combination of a numerical value indicating the upper digit and a numerical value indicating the lower digit of the address value. One of the numerical values defining the address (address 1) is transmitted to the address conversion unit 3 by the first address bus 51 and the other (address 2) is transmitted by the second address bus 52.

As shown in FIG. 4, the address conversion unit 3 is
It has an address conversion table 7 composed of a readable / writable memory, and corresponds to the address of the packet represented by the combination of address 1 and address 2, the start address value of one block on the memory 8 (block・ Address) is output.

When a packet having the first packet identifier of the packet sequence arrives at the input port 2 and a new packet address is input to the address translation unit 3, the address translation unit 3 causes the buffer management unit 4 to store a memory block. Request an allocation of 8. The buffer management unit 4 that manages the usage state of the memory block 8 allocates an unused block of the memory in response to a request, and notifies the address conversion unit 3 of the start address of the block. Address conversion unit 3
Writes the notified start address of the memory block in the table position corresponding to the packet address.

The written start address is sent to the memory 1 via the address bus 5 and specifies the address when writing data to the memory 1. On the other hand, the data of the first packet is transferred to the memory 1 via the data bus 6.
Sent to and stored in the specified block.

Further, when a series of packets having the same address as the head packet arrives at the input port 2 and those addresses are input to the address conversion unit 3, the address conversion unit 3 is recorded in the table 7. Address the block address of memory 1 corresponding to the packet address
Output to bus 5. As a result, the data storage position of these series of packets will be stored in the same memory as the first packet.
Specified in the block.

As described above, the plurality of packets divided and generated from the series of data having the same information source are identified based on the address value of each packet and stored in the same memory area.

[0012]

However, in the conventional buffer management system, the address conversion table 7 records and holds the block address value in the memory 1 corresponding to all the address values of the input packet. However, there is a problem that the scale of the table 7 becomes extremely large.

The present invention solves such a conventional problem, and uses a table having a smaller scale than the address space width defined by the number of address digits to perform address conversion of the same scale as the conventional one. It is an object of the present invention to provide a buffer management method capable of realizing

[0014]

Therefore, according to the present invention, in a buffer management system in which data of a plurality of information blocks assigned with the same address are stored in the same block of the buffer memory and managed, the blocks are stored in the buffer memory. A plurality of areas including a fixed number of the data blocks are set, one of the areas of the buffer memory is designated in correspondence with a part of the address given to the information block, and the other part of the address is designated in correspondence with the data. The relative position in the area of the block in which is stored is specified.

[0015]

Therefore, the block of the buffer memory for storing the data can be determined by the combination of the functions of the two types of tables. One of them is a first table that identifies one area of the buffer memory based on the address data of a part of the information block, and the other table.
The second is a second table for specifying the relative position from the head position of the area specified in the first table to the block based on the address data of the other part of the information block. By thus sharing the functions by the two tables, the size of the table can be small.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A communication control device for implementing the buffer management system of the present invention is shown in FIG.

This device comprises a memory 1 having a buffer area, an input port 2 to which a packet is input, and a first address for transmitting two types of address information of the packet.
An address bus 51 and a second address bus 52, a first address conversion unit 31 that performs address conversion based on the first address information of the packet, and a memory area management that manages the usage status of the memory area in this address conversion. Part 41
A second address conversion unit 32 that performs address conversion based on the second address information of the packet, a memory block management unit 42 that manages the usage status of the memory block in this address conversion, and the storage of packet data. An address bus 5 for transmitting memory addresses to be stored and a data bus 6 for transmitting packet data.

In the buffer area in the memory, as shown in FIG. 2, a unit area (block) in which a fixed length is set so that an information unit of the maximum length handled in this apparatus can be stored,
A large number of m unit areas (this unit area is referred to as an “area”) are formed by collecting the blocks in a fixed number (n pieces).

The packet input to the input port 2 is the same as the conventional one.

When a packet arrives at the input port 2, the address 1 representing the upper digit of the address value of the packet is input to the first address conversion unit 31 via the first address bus 51, and the lower address value of the packet. Address 2 representing a digit is input to the second address conversion unit 32 via the second address bus 52.

As shown in FIG. 2, the first address conversion unit 31 has an address 1 conversion table 71 composed of a readable / writable memory. This table 71
Has a function of converting the address 1 information of the packet into the start address of the area of the buffer memory space 81 in which this packet should be stored, and corresponds to the address 1 value and on the memory 81 assigned to that address 1 value. The head address value (area address) of one of the areas is output.

When the area of the buffer memory space 81 is not allocated to the input address 1 value, the first address conversion unit 31 requests the memory area management unit 41 to allocate the area. To do.

The memory area management unit 41 manages whether each area on the memory 1 is used or unused, and when the first address conversion unit 31 makes a request for area allocation, One unused area is allocated and the first address of the area is notified to the first address conversion unit 31. First
The address conversion unit 31 writes the notified start address of the memory area in the corresponding position of the address 1 conversion table 71 and outputs address information designating the area.

The area designation address information output from the first address conversion unit 31 is stored in the memory 1 and the second address conversion unit.
Sent to 32 and.

As shown in FIG. 2, the second address conversion unit 32 has m sets of address 2 conversion tables 72 corresponding to the respective areas. This address 2 conversion table 72
Has a function of converting the address 2 information into the position information of the block of the memory 1. In this table 72, block position information is held as a relative address from the start address position of each area.

Upon receiving the area designation address information from the first address conversion unit 31, the second address conversion unit 32 calls a corresponding set of tables 72, performs conversion using the table 72, and inputs the address 2 Outputs the relative address value of the block assigned to the value.

When the block of the buffer memory space 81 is not assigned to the input address binary value, the second address conversion unit 32 determines the memory / block management unit.
Request block allocation from 42.

In the memory / block management unit 42, the memory 1
The presence / absence of each of the above blocks is managed, and when a block allocation request is issued from the second address conversion unit 32, an unused block in the corresponding area of the memory 1 is allocated,
The relative address value from the head of the area of the block is notified to the second address conversion unit 32. The second address translation unit 32
The notified relative address value of the unused block is written in the corresponding position of the address 2 conversion table 72, and the address information for designating the block is output to the memory 1.

The start address value designated by the area output by the first address conversion unit 31 and the relative address value designated by the block output by the second address conversion unit 32 are the address bus 5
The data write address to the memory 1 is specified by these address values. On the other hand, the packet data is sent to the memory 1 via the data bus 6 and stored in the designated block in the designated area.

When a series of packets having the same address as the head packet arrives at the input port 2, each of the first address conversion unit 31 and the second address conversion unit 32 receives the same address 1 and Address 2
Is entered.

The first address conversion unit 31 outputs the start address of the area corresponding to the address 1 using the address 1 conversion table 71, and the second address conversion unit 32 outputs the first address.
The relative address of the block corresponding to the address 2 is output using the address 2 conversion table 72. Thereby,
A series of packets following the first packet is stored in the same memory block as the first packet.

When the storage position of the packet data stored in the memory 1 is searched from the address data, after the area position is specified by the address 1 value, the address provided corresponding to each area. The block position in the area is specified by the binary table.

By adopting such a management system, it is possible to specify the storage position of each packet using the small scale tables 71 and 72.

Further, according to this management method, since the packet data having the same address 1 is stored in one area, the address 1 such as registration or deletion of all the packet data having the same address 1 is registered. It becomes possible to carry out batch processing with the key as a key, and the methods that can be adopted in managing packet data are diversified.

[0035]

As is apparent from the above description of the embodiments, the buffer management system of the present invention can manage packet data without increasing the scale of the table used.

Further, it becomes possible to collectively process the packet data stored in the memory in units of one area, and the range of management methods can be expanded.

[Brief description of drawings]

FIG. 1 is a block diagram of a communication control device that implements a buffer management system of the present invention;

FIG. 2 is a configuration diagram of a memory and an address conversion table in the communication control device,

FIG. 3 is a block diagram of a communication control device that implements a conventional buffer management system;

FIG. 4 is a configuration diagram of a memory and an address conversion table in a conventional communication control device.

[Explanation of symbols]

 1 memory 2 input port 3 address conversion unit 31 first address conversion unit 32 second address conversion unit 4 buffer management unit 41 memory area management unit 42 memory block management unit 5 address bus 51 first address bus 52 second address・ Bus 6 Data bus 7 Address conversion table 71 Address 1 conversion table 72 Address 2 conversion table 8, 81 Buffer memory address space

Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display area H04L 12/56

Claims (1)

[Claims] 1. A buffer management method for managing data of a plurality of information blocks to which the same address is assigned by storing the data in the same block of a buffer memory, wherein the buffer memory includes an area including a certain number of the blocks. Is set, a part of the address given to the information block is made to correspond to, one of the areas of the buffer memory is designated, and it is made to correspond to the other part of the address,
A buffer management method characterized in that a relative position of a block in which data is to be stored in the area is designated.