JPH06149593A - Multitask executive device - Google Patents

Abstract

(57) [Summary] [Purpose] The task switching can be executed according to the external situation without burdening the user program, and the overhead is minimized. [Structure] The register file switching control unit 1 selects and switches one register file from the register file group 8 according to the input data of the external terminal 3, and notifies the save process execution unit 2 of the terminal start signal 5 and the register file under execution. The information signal 6 is output. When the signal 4 indicating the occurrence of an interrupt, an exception, or a recovery event occurs, the save process execution unit 2
Is a specific register file designation signal 7 to the switching control unit 1.
Is output. When the switching control unit 1 receives the signal 7, the switching control unit 1 forcibly switches to the specific register file.
Each register file of the register file group 8 has a start priority register, an instruction pointer, and a stack area pointer, which are connected to the address bus 9 and the data bus 10 and are under the control of the save processing execution unit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-task execution device for performing time-division parallel processing of two or more tasks (work) by using one central processing unit (hereinafter referred to as CPU).

[0002]

2. Description of the Related Art When a microprocessor is used to execute a task, a register group for one CPU,
In many cases, a set of register files including a stack pointer and a status register is prepared, and tasks are executed while transferring necessary data to the register files according to an instruction from the CPU.

However, in this method, only one task can be executed at any one time, so that there is a problem that the execution efficiency is deteriorated. Therefore, one set of register files conventionally provided for one CPU is used in a time-sharing manner,
Methods for performing multiple tasks are being considered. However, with this method, each time the task is switched, the data previously stored in the register file is temporarily saved in the memory (stack) area, and the data required for the next task is called from another memory area to the register file. Operation is required. During this data switching time, the task cannot be executed, and therefore the time loss becomes large.

In order to solve such a problem, there has been considered a method of preparing a plurality of register files for one CPU and executing a plurality of tasks while sequentially switching them. With this method, one register file is prepared for one task, so there is no need to save or recall data when switching,
Therefore, time loss is reduced. However, even in this case, since a plurality of task switching settings are executed by the program, it has been a great burden for the user to create the program according to the user's specifications.

On the other hand, as a timing of switching the task, a method of switching each time one instruction is executed, or a method of switching each task by weighting it with time is considered. In this case, in the case of an application in which multiple tasks are executed in a certain long time, it can be a very effective switching means, but the task to be executed differs depending on the external situation of the application, and the external task is given priority. When executing a task that corresponds to a situation, it is necessary to judge the external situation and select the task to be executed based on the judgment result by a program, which causes a large overhead from the event occurrence to the actual execution. there were.

In addition, the activation of a register file by an interrupt / exception is generally carried out by a method of accepting the interrupt / exception according to the priority and executing the processing when the interrupt / exception factors are generated simultaneously or in a multiple manner. It was known, and the priority was determined by hardware. However, with this method, it is possible to compare and judge the execution priorities of interrupts and exceptions, but since the software compares the execution priorities with normal tasks, the load on the software is heavy, and the priority judgment processing is performed. Was taking time.

[0007]

When a plurality of tasks are executed by one CPU in this way, (1) the switching setting of each task must be set by a program, which imposes a heavy burden on the user. (2) Even if the execution task is changed depending on the external situation, the intervention of the program causes a large overhead. (3) When a register file is activated by an interrupt / exception and a register file is activated by a terminal, the burden of comparing both priorities by software is heavy. The present invention provides a multitask execution device that solves such conventional problems.

[0008]

In order to solve the above problems, the present invention comprises a structure having the following functions. (1) At least one external input terminal corresponding to the external situation is provided, and the register file is directly selected by the data input from the external input terminal. (2) When an interrupt / exception occurs, the stack pointer corresponding to the register file that executes interrupt / exception processing saves the acceptable register file activation priority or interrupt / exception priority before interrupt / exception processing. It (3) When a register file is directly activated due to an external situation, the stack pointer corresponding to the selected register file saves the acceptable register file activation priority or interrupt / exception priority before register file activation. . (4) When the register file is directly activated due to an external situation, the hardware executes the activation judgment by the flag as to whether or not the activation of the register file is permitted. (5) When the register file is directly activated due to an external situation, the hardware executes activation of another register file or comparison of priorities with interrupts, exceptions, and system calls.

[0009]

With this configuration, in multitask processing,
Task switching can be executed according to external conditions without burdening the user program, and a system with minimal overhead can be realized.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a multi-task execution in which a register file can be selected / switched by hardware by means of the terminals of the present invention, and a stack pointer for saving program information at terminal activation and a SP for saving program information at exception / interrupt occurrence are used separately. It is the figure which showed the structure of the apparatus.

The register file switching control unit (hereinafter simply referred to as a switching control unit) 1 selects one register file from the register file group 8 according to the input data of the external terminal 3 and switches it, and at the same time, the save processing execution unit 2 On the other hand, the terminal start signal 5 indicating that the register file switching operation has been performed by the external terminal 3 and the register file number currently being executed (register file group 8
(Indicating which register file is currently used) in the execution register file information signal 6 is output. In addition, a signal indicating that an interrupt event (which occurs asynchronously with the processing in the program or not), an exception (occurs depending on the execution of the program), and a return event (return from interrupt / exception) When the return signal 4 is generated, the save processing execution unit 2 outputs the specific register file designation signal 7 to the switching control unit 1.
Once the switching control unit 1 receives the specific register file designating signal 7, it forcibly switches to the specific register file. Each register file of the register file group 8 has a startup priority register, an instruction pointer (hereinafter referred to as IP), a stack area pointer (hereinafter S
If you have a register file 0,
The boot priority register 11, the IP 12 and the SP 13 are provided one each. Each boot priority register, IP, SP is connected to the address bus 9 and the data bus 10, and is under the control of the save process execution unit 2.

In this embodiment, as an example, the activation priority register is provided in each register file, but it is not always necessary to provide it in correspondence with the register file. Further, the register file that executes interrupt / exception processing is specified (specific register file), and the interrupt / exception processing is executed by the specific register file, but this can also be processed by an unspecified register file.

In the embodiment of FIG. 1, the specific register file will be described as the register file 0 below. External terminal 3
When there is a request to activate the register file 2, the switching control unit 1 selects the register file 2 from the register file group 8 via the register file selection signal 14.
Select. At this time, the activation priority register 15, IP16 and SP17 corresponding to the register file 2 are also selected. Further, the switching control unit 1 makes the terminal activation signal 5 valid and informs the evacuation process execution unit 2 that the register file 2 has been activated through the in-execution register file information signal 6. Retraction processing execution unit 2
Receives these information, SP of register file 2
17 is used to execute processing for saving the activation priority register 15 and the IP 16. The processing contents are as follows. (1) Select SP17 via address bus 9 and
The stack area address information in P17 is transferred to the data bus 10
Read through. (2) Using the stack area address information, IP16,
The save processing is performed in the order of the activation priority register 15. (3) The new stack area address information is written back to the SP 17 using the address bus 9 and the data bus 10.

Next, the case where the interrupt / exception / return signal 4 becomes valid will be described. Interrupt / Exception / Return signal 4
Indicates the interrupt / exception state, the save process execution unit 2 causes the switching control unit 1 to activate the register file 0 via the specific register file designation signal 7. The switching control unit 1 selects the register file 0 by the register file selection signal 14 and
The execution of the register file 0 is transmitted via the register file information signal 6 being executed. Receiving the above information, the save processing executing unit 2 uses the SP 13 of the register file 0 to start the boot priority register 11 and IP1.
The process of saving 2 is executed. The processing contents are as follows. (1) Select SP13 via address bus 9
The stack area address information in P13 is transferred to the data bus 10
Read through. (2) IP12, using the stack area address information
Evacuation processing is performed in the order of the activation priority register 11. (3) The new stack area address information is written back to the SP 13 using the address bus 9 and the data bus 10.

When the interrupt / exception / return signal 4 is in the return state from the interrupt / exception process, the save process execution unit 2 follows the running priority register file indicated by the running register file information signal 6 to start the priority register, IP, SP
Select to execute the return operation. The processing contents are as follows. (1) The SP is selected via the address bus 9 and the stack area address information in the SP is read via the data bus 10. (2) Using the stack area address information, the recovery operation is performed in the order of the boot priority register and IP. (3) The new stack area address information is written back to the SP using the address bus 9 and the data bus 10.

Since the saving operation to the stack is performed by the SP managed by the activated register file, the management is easy when the saving processing occurs in multiple times, and the saving processing including the selection of the SP is performed. By executing the above with hardware, it is possible to realize a system with less burden on software.

FIG. 2 shows that a register file can be selected / switched by hardware through the terminals of the present invention, and a flag for selecting whether to permit switching by hardware and a register indicating a register file activation priority level are provided and switched. It is a figure showing the composition of the multitask execution device which judges.

The register file switching control unit 1 (hereinafter, switching control unit) has a function of selecting and switching one register file from the register file group 8 according to the input data of the external terminal 3. Register file group 8
Each register file has a start permission flag indicating whether the register file can be activated, and a start priority register indicating the start priority of the register file. A flag 18 and a boot priority register 19 are provided and can be set arbitrarily. In the present embodiment, as an example, the activation permission flag and the activation priority register are provided in each register file, but they need not necessarily be provided corresponding to the register file. Both the activation permission flag and the activation priority register are input to the save processing execution unit 2. The activation priority register is compared with the currently executing priority register 22, and if the activation permission flag is “1” and (activation priority register)> (execution priority register 22), the switching permission signal 23 Is output from the save processing execution unit 2 to the switching control unit 1, and the switching operation is executed. Further, the save processing execution unit 2 writes the value of the activation priority register into the executing priority register 22. The value of the startup priority register indicates the priority between register files and between register file startup due to interrupts and exceptions.
high priority. As an example, when the value of the activation priority register is indicated by 4 bits, the activation priority register 19 is “1111” and the activation priority register 21 is “100”.
1 ", and the interrupt priority (not shown) is" 1010 "
Then, the priority is (register file 0)
>(Interrupt)> (register file 2). However, in the activation permission flag, the activation permission flag 18
Is "1", the activation permission flag 20 is "1", and the interruption permission flag (not shown) is "0", the activation sequence is register file 0, register file 2, and the interrupt is not accepted.

If register file 0 is a "specific register file" when an interrupt / exception occurs, each interrupt / exception / system call has a start enable flag and a start priority register. The permission flag 18 and the activation priority register 19 are unnecessary, and
A system in which the activation permission flag 18 and the activation priority register 19 are removed from is also possible. Here, the register file that executes interrupt / exception processing is specified (specific register file), and the interrupt / exception processing is executed in the specific register file, but this can also be processed by an unspecified register file. In this way, by prioritizing each register file, interrupts, exceptions, and system calls, it is possible to process from the highest priority, and the priority comparison and judgment can be executed by hardware. Thus, it is possible to realize a system in which the load of software is light.

FIG. 3 is a diagram showing the timing of the multitask execution system of the present invention shown in FIGS. The horizontal axis indicates time, and the time advances to the right in the figure. Here, as an example, the register file 0 is started as the “specific register file”. Here, the register file that executes interrupt / exception processing is specified (specific register file), and the interrupt / exception processing is executed in the specific register file, but this can also be processed by an unspecified register file. If the register file 2 and the register file 4 occupy a CPU (not shown) in a time-sharing manner and execute multitask processing, if the register file 5 is activated by terminal activation, here, The execution priority register 22 and the activation priority register of the register file 5 are compared and the activation permission flag is checked. When the activation of the register file 5 is permitted, the SP of the register file 5 is used to execute the IP of the register file 5 and the executing priority register 22 (execution if another task is not assigned in the register file 5 in the past. Only the medium priority register 22 is also saved) in the stack area of the register file 5. The value of the running priority register 22 that is saved is the value of the running priority register 22 before the register file 5 is activated. After the save processing is completed, the value of the activation priority register of the register file 5 is set in the executing priority register 22 as it is in the executing priority register 22. The IP of the register file 5 is retained as it is.

When the activation of the register file 0, which is a specific register file, is permitted by the occurrence of an interrupt, the IP of the register file 0 and the executing priority register 22 are set to the register file 0 by using the SP of the register file 0.
Are saved in the stack area. The value of the running priority register 22 saved here is the value before the register file 0 is started (= start priority of the register file 5). After the save processing, the value of the activation priority register of the register file 0 is set in the executing priority register 22. When the "return instruction" from the interrupt is executed in the register file 0, the IP of the register file 0 and the executing priority register 22 are returned from the stack area of the register file 0 by using the SP of the register file 0. The in-execution priority register 22 stores the activation priority of the register file 0, that is, the activation priority of the register file 5. Since the IP of the register file 5 is held, the register file 5 is returned to the state before the system call was issued. When the "restore instruction" for the activation of the register file 5 is executed in the register file 5, the SP of the register file 5 is used to change the I of the register file 5 from the stack area of the register file 5.
P and the running priority register 22 (or only the running priority register 22) are returned. Executing priority register 2
Since the activation priority before activation of the register file 5 is stored in 2, the value of the in-execution priority register 22 is returned to the state before activation of the register file 5. When a register file is activated by an interrupt, exception, or pin, the priority before activation is saved in the stack.
At the time of returning from the activation of the register file by the exception / terminal, the state before the activation of the register file by the interrupt / exception / terminal can be restored, and the system management becomes easy.

[0023]

With this configuration, in multitask processing, there is no burden on the user program when switching tasks, task switching can be executed according to external conditions, and overhead can be minimized. Also,
Since the save operation to the stack is performed by the SP managed by the activated register file, if multiple save operations occur, it is easy to manage and prioritize each register file and interrupt / exception. As a result, it is possible to perform processing in descending order of priority, and since the series of processing described above is executed by hardware, it is possible to provide a system with low software load and good responsiveness.

[Brief description of drawings]

FIG. 1 is a multi-task execution in which a register file can be selected / switched by hardware by a terminal of the present invention, and a program information saving stack pointer (SP) at terminal activation and a program information saving SP at exception / interrupt occurrence are used separately. Diagram showing the configuration of the device

FIG. 2 is a diagram showing a register file which can be selected / switched by hardware by the terminal of the present invention, a flag for selecting whether to permit switching by hardware and a register indicating a register file activation priority level are provided, and switching judgment is performed. Diagram showing the configuration of the multitask execution unit

FIG. 3 is a timing diagram of the multitask execution device of the present invention shown in FIGS. 1 and 2.

[Explanation of symbols]

 1 register file switching control unit 2 save processing execution unit 3 external terminal 4 signal interrupt / exception / return signal 5 terminal start signal 6 executing register file information signal 7 specific register file designation signal 8 register file group 9 address bus 10 data bus 11 Start priority register 12 Instruction pointer (IP) 13 Stack area pointer (SP) 14 Register file selection signal 15 Start priority register 16 Instruction pointer (IP) 17 Stack area pointer (SP) 18 Start permission flag 19 Start priority Register 20 Activation permission flag 21 Activation priority register 22 Currently executing priority register 23 Switching permission signal

Claims (3)

[Claims] 1. Multitask execution in which one central processing unit is occupied by a plurality of register files in a time-sharing manner under the control of a register file switching control unit, and a plurality of tasks are processed in a time-sharing parallel manner by the plurality of register files. In the device, as a register file switching means,
At least one input terminal is provided, and the data input from the input terminal can specify a part or all of the plurality of register files that the central processing unit occupies in a time division manner. A first means for selecting / switching a register file to be executed from the plurality of register files by hardware by inputting, and a second means for indicating a priority level of task execution in the register file. Multitasking device. 2. A multitask execution in which one central processing unit is occupied by a plurality of register files in a time-sharing manner under the control of a register file switching control unit, and a plurality of tasks are processed in a time-sharing parallel manner by the plurality of register files. In the device, as a register file switching means,
At least one input terminal is provided, and the data input from the input terminal can specify a part or all of the plurality of register files that the central processing unit occupies in a time division manner. By inputting, to select and switch the register file to be executed from the plurality of register files by hardware, and second means for indicating the activation permission of the register file by the input terminal. Multitasking device. 3. A multitask execution in which a plurality of register files occupy one central processing unit in a time-sharing manner under the control of a register file switching control unit, and a plurality of tasks are processed in a time-sharing parallel manner by the plurality of register files. In the device, as a register file switching means,
At least one input terminal is provided, and the data input from the input terminal can specify a part or all of the plurality of register files that the central processing unit occupies in a time division manner. Means for selecting / switching the register file to be executed from the plurality of register files by hardware by inputting, and an exception / interruption factor, a factor of activating the register file at the input terminal, or the register file Means for indicating the priority level of task execution in
The third means indicating the priority level currently being executed by the central processing unit, the priority level by the second means and the priority level currently being executed by the third means are compared to determine whether an exception or an interrupt has occurred. A fourth means for determining whether or not the central processing unit is to occupy the register file in which a task or a task generated at the input terminal is executed; and an exception / interruption generated by the fourth means. When the central processing unit is to occupy the register file in which the task or the task generated in the input terminal is executed, it is currently executed by the third means in a stack area where the register file to be executed can be used. By saving the medium priority level, it is possible to return to the currently executing priority level before task activation at the end of the accepted task. Multitask execution and means.