JPH06187169A - Multi-task executing device - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] In multitask processing, task switching can be executed according to the external situation, and overhead is minimized. [Structure] The output of each bit (bp0, 1, to n) of the register file switching scheduling register 1 is input to the register file switching control unit 2, and the control unit 2
Outputs the register file selection signal 4 via the AND-OR circuit 7 in synchronization with the switching timing signal 3 to select the register file in the register file group 5.
Further, each terminal of the external signal group 6 is also input to the circuit 7, and the register file in the file group 5 is selected as the selection signal 4. The circuit 7 outputs the selection signal 4 so that the selection of the register file by the external signal group 6 is always prioritized over the selection by the control unit 2. Further, when the input of the external signal group becomes valid, the detection operation of the scheduling register 1 by the control unit 2 is temporarily stopped, and is restarted when the input of the external signal group becomes invalid.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention uses one central processing unit (CPU) to perform two or more tasks (work).
The present invention relates to a multitask execution device that performs time-division parallel processing.

[0002]

2. Description of the Related Art When a task is executed by using a microprocessor, a set of register files including a register group, a stack pointer, a status register, etc. is prepared for one CPU, and the instruction file from the CPU is prepared. There are many methods of executing tasks while transferring necessary data to the register file. However, in this method, only one task can be executed at any one time, which causes a problem that the execution efficiency is deteriorated. Therefore, conventionally, a method of executing a plurality of tasks by using a set of register files provided for one CPU in a time-sharing manner has been considered. However, with this method, each time the task is switched, the data previously stored in the register file is temporarily saved in the memory (stack) area, and the data required for the next task is called from another memory area to the register file. Operation is required. During this data switching time, the task cannot be executed, and therefore the time loss becomes large.

In order to solve such a problem, there has been considered a method of preparing a plurality of register files for one CPU and executing a plurality of tasks while sequentially switching them. With this method, one register file is prepared for one task, so there is no need to save or recall data when switching,
Therefore, time loss is reduced. However, even in this case, since a plurality of task switching settings are executed by the program, it has been a heavy burden for the user to create the program according to the user's specifications.

On the other hand, as a timing of switching the tasks, a method of switching each time one instruction is executed or a method of weighting each task with time is considered. In this case, it can be a very effective switching means in the case of an application in which multiple tasks are executed in a certain long time, but the task to be executed differs depending on the external situation of the application, and the external situation is given priority. When executing the task corresponding to, it is necessary to judge the peripheral situation and select the task to be executed based on the judgment result by the program, and there is a large overhead from the event occurrence to the actual execution.

[0005]

When a plurality of tasks are executed by one CPU in this way, (1) the switching setting of each task must be set by a program, which imposes a heavy burden on the user. (2) Even when the execution task is changed depending on the peripheral situation, the overhead is large because of the intervention of the program.

The present invention provides a multitasking execution device that solves such conventional problems.

[0007]

In order to solve the above problems, the present invention provides (1) a control register for designating which register file is to be executed among a plurality of register files, and the external input timing is set. The CPU is occupied by one register file with reference to the control register. (2) A single or a plurality of external input terminals corresponding to the external peripheral situation are provided, each external input terminal and each register file have a one-to-one correspondence, and the register file is directly selected by the external input terminal. (3) A serial data input terminal corresponding to the external peripheral condition is provided, and each register file can be specified for the data input from the serial data input terminal, and the register file is directly selected by the serial data input terminal. (4) When the register file is selected by the external input terminal during the operation of occupying the CPU in one register file by the control register, the selection of the register file by the external input terminal is prioritized. (5) When the register file is selected by the external input terminal or the serial data input terminal during the operation of occupying the CPU in one register file by the control register, the register file selected by the terminal is set by the control register. It is treated the same as specified.

The above functions are realized by hardware.

[0009]

With this configuration, in multitask processing,
Task switching can be executed according to external conditions without burdening the user program, and a system with minimal overhead can be realized.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows that the register file can be selected and switched by hardware by the control register or terminal of the present invention, and when the switching operation by the terminal occurs during the operation by the control register, the register file switching operation by the terminal is prioritized. 2 is a timing diagram of the multitask execution device of the present invention shown in FIG. 1.

In FIG. 1, the output of each bit (bp0, 1, 2, to n) of the register file switching scheduling register 1 (hereinafter, scheduling register) is input to the register file switching control unit 2 and the register file switching control unit 2 Outputs the register file selection signal 4 via the AND-OR circuit 7 in synchronization with the register file switching timing signal 3 to select the register file (register files 0, 1, 2, ... N) in the register file group 5. To do. Further, each terminal (terminals 0, 1, 2, to n) of the external signal group 6 is also input to the AND-OR circuit 7, and is used as the register file selection signal 4 in the register file (register files 0, 1, 2, ~ n) is selected.

The register file switching scheduling register 1 is a register for designating which register file in the register file group 5 composed of a plurality of register files is to be used, and is composed of a plurality of bits. Is set. Register file switching Each bit in the scheduling register 1 corresponds to each register file of the register file group 5, and when (bp0 of scheduling register 1) = 1,
When register file 0 is selected (bp1 of scheduling register 1) = 1,
When register file 1 is selected (bp2 of scheduling register 1) = 1,
Register file 2 is selected ... (Scheduling register 1 bpn) = 1,
The register file n is selected.

The scheduling register 1 can set a plurality of bits. The register file switching control unit 2 detects the bit set to “1” in the scheduling register 1 and outputs the result to the AND-OR circuit 7.

On the other hand, the external signal group 6 also includes an AND-OR circuit 7
(However, it is not allowed to set a plurality of terminals in the external signal group 6). Therefore, the AND-OR circuit 7 has (1) the detection output of the register file switching control unit 2 (2) the input of the external signal group 6 (3) the input of the external signal group 6 more than the detection output of the register file switching control unit 2 Three kinds of signals, which are the outputs of the NOR circuit 8 of the external signal group 6 for preferential processing, are input, and the register file selection signal 4 for selecting each register file of the register file group 5 is output.

The AND-OR circuit 7 outputs the register file selection signal 4 so that the register file selection by the external signal group 6 is always prioritized (valid) over the register file selection by the register file switching control unit 2. When the input of the external signal group 6 becomes valid (terminal input value = “1”), the detection operation of the scheduling register 1 by the register file switching control unit 2 is temporarily stopped. Let N
The output of the OR circuit 8 is input to the register file switching control unit 2 via the AND circuit 9. In the AND circuit 9, when the external signal group 6 is in the valid state, the input of the register file switching timing signal 3 is prohibited, whereby the detection operation of the register file switching control unit 2 is performed until the external signal group 6 is in the invalid state. Stop. The detection output of the register file switching control unit 2 is the external signal group 6
Is held as it becomes valid. Like this
The D-OR circuit 7 selects the register file group 5 while having a function of processing the input of the external signal group 6 with priority over the detection output of the register file switching control unit 2 (bp0 of the scheduling register 1). ) = 1 or terminal 0 of external signal group 6) = 1, select register file 0, (bp1 of scheduling register 1) = 1, or (terminal 1 of external signal group 6) = 1, Select the register file 1, when (bp2 of the scheduling register 1) = 1 or (terminal 2 of the external signal group 6) = 1, select the register file 2 ,. ) = 1 or (terminal n of external signal group 6) = 1, select register file n Output register file selection signal 4 under the above conditions That.

FIG. 2 is a timing chart when the register file group 5 is composed of eight register files, the scheduling register 1 has an 8-bit configuration, and the external signal group 6 has an 8-terminal configuration. The horizontal axis indicates time, and the time advances to the right side of the figure. Here, as an example, the scheduling register 1 is programmed (1010010
The case where it is set to 1) will be described. The register file selected by the register file switching control unit 2 is (bp0 of scheduling register 1) = 1,
When register file 0 is selected (bp2 of scheduling register 1) = 1,
When register file 2 is selected (bp5 of scheduling register 1) = 1,
When the register file 5 is selected (bp7 of the scheduling register 1) = 1,
The register file 7 is selected, and in synchronization with the register file switching timing signal 3, the register file switching control unit 2 instructs the AND-OR circuit to register files 0, 2, 5, 7, 0, 2,
Signals for selecting 5, 7, ... Are sequentially output.

However, the input to the terminal 1 of the external signal group 6 is "
When set to "1", the control shifts from the control of register file switching by the scheduling register 1 to the control by terminal switching, the detection operation of the scheduling register 1 of the register file switching control unit 2 is frozen, and the register file switching control unit The output from 2 is held.In this example, since the input of the terminal 1 of the external signal group 6 is set to "1" during execution of the register file 0, the register file 1 is selected and the register file switching control is performed. The output from the section 2 is held in "register file 0." The input to the terminal 1 of the external signal group 6 is "
When it becomes "0", the output from the register file switching control unit 2 becomes valid again and the register file 0 is selected.

By thus specifying the register file to be used in advance, the register file can be switched by the hardware without the program processing, and the register file can be directly switched by the external signal group 6. Therefore, in the multitask processing, it is possible to realize a system in which the overhead of the user program is minimized without burdening the user program when switching tasks.

FIG. 3 shows that the register file can be selected / switched by hardware by the control register or terminal of the present invention, and when the switching operation by the terminal occurs during the operation by the control register, both the control register and the terminal are switched. FIG. 4 is a diagram showing the configuration of a multitask execution device that performs a register file switching operation while referring to FIG. 4, and FIG. 4 is a timing diagram of the multitask execution device of the present invention in FIG.
In FIG. 4, the output of each bit (bp0, 1, 2, to n) of the scheduling register 1 and each terminal (terminals 0, 1, 2, to n) of the external signal group 6 are registered in the register file via the OR circuit 10. Input to the switching control unit 2, the register file switching control unit 2 outputs the register file selection signal 4 in synchronization with the register file switching timing signal 3, and the register files in the register file group 5 (register files 0, 1, 2, , ~ N) are selected.

The input to the register file switching control unit 2 is each bit (bp0,
1, 2 ... N) and the output of the OR circuit 10 of each terminal (terminals 0, 1, 2, ... N) of the external signal group 6, the register file switching control unit 2 When bp0 of register 1 = 1 or (terminal 0 of external signal group 6) = 1, select register file 0 (bp1 of scheduling register 1) = 1 or (terminal 1 of external signal group 6) = 1 When, register file 1 is selected (bp2 of scheduling register 1) = 1, or (terminal 2 of external signal group 6) = 1, register file 2 is selected ........ (bpn of scheduling register 1) = 1 or (terminal n of the external signal group 6) = 1, the register file n can be selected, so that the register file is switched in synchronization with the register file switching timing signal 3. And outputs a file selection signal 4.

FIG. 4 is a timing chart when the register file group 5 is composed of eight register files, the scheduling register 1 has an 8-bit structure, and the external signal group 6 has an 8-terminal structure. The horizontal axis indicates time, and the time advances to the right side of the figure. Here, as an example, the scheduling register 1 is programmed (1010010
The case where it is set to 1) will be described. The register file selected by the register file switching control unit 2 is (when the terminal is in the invalid state = "0") (bp0 of the scheduling register 1) = 1,
When register file 0 is selected (bp2 of scheduling register 1) = 1,
When register file 2 is selected (bp5 of scheduling register 1) = 1,
When the register file 5 is selected (bp7 of the scheduling register 1) = 1,
The register file 7 is selected, and in synchronization with the register file switching timing signal 3, the register file switching control unit 2 causes the register files 0, 2, 5, 7, 0, 2, 5, 7, ... Of the register file group 5. The signals for selecting are sequentially output. However, when the input of the terminal 3 of the external signal group 6 is set to "1", the register file switching control unit 2 becomes in the same state as (bp3 of the scheduling register 1) = 1, and the register file 3 is selected. The input to the terminal 1 of the external signal group 6 also becomes "1", and the register file switching control unit 2 registers the register files 0, 1, 2, 3, 5, 7, 0, 1,
Signals for selecting 2, 3, 5, 7, ... Are sequentially output.

By thus specifying the register file to be used in advance, the register file can be switched by the hardware without the program processing, and the register file to be switched can be directly specified by the external signal. Therefore, in multitask processing, it is possible to realize a system in which the overhead of the user program is minimized without burdening the user program when switching tasks.

FIG. 5 shows that the register file can be selected / switched by hardware by the control register of the present invention or at least one input terminal, and when the switching operation by the serial data input terminal occurs during the operation by the control register, It is the figure which showed the structure of the multitask execution apparatus which gives priority to the register file switching operation by an input terminal. In this example, a case where the input terminal is a serial data input terminal will be described. The output of each bit (bp0, 1, 2, to n) of the scheduling register 1 is input to the register file switching control unit 2, and the register file switching control unit 2 synchronizes with the register file switching timing signal 3 and the AND-OR circuit. The register file selection signal 4 is output via 7 and the register file (register file 0,
1, 2, to n) are selected. Further, the data input from the serial data input terminal 11 is input to the serial data receiving register 12 (internally has a shift register configuration), and each bit of the serial data receiving register 12 is output (bp
0, 1, 2, ... n) are also input to the AND-OR circuit 7,
As the register file selection signal 4, the register files in the register file group 5 (register files 0, 1,
2, ~ n) is selected.

The register file switching scheduling register 1 is a register for designating which register file in the register file group 5 composed of a plurality of register files is to be used, and is composed of a plurality of bits. Is set. Register file switching Each bit in the scheduling register 1 corresponds to each register file of the register file group 5, and when (bp0 of scheduling register 1) = 1,
When register file 0 is selected (bp1 of scheduling register 1) = 1,
When register file 1 is selected (bp2 of scheduling register 1) = 1,
Register file 2 is selected ... (Scheduling register 1 bpn) = 1,
Register file n is selected.

The scheduling register 1 can set a plurality of bits. The register file switching control unit 2 detects the bit set to “1” in the scheduling register 1 and outputs the result to the AND-OR circuit 7.

On the other hand, the value of the serial data reception register 12 is also input to the AND-OR circuit 7 (however, the serial data reception register 12 cannot set a plurality of bits to "1"). Therefore, the AND-OR circuit 7 has (1) detection output of the register file switching control unit 2 (2) output of the serial data reception register 12 (input of the serial data input terminal 11) (3) output of the serial data reception register 12 Of the serial data receiving register 12 for preferentially processing the detection output of the register file switching control unit 2
Three kinds of signals of the output of the R circuit 8 are inputted and the register file selection signal 4 for selecting each register file of the register file group 5 is outputted.

In the AND-OR circuit 7, the register file selection by the serial data receiving register 12 (serial data input terminal 11) is always prioritized (valid) over the register file selection by the register file switching control unit 2. The selection signal 4 is output. Further, when the input value of the serial data becomes valid (serial data input value = “1”), the detection operation of the scheduling register 1 by the register file switching control unit 2 is temporarily stopped. The output of the NOR circuit 8 which is an input is AN
It is input to the register file switching control unit 2 via the D circuit 9. In the AND circuit 9, when the serial data receiving register is in the valid state, the input of the register file switching timing signal 3 is prohibited, whereby the detection operation of the register file switching control unit 2 is performed by the external signal group 6.
Stop until is disabled. The detection output of the register file switching control unit 2 is held when the serial data becomes valid.

As described above, the AND-OR circuit 7 selects the register file group 5 while having a function of preferentially processing the selection of the register file by the serial data reception register 12 over the detection output of the register file switching control unit 2. Therefore, when (bp0 of scheduling register 1) = 1 or (bp0 of serial data receiving register 12) = 1, register file 0 is selected (bp1 of scheduling register 1) = 1 or (serial data receiving register 12 When bp1) = 1, select register file 1 When (bp2 of scheduling register 1) = 1 or (bp2 of serial data receiving register 12) = 1, select register file 2 (Scheduling register 1 bpn) = 1, or ( When the real data bpn the receive register 12) = 1, and outputs a register file selection signal 4 produced under the conditions selected register file n.

By thus specifying the register file to be used in advance, the register file can be switched by the hardware without the program processing, and the register file can be directly switched by the serial data input terminal. Therefore, in the multitask processing, it is possible to realize a system in which the overhead of the user program is minimized without burdening the user program when switching tasks.

FIG. 6 shows that the register file can be selected / switched by hardware by the control register of the present invention or at least one input terminal, and when the switching operation by the input terminal occurs during the operation by the control register,
It is the figure which showed the structure of the multitask execution apparatus which performs a register file switching operation, referring to both a control register and an input terminal. In this example, a case where the input terminal is a serial data input terminal will be described. Each bit of scheduling register 1 (bp0, 1, 2, ~ n)
Output and each bit (bp0, 1, 2, to n) of the serial data input register 12 are input to the register file switching control unit 2 via the OR circuit 10, and the register file switching control unit 2 outputs the register file switching timing signal. Register file selection signal 4 in synchronization with 3
Is output, and a register file (register files 0, 1, 2, ... N) in the register file group 5 is selected. Data is input from the serial data input terminal 11 to the serial data input register 12 as serial data.

The input to the register file switching control unit 2 is each bit (bp0, bp0,
1, 2, ..., n) output and serial data input register 1
OR circuit 10 for each bit of 2 (bp0, 1, 2, ... n)
Therefore, the register file switching control unit 2 selects the register file 0 when (bp0 of the scheduling register 1) = 1 or (bp0 of the serial data reception register 12) = 1 (scheduling register 1 Register file 1 is selected when (bp1 of serial data reception register 12) = 1 or (bp1 of serial data reception register 12) = 1, or (bp2 of serial data reception register 12) = 1 , Register file 2 is selected ... When (bpn of scheduling register 1) = 1 or (bpn of serial data reception register 12) = 1, register file n can be selected, so register file switching timing signal Register file in sync with 3 And it outputs the 択信 No. 4.

By thus specifying the register file to be used in advance, the register file can be switched by the hardware without the program processing, and the register file to be switched can be directly specified by the serial data input terminal. Therefore, in multitask processing, it is possible to realize a system in which the overhead of the user program is minimized without burdening the user program when switching tasks.

FIG. 7 shows that the register file can be selected / switched by hardware by the control register or terminal of the present invention, and when the switching operation by the terminal occurs during the operation by the control register, the register file switching operation by the terminal is prioritized. FIG. 6 is a diagram showing a configuration of a multitask execution device capable of switching whether to perform a register file switching operation with reference to both a control register and a terminal by a flag. As an example, a serial data input terminal will be described as a terminal. Each bit of the scheduling register 1 (bp0, 1, 2,
Outputs of n) are logically ORed with the serial data reception register 12 via the OR circuit 10 and input to the register file switching control unit 2. The register file switching control unit 2 outputs the register file switching timing signal 3
The register file selection signal 4 is output via the selector circuit 14 in synchronism with the above, and the register files (register files 0, 1, 2, ... N) in the register file group 5 are selected. The data input from the serial data input terminal 11 is input to the serial data reception register 12 (internally has a shift register configuration), and the output of each bit of the serial data reception register 12 (bp0, 1, 2, to n).
Is also input to the selector circuit 14 and selects the register file (register files 0, 1, 2, ... N) in the register file group 5 as the register file selection signal 4.
The input selection flag 13 determines whether the selector circuit 14 selects the logical sum data of the scheduling register 1 and the serial data reception register 12 or the data of only the serial data reception register 12. When the value of the input selection flag 13 is "0", the logical sum data of the scheduling register 1 and the serial data receiving register 12 is valid, and when it is "1", the data input of only the serial data receiving register 12 is valid. However, when the value of the input selection flag 13 is "0" because there are restrictions on the serial data reception register 12, it is possible to set a plurality of bits to "1", but the value of the input selection flag 13 is "1". When "", multiple bits are "1"
Setting to is not allowed.

The register file switching scheduling register 1 is a register for designating which register file in the register file group 5 composed of a plurality of register files is to be used, and is composed of a plurality of bits. Is set. Register file switching Each bit in the scheduling register 1 corresponds to each register file of the register file group 5, and when (bp0 of scheduling register 1) = 1,
When register file 0 is selected (bp1 of scheduling register 1) = 1,
When register file 1 is selected (bp2 of scheduling register 1) = 1,
Register file 2 is selected ... (Scheduling register 1 bpn) = 1,
Register file n is selected.

The scheduling register 1 can set a plurality of bits. The register file switching control unit 2 detects the bit set to "1" in the logical sum data of the scheduling register 1 and the serial data reception register 12 and outputs the result to the selector circuit 14 (in this case, the serial data reception register 12 can set a plurality of bits to "1".) Therefore, the selector circuit 14 selects the register file 0 when (bp0 of the scheduling register 1) = 1 or (bp0 of the serial data reception register 12) = 1 (bp1 of the scheduling register 1) = 1 or (serial When bp1 of the data reception register 12 = 1, select the register file 1 When (bp2 of the scheduling register 1) = 1 or (bp2 of the serial data reception register 12) = 1, select the register file 2 ... .. (When the bpn of the scheduling register 1) = 1 or (the bpn of the serial data reception register 12) = 1, the register file selection signal 4 is output according to the condition of selecting the register file n.

On the other hand, the value of the serial data reception register 12 can also be independently input to the selector circuit 14 (however, the serial data reception register 12 cannot set a plurality of bits to "1"). Therefore, the selector circuit 14 receives (1) the detection output of the register file switching control unit 2 and (2) the output of the serial data receiving register 12 (input only to the serial data input terminal 11), and the value of the input selection flag 13 The above items (1) and (2) are selected. Also, input selection flag 1
According to the value of 3, the selector circuit 14 causes the register file group 5
The register file selection signal 4 for selecting each register file is output. The value of the input selection flag 13 is "
When it is 1 ″, the detection operation by the register file switching control unit 2 is stopped, so that the input of the register file switching timing signal 3 via the AND circuit 15 is prohibited.

By thus specifying the register file to be used in advance, the register file can be switched by the hardware without the program processing, and the register file can be directly switched by the terminal. Therefore, in multitask processing, it is possible to realize a system in which the overhead of the user program is minimized without burdening the user program when switching tasks.

FIG. 8 is a diagram showing the configuration of a multitask execution device for selecting / switching a register file by hardware through at least one input terminal of the present invention. In this example, a case where the input terminal is a serial data input terminal will be described. Each bit (bp0, 1, 2, to n) of the serial data input register 12 is input to the register file switching control unit 2, and the register file switching control unit 2 outputs the register file switching timing signal 3
The register file selection signal 4 is output in synchronism with, and the register files (register files 0, 1, 2, ... N) in the register file group 5 are selected. Data is input from the serial data input terminal 11 to the serial data input register 12 as serial data.

Input to the register file switching control unit 2 is performed by each bit (bp) of the serial data input register 12.
The register file switching control unit 2 selects the register file 0 when (bp0 of the serial data reception register 12) = 1, and (bp1 of the serial data reception register 12). ) = 1, register file 1 is selected, (bp2 of serial data receiving register 12) = 1, register file 2 is selected, ... (bpn of serial data receiving register 12) = 1 At this time, since the register file n can be selected, the register file selection signal 4 is output in synchronization with the register file switching timing signal 3.

Since the register file to be switched can be directly designated by the serial data input terminal, it is possible to realize a system in which overhead is minimized without burdening a user program when switching tasks in multitask processing.

[0042]

With this configuration, in multitask processing, there is no burden on the user program at the time of task switching, task switching can be executed according to external conditions, and a system with a minimum overhead can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram of a multitask execution device of the present invention.

FIG. 2 is a timing diagram of the multitask execution device of the present invention.

FIG. 3 is a block diagram of a multitask execution device of the present invention.

FIG. 4 is a timing diagram of the multitask execution device of the present invention.

FIG. 5 is a block diagram of a multitask execution device of the present invention.

FIG. 6 is a block diagram of a multitask execution device of the present invention.

FIG. 7 is a block diagram of a multitask execution device of the present invention.

FIG. 8 is a configuration diagram of a multitask execution device of the present invention.

[Explanation of symbols]

1 register file switching scheduling register 2 register file switching control unit 3 register file switching timing signal 4 register file selection signal 5 register file group 6 external signal group 7 AND-OR circuit 11 serial data input terminal 12 serial data reception register 13 input selection flag 14 Selector circuit

Claims (6)

[Claims] 1. A multi-task execution device for allocating one CPU to a plurality of register files in a time-sharing manner under the control of a register file switching control unit, and performing a plurality of tasks in a time-sharing parallel manner by the plurality of register files. The register file switching means is provided with a set of control registers for designating all of the plurality of register files that the CPU occupies in a time-sharing manner, and the CPU is time-divided with reference to the control registers. First register means for sequentially selecting / switching register files to be occupied by hardware and terminals corresponding to one-to-one with a part or all of the plurality of register files, and selecting the terminals to provide the plurality of registers. Second means for selecting / switching register file to be executed from hardware by hardware When the register file switching operation by the second means occurs while the register file switching operation is performed by the first means to perform a plurality of tasks in a time-division parallel processing, the first means is temporarily stopped. And a third means for executing the register file switching operation by the second means with priority. 2. A multi-task execution device that allows a plurality of register files to occupy one CPU in a time-division manner under the control of a register-file switching control unit and performs a plurality of tasks in a time-division parallel processing by the plurality of register files. The register file switching means is provided with a set of control registers for designating all of the plurality of register files that the CPU occupies in a time-sharing manner, and the CPU is time-divided with reference to the control registers. First register means for sequentially selecting / switching register files to be occupied by hardware and terminals corresponding to one pair to some or all of the plurality of register files, and selecting the terminals allows the plurality of register files to be selected. The second means to select and switch the register file to be executed from the hardware by hardware When the register file switching operation by the second means occurs when the register file switching operation is performed by the first means and a plurality of tasks are processed in time division parallel processing, the terminal by the second means is generated. Both the register file designated by the above-mentioned control register of the first means and the terminal of the second means can be handled as those designated by the control register of the first means. And a third means for sequentially selecting / switching register files to be occupied by the CPU in a time division manner by hardware. 3. A multi-task execution device that allows a plurality of register files to occupy one CPU in a time-sharing manner under the control of a register file switching control unit and performs a plurality of tasks in a time-sharing parallel manner by the plurality of register files. The register file switching means is provided with a set of control registers for designating all of the plurality of register files that the CPU occupies in a time-sharing manner, and the CPU is time-divided with reference to the control registers. The first means for sequentially selecting / switching the register file to be occupied by the hardware and the data inputted from at least one input terminal designates a part or all of the plurality of register files to be occupied by the CPU in a time sharing manner. Possible,
By inputting the data from the input terminal and selecting / switching the register file to be executed from the plurality of register files by hardware, the second means and the first means are operated to switch the register files to perform a plurality of operations. When the register file switching operation by the second means occurs during the time-division parallel processing of the task (1), the first means is temporarily stopped,
And a third means for executing the register file switching operation by the second means with priority. 4. A multi-task execution device for causing a plurality of register files to occupy one CPU in a time-sharing manner under the control of a register file switching control unit and performing a plurality of tasks in a time-sharing parallel manner by the plurality of register files. The register file switching means is provided with a set of control registers for designating all of the plurality of register files that the CPU occupies in a time-sharing manner, and the CPU is time-divided with reference to the control registers. The first means for sequentially selecting / switching the register file to be occupied by the hardware and the data inputted from the at least one input terminal are all or part of the plurality of register files to be occupied by the CPU in a time division manner. Can be specified,
By inputting the data from the input terminal and selecting / switching the register file to be executed from the plurality of register files by hardware, the second means and the first means are operated to switch the register files to perform a plurality of operations. When the register file switching operation by the second means occurs during the time-division parallel processing of the task (1), the register file designated by the input terminal by the second means also includes the register file of the first means. Cause the CPU to occupy in a time division manner with reference to both the control register of the first means and the input terminal of the second means, which can be treated as specified by the control register. A third means for sequentially selecting / switching register files by hardware. Task execution device. 5. A multi-task execution device that allows a plurality of register files to occupy one CPU in a time-sharing manner under the control of a register file switching control unit, and performs a time-sharing parallel processing of a plurality of tasks by the plurality of register files. The register file switching means is provided with a set of control registers for designating all of the plurality of register files that the CPU occupies in a time-sharing manner, and the CPU is time-divided with reference to the control registers. First register means for sequentially selecting / switching register files to be occupied by hardware and terminals corresponding to one-to-one with a part or all of the plurality of register files, and selecting the terminals to provide the plurality of registers. Second means for selecting / switching register file to be executed from hardware by hardware Alternatively, the data input from at least one input terminal can specify a part or all of the plurality of register files that the CPU occupies in a time-sharing manner, and by inputting the data from the input terminal, A third means for selecting and switching the register file to be executed from the plurality of register files by hardware is provided, and the register file is switched by the first means to perform a plurality of tasks in time division parallel processing. At this time, when the register file switching operation by the second means occurs, the first means is temporarily stopped and the register file switching operation by the second means is preferentially executed. Alternatively, the register file is switched by the first means to execute a plurality of tasks in a time division parallel processing manner. When the register file switching operation by the third means occurs during the operation, the register file specified by the terminal by the third means is also specified by the control register of the first means. A register file, which can be handled as one, is sequentially selected by hardware while referring to both the control register of the first means and the terminal of the third means, which register file is to be occupied by the CPU in a time-sharing manner. A multitask execution device, wherein any of the fifth means for switching can be switched by a flag. 6. A multi-task execution device that allows a plurality of register files to occupy one CPU in a time-sharing manner under the control of a register file switching control unit, and performs a time-sharing parallel processing of a plurality of tasks by the plurality of register files. Further, at least one input terminal is provided as a register file switching means, and the data input from the input terminal can specify all of the plurality of register files that the CPU occupies in a time-sharing manner. A multitask execution device characterized in that a register file to be executed is selected / switched by hardware from among the plurality of register files by inputting the data from.