JPH06149603A - Real time control circuit with checking function - Google Patents

Abstract

(57) [Abstract] [Object] The present invention relates to a real-time control circuit using a plurality of processing circuits. By duplicating the processing circuits,
It is an object of the present invention to realize a real-time control circuit that has a simple structure and can switch control circuits when an abnormality occurs and continue control processing and that is inexpensive. A real-time control circuit 100 including a plurality of control circuits 11 to 1n, a read-only memory 20, a random access memory 30, and an input / output circuit 40,
An address check circuit 50 for checking the address output by the control circuit 1i in the control operation, an operation check circuit 60 for checking that the control circuit 1i in the control operation is operating, the address check circuit 50 and the operation check circuit When an abnormality is detected from the output of 60, a switching circuit 70 is provided to switch the control circuit 1i in control operation to the next control circuit 1j.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a real-time control circuit using a plurality of processing circuits. In recent years, high-performance microprocessors have become available at low cost, so the hardware of various electronic devices and communication devices (collectively referred to as electronic devices below) is realized by a microprocessor and a real-time control circuit by firmware control. By doing so, downsizing and economicization have come to be performed.

On the other hand, as the functions of electronic devices controlled by firmware have become more sophisticated and complex, the number of steps of the firmware program has increased, and the processing speed of hardware has also become faster. In addition, the environment in which the equipment is installed has been demanded from an air-conditioned room to cope with adverse conditions such as in a non-air-conditioned room.
Equipment failures due to these congestion causes are increasing.

There is a demand for a real-time control circuit having a check function, which is controlled by a plurality of processors in order to maintain high reliability of an electronic device controlled by such a real-time control circuit.

[0004]

2. Description of the Related Art FIG. 4 shows a block diagram for explaining a conventional example. The figure shows a microprocessor as a control circuit (MP
An example of a real-time control circuit (which may be a system) 100A for performing control by U) is shown. 11A in the figure
Is an MPU that controls the real-time control circuit 100A, 2
Reference numeral 0 is a read only memory (hereinafter referred to as ROM) in which a program for the MPU 11A to execute the control operation is written, and 30 is a random access memory in which data to be input / output for the MPU 11A to execute the control operation is written. (Hereinafter referred to as RAM) 40 is an input / output circuit (hereinafter referred to as I / O circuit) for executing a control operation based on the processing result of the MPU 11A.

In the configuration shown in the figure, the MPU 11A is a ROM
20 read the program written in the RAM
The data written in the designated address of 30 is used as an input to execute the processing, and the result is used to control the I / O circuit 40, thereby performing control as the real-time control circuit 100A.

[0006]

The above-mentioned conventional real-time control circuit 100A operates under the control of one MPU 11A. Real-time control circuit 1 with this configuration
00A operates in real time, and if a failure occurs due to some external factor or internal factor, the system goes down, and since it is a real time operation, the system down is a serious problem.

Further, as one method for avoiding the system down, it is possible to duplicate all the hardware and switch the system when a failure occurs, but it is possible to deal with it by increasing the system size. The amount of wear increases and it becomes difficult to deal with it. In addition, even if the system down due to disturbance takes a redundant configuration,
Since each piece of the duplicated hardware is affected by the disturbance under the same condition, the pieces of the duplicated hardware may stop at the same time.

By duplicating only the control circuit, the present invention aims to realize a real-time control circuit which has a simple structure and is capable of continuing the control process by switching the control circuit when an abnormality occurs and at a low cost.

[0009]

FIG. 1 is a block diagram for explaining the principle of the present invention. In the figure, 100 is a real-time control circuit including a plurality of control circuits for controlling an electronic device, 11 to 1n are a plurality of control circuits for controlling the operation of an electronic device (not shown), and 20 is a plurality of control circuits 11 ~
1n is a ROM in which a program for executing a control operation is written, and 30 is a plurality of control circuits 11 to 1n.
Is a RAM in which data to be input / output for executing control operations is written, and 40 is a plurality of control circuits 11 to 1
Reference numeral n is an input / output circuit 40 for executing a control operation based on the processing result.

Further, 50 is provided by the present invention, and is an address check circuit for checking the address output by the control circuit 1i in control operation, and 60 is the control circuit 1i in control operation. An operation check circuit 70 is a switching circuit for switching the control circuit 1i in the control operation to the next control circuit 1j when an abnormality is detected from the outputs of the address check circuit 50 and the operation check circuit 60. During the control operation of one control circuit 1i of the control circuits 11 to 1n, the address check circuit 50 and the operation check circuit 60 check the normality of the operation of the control circuit 1i. The switching control operation from the processing device 1i to the next control device 1j is continued by 70.

[0011]

One control circuit 1i of the plurality of control circuits 11 to 1n reads out the data in the RAM 30 to read the data from the ROM 20.
The process is executed according to the program of
Control data is output through the I / O circuit 40 to control an electronic device (not shown).

At this time, the address check circuit 50 checks the address generated by the control circuit 1i, and the operation check circuit 60 checks that the control circuit 1i is operating.

When the address check circuit 50 and the operation check circuit 60 make a check and an abnormality is detected, the switching circuit 70 continues the switching control operation from the processing device 1i to the next control device 1j.

[0014]

FIG. 2 is a block diagram illustrating an embodiment of the present invention. The figure shows an example in which two MPUs 11A and 12A are used.

The ROM 20, the RAM 30, the I / O circuit 40, the address check circuit 50, the operation check circuit 60, and the switching circuit 70 in the figure are the same as those described in the principle diagram. In this embodiment, an MPU is further added. A restart & data memory 80 and an I / O data memory 90 for starting from the middle of processing when switching are provided. FIG. 3 is a diagram for explaining the operation of the embodiment of the present invention. The operation of the embodiment will be described below with reference to FIGS.

First, when each subroutine SB is processed, the subroutine SB writes initial setting data in the start & data memory 80. In the process in the subroutine SB, the data by the write command is restarted &
The data is written in the data memory 80.

When the processing of the subroutine SB is completed normally, the write data written in the start & data memory 80 is read and written in the designated address of the RAM 30.

It is assumed that the MPU 11A controls at the start. When the MPU 11A is operating, the address check circuit 50 checks the address output by the MPU 11A. If an address outside the set range is detected, it is determined that the MPU 11A has malfunctioned and a switching instruction is output to the switching circuit 70.

Further, the operation check circuit 60 is the MPU 11
It is composed of a counter that is reset each time A operates, and if it is not reset for a certain period of time, it determines that the operation is stopped and outputs a switching instruction to the switching circuit 70.

The switching circuit 70 is an address check circuit 50.
Alternatively, when a switching instruction is input from the operation check circuit 60, the MPU 11A is switched to the MPU 12A, the flag A of the flag memory F for displaying the switching state is set to "ON", and the operation of the MPU 12A is started.

Since the flag A is "on", the MPU 12A knows that the process has started in the middle of the process. In this case, the MPU 12A can start in the middle of the process by reading the information in the restart & data memory 80.

The I / O data memory 90 is a subroutine S
I / O data is stored in memory for each B, and is cleared when the processing ends normally. Restart & data memory 80
For example, a restart address is set for each program delimiter in the subroutine SB or the like, and data is set so as to be restartable.

All data and write data processed in one subroutine SB are written in the restart & data memory 80. When the processing of the subroutine SB is completed normally, the restart & data memory 8
The write data written in 0 is read out and written in the designated address of the RAM 30.

By writing data in this way, even if a malfunction occurs in a certain subroutine SB,
From the data written in the restart & data memory 80 and the restart address, MPU 11A to M
It becomes possible to switch to the PU 12A and continue the processing.

Here, the reason why the data generated by the processing of the subroutine SB is not directly written to the designated address of the RAM 30 is to prevent the contents of the RAM 30 from being rewritten with the wrong data when a malfunction occurs. The method of once writing into the restart & data memory 80 is adopted.

Similarly, the I / O data memory 90 also writes the data input / output to / from an input / output device (not shown) into the I / O data memory 90 and stores it as input / output information during the processing of one subroutine SB. Keep it. This information is cleared when the processing of this subroutine SB ends normally. When switching is performed due to the occurrence of an abnormality, the input / output information can be known from this information, and the processing can be continued.

With this configuration, it is possible to minimize the system down when an abnormality occurs and to continue the operation. If an error occurs during the debugging of the real-time control circuit 100, the MPU process is stopped and the contents of the restart & data memory 80 and the I / O data memory 90 are checked to determine the cause of the error. You can look it up.

[0028]

According to the present invention, in a real-time control system in which control is performed by a plurality of processing devices, an address check circuit and an operation check circuit are provided, and the processing device is provided when the address check circuit and the operation check circuit detect an abnormality. The switching process can be restarted.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram illustrating an embodiment of the present invention.

FIG. 3 is a diagram for explaining the operation of the embodiment of the present invention.

FIG. 4 is a block diagram illustrating a conventional example.

[Explanation of symbols]

 100, 100A Real-time control circuit 11-11n Control circuit 11A, 12A MPU 20 ROM 30 RAM 40 I / O circuit 50 Address check circuit 60 Operation check circuit 70 Switching circuit 80 Restart & data memory 90 I / O data memory SB Subroutine F Flag memory

Claims (2)

[Claims] 1. A real-time control circuit including a plurality of control circuits for controlling an electronic device, the plurality of control circuits (11 to 1) controlling an operation of the electronic device.
n), a read-only memory (20) in which a program for the plurality of control circuits (11 to 1n) executes a control operation, and a plurality of the control circuits (11 to 1n) execute a control operation. A random access memory (30) for writing data to be input / output for performing the input / output, and an input / output circuit (40) for executing a control operation based on the processing results of the plurality of control circuits (11 to 1n). In the real-time control circuit (100), an address check circuit (50) that checks an address output by the control circuit (1i) that is in control operation, and that the control circuit (1i) that is in control operation are operating. An abnormality is detected from the operation check circuit (60) to be checked, and the outputs of the address check circuit (50) and the operation check circuit (60). Come, the control circuit in the control operation of the (1i) following said control circuit (1j)
A switching circuit (70) for switching is provided, and the address check circuit (50) and the operation check circuit (60) are provided while one of the plurality of control circuits (11 to 1n) is in control operation. ), The normality of the operation of the control circuit (1i) is checked, and when an abnormality is detected, the switching circuit (70) switches the processing device (1i) to the next control device (1j). A real-time control circuit with a check function characterized by continuing operation. 2. In the real-time control circuit (100) with a check function according to the preceding paragraph, the setting data of a subroutine (SB) in which the plurality of control circuits (11 to 1n) execute processing, and the processing of the subroutine (SB). Is provided with a restart & data memory (80) for writing the data generated by each of the subroutines, and an input / output data memory (90) for writing the input / output data generated for each of the subroutines. 1) during the control operation of the control circuit (1i), the subroutine (S
When the process of B) is started, the setting data required for the subroutine (SB) is written in the restart & data memory (80), and then the process of the subroutine (SB) is started, and the subroutine (SB) is started. Data written by the write command in () is written in the restart & data memory (80), input / output data is written in the input / output data memory (90), and the address check circuit (50) and the operation check circuit are written. At (60), the normality of the operation of the control circuit (1i) is checked, and when an abnormality is detected, the switching circuit (70) causes the processing device (1i) to switch to the next control device (1j). After switching, the data written in the restart & data memory (80) is read and restarted in the middle of the processing of the subroutine (SB). Claim 1 check function with real-time control circuit, wherein the door.