JPH06149765A - Shared memory exclusive control automatic release method - Google Patents

Abstract

(57) [Summary] [Purpose] When a processor under exclusive control fails, another processor recognizes it and cancels the exclusive control, allowing normal processor processing to continue, and The technical purpose is to improve the processing capacity. [Configuration] In each memory pool (4) of the shared memory (1),
A state display unit (4a) indicating whether or not the memory pool (4) is under exclusive control, and a first processor that stores a processor ID that identifies a processor (2) that is under exclusive control of the memory pool (4). An ID storage unit (4b) is provided, and a buffer (2a) for storing the processor ID of the first processor ID storage unit (4b) and another processor (2) are in an access state to each processor (2). And an access counter (2b) for counting the number of access requests to the memory pool (4).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system having a plurality of processors and activating them in parallel to perform processing. In particular, when any processor is accessing a shared memory, the other processors are processed. The present invention relates to a multiprocessor system that performs exclusive control to prevent access by a user.

[0002]

2. Description of the Related Art A computer system consists of a hardware resource (hereinafter referred to as a resource) consisting of a memory, a processor, an input / output device, etc., and a control program, ie software, for allocating the resource to each task and controlling its operation. It consists of

Recently, a multi-task system has been known in which a software has a function of enabling a plurality of tasks to be processed in parallel by a single processor by a time division multiplex system. The multitasking method has an advantage that resources can be efficiently shared among a plurality of tasks, the arithmetic processing can be performed at high speed, and the processing capacity of the entire computer system is improved.

However, since the amount of information processing has increased remarkably in recent years, there has been a problem that it takes a very long time to perform such information processing by one processor. Therefore, a multiprocessor system having a plurality of processors has become widespread. I'm doing it.

In some multiprocessor systems, resources such as a main memory are shared by a plurality of processors for operation. This concrete structure is shown in FIG.

In FIG. 1, the multiprocessor system is constructed by connecting N processors and a shared memory to be shared by these processors by a common bus.
Here, the shared memory is composed of a plurality of independent memory pool groups, and in order to prevent a plurality of processors from accessing the same memory pool of the shared memory at the same time, that is, an arbitrary processor has a memory pool. Exclusive access control is performed to prevent other processors from accessing the same memory pool while accessing the memory.

In this exclusive control, an exclusive control flag is provided in the head address area of each memory pool, and this flag is set to "
When it is "0", it means that the exclusive control is not performed and the access is possible. On the other hand, when this flag is "1", the exclusive control is being performed, that is, an arbitrary processor is accessing the memory pool. I try to show that.

As a result, each processor refers to the exclusive control flag of the start address of the memory pool to which it accesses, and if this flag is "0", it accesses that memory pool and sets this flag. ”
The value is changed to 1 ”. Then, after the access is completed, the flag is set back to“ 0 ”again.

On the other hand, when the exclusive control flag is "1" when an access is attempted, the processor once suspends its activation and refers to the exclusive control flag again after a lapse of a certain time. Here, if the flag is "0", the memory pool is accessed, and if it is "1", a pause for a certain time is performed again.

As a result, the shared memory can be shared by a plurality of processors, and the processing of the system can be smoothly performed.

[0011]

However, in the system described above, when the processor accessing an arbitrary memory pool goes down, the exclusive control flag remains fixed at "1" and other normal processors However, there is a problem in that the access to the memory pool is hindered, which causes a reduction in the processing capacity of the entire system.

Therefore, the present invention has been made in view of the above problems, and when a processor under exclusive control fails for some reason, another processor recognizes the failure and the exclusive control is executed. By canceling the above, it is a technical subject to enable the normal processor to continue the processing of the system and improve the processing capacity of the entire system.

[0013]

In order to solve the above-mentioned problems, the present invention will be described below with reference to the principle diagram of FIG.

The multiprocessor system according to the present invention comprises a shared memory 1 having a plurality of memory pools 4 and a plurality of processors 2. The first means for solving the above problem is that each memory pool 4 is provided with a status display means 4a and a processor ID storage section 4b.

On the other hand, each processor 2 has a buffer 2
a, access counter 2b. The above-mentioned status display means 4a is provided for the processor 2 whose memory pool 4 is arbitrary.
Indicates whether or not it is in the access state.

The processor ID storage unit 4b stores a processor ID that identifies the processor 2 that is accessing the memory pool 4. Also, buffer 2
a is for copying / registering the processor ID stored in the processor ID storage unit 4b.

The access counter 2b counts the number of times an access request is issued to a specific memory pool 4. Further, each memory pool 4 has a counter 4 that is incremented when access by an arbitrary processor 2 is permitted.
You may make it provide c.

Next, as a second means for solving the above problems, each memory pool 4 has a status display means 4a,
First processor ID storage unit 4b, second processor I
The D storage unit 4d is provided.

On the other hand, each processor 2 has a buffer 2
a and access counter 2b. Here, the state display unit 4a described above indicates whether or not the memory pool 4 is in an access state by an arbitrary processor 2 as in the case of the first solving unit described above.

The first processor ID storage section 4b stores the processor ID of the processor 2 accessing the memory pool 4. Second processor I
The D storage unit 4d stores the processor ID of the processor 2 in which the failure has occurred while accessing the memory pool 4.

The buffer 2a also copies and stores the processor ID registered in the first processor ID storage unit 4b. The access counter 2b counts the number of access requests issued to the memory pool 4.

Further, the status display means 4a is provided with a first
When the processor ID is stored in the processor ID storage unit 4b, the function of displaying the access state by the processor 2 corresponding to the processor ID may be added. In this case, when the processor IDs are stored in both the first processor ID storage unit 4b and the second processor ID storage unit 4d, it is indicated that the memory pool 4 is in the double access state by the two processors 2. Add the function to display.

Next, the third means for solving the above problems will be described below. Status display means 4 is provided in each memory pool 4.
a, processor ID storage unit 4b.

On the other hand, each processor 2 has a matching means 2c.
Be prepared. Here, the status display means 4 described above
“A” indicates whether the memory pool 4 is being accessed by any processor 2, is not being accessed by any of the processors 2, or in other words, is accessible from the access state.

The processor ID storage unit 4b stores a processor ID for identifying the processor 2 that is accessing when the memory pool 4 is in an access state.

On the other hand, in the processor 2, the matching means 2
The c collates the processor ID registered in the processor ID storage unit 4b with the own processor ID.

[0027]

According to the first means of the present invention, when the processor 2 accesses an arbitrary memory pool 4 of the shared memory 1, the state display means 4 of the memory pool 4 is provided.
See a.

When the accessible state of the memory pool 4 is displayed by the state display means 4a,
The processor ID that identifies the processor 2 is stored in the processor ID storage unit 4b. Here, the status display unit 4a displays the access status of the memory pool 4.

On the other hand, when the status display means 4a is displaying the access status of the memory pool, the access counter 2b is incremented and the processor I
Copy the processor ID of the D storage unit 4b to the buffer 2a.
Store.

After a lapse of a predetermined time, the processor 2 makes another access request to the memory pool 4. That is, the state display unit 4a is referred to and it is determined whether the memory pool 4 is in the access state or the accessible state.

If it is in the accessible state, the processor ID of itself is registered in the processor ID storage section 4b and the memory pool 4 is accessed as described above. On the other hand, if the other processor is in an access state, the processor 2 collates the processor ID stored in the buffer 2a with the processor ID stored in the processor ID storage unit 4b.

If the two processor IDs do not match, the value of the access counter 2b is reset and the same processing as above is repeated. If the two processor IDs match, it is determined that some failure has occurred in the processor 2 corresponding to this processor ID. Then, after displaying the accessible state on the state display means 4a, the processor I of the processor ID storage unit 4b is displayed.
Rewrite D to its own processor ID. This allows
The exclusive control state by the faulty processor 2 is released, and the processor 2 becomes accessible.

Next, the case where the counter 4c is provided in each memory pool 4 will be described. Any processor 2
When accessing the memory pool 4, the state display means 4a is referred to. Then, it is determined whether or not the memory pool 4 is in the access state, that is, the exclusive control state, by another processor 2.

Here, if the memory pool 4 is accessible, the processor 2 determines the processor ID.
The own processor ID is stored in the storage unit 4b. At this time,
The value of the counter 4c is incremented by one.

On the other hand, when the memory pool 4 is in the exclusive control state, the value of the counter 4c is stored in the buffer 2a together with the processor ID of the processor ID storage unit 4b. After the elapse of a predetermined time, the processor 2 makes another access request to the memory pool 4.

If the accessible state is displayed on the state display means 4a, the processor 2 executes the access process to the memory pool 4. That is, the processor ID storage unit 4b stores its own processor ID and then accesses the memory pool 4. At this time counter 4
c is incremented by one.

When the exclusive control status is displayed on the status display means 4a, the processor 2 collates the processor ID stored in the buffer 2a with the processor ID in the processor ID storage section 4b, and at the same time, the buffer 2
The counter value stored in a is compared with the counter value of the counter 4c.

If either the processor ID or the counter value does not match, the new processor ID and the new counter value are stored in the buffer 2a. Further, after resetting the value of the access counter 2b, it is incremented by one.

When both the processor ID and the counter value match, the processor 2 increments the value of the access counter 2b by one. The above operation is repeated, and when the value of the access counter 2b reaches a specific value, the processor I of the processor ID storage unit 4b is processed.
It recognizes that some failure has occurred in the processor 2 corresponding to D, and changes the state display means 4a to the accessible state. After that, the processor ID storage unit 4b stores its own processor ID, and the counter 4c is incremented by one.

According to the second means of the present invention, the processor 2 refers to the status display means 4a when accessing the memory pool 4. As a result, whether the memory pool 4 is being accessed by another processor 2,
That is, it is determined whether or not the exclusive control state is set.

When the memory pool 4 is accessible, the processor ID of its own processor 2 is stored in the first processor ID storage section 4b. On the other hand, when the memory pool 4 is in the exclusive control state, the processor ID of the first processor ID storage unit 4b is set to the buffer 2a.
To the access counter 2b (only for the first time)
Increment the value of.

After that, when a predetermined time has elapsed, another access request is issued. Then, when this process is repeated and the value of the access counter 2b reaches a specific value,
The processor 2 collates the processor ID stored in the buffer 2a with the processor ID in the first processor ID storage unit 4b.

If the two processor IDs match, it is determined that some failure has occurred in the processor 2 corresponding to the processor ID in the first processor ID storage section 4b. Then, this processor ID is stored in the second processor ID storage section 4d, and the status display means 4a is stored.
To display the accessible status. As a result, the processor 2 assigns its own processor ID to the first processor I.
It becomes possible to store the data in the D storage unit 4b and access the memory pool 4.

Here, in the present invention, when the exclusive control by the faulty processor is forcibly released, the first processor ID storage unit 4b and the second processor ID storage unit 4 are
Since the processor IDs are stored in both d, this state (double access state) is displayed in the state display means 4 described above.
It can be displayed by a. As a result, when ending the access to the arbitrary memory pool 4, the processor 2 refers to the first processor ID storage unit 4b and the second processor ID storage unit 4d.

Here, the first processor ID storage unit 4b
If only the processor ID is stored, the processor ID is erased after confirming that the processor ID and the own processor ID match, and the access to the memory pool 4 is terminated.

When the processor IDs are stored in both the first processor ID storage unit 4b and the second processor ID storage unit 4d, the self processor ID and the first processor ID storage unit 4b and The respective processor IDs of the second processor ID storage unit 4d are compared.

If the self processor ID and the processor ID of the second processor ID storage unit 4d match, the self processor ID is erased from the second processor ID storage unit 4d.

On the other hand, when the own processor ID matches the processor ID in the first processor ID storage unit 4b, this processor ID is deleted and the processor ID in the second processor ID storage unit 4d is set to the first processor ID. It is stored in the processor ID storage unit 4b.

As a result, when a processor accessing an arbitrary memory pool fails for some reason, the processor trying to access this memory pool recognizes the occurrence of the failure of the processor, and the memory pool concerned is recognized. It is possible to release the exclusive control related to. Therefore, another normal processor can access the memory pool.

Next, according to the third means of the present invention, the processor 2 accesses each memory pool 4 of the shared memory 1 when the processor 2 is restarted from the occurrence of a failure.
Then, in each memory pool 4, the status display means 4a
It is determined whether or not the memory pool is being accessed by any processor 2 by referring to.

When the memory pool 4 is in the access state, the collating means 2c collates the processor ID stored in the processor ID storage section 4b of this memory pool 4 with its own processor ID.

Here, the self processor ID and the processor I of the processor 2 accessing the memory pool 4
When D matches, the processor 2 rewrites the status display unit 4a to the accessible state and erases the processor ID in the processor ID storage unit 4b.

As described above, according to the third means, when an arbitrary processor fails during exclusive control of a memory pool, that processor automatically executes the memory pool which it has been in exclusive control after the failure is repaired. Can be detected. Further, the exclusive control of the memory pool can be released.

[0054]

EXAMPLES Specific examples of the present invention will be described below.

[0055]

First Embodiment FIG. 2 shows a schematic configuration of a multiprocessor system according to the first embodiment. The multiprocessor system according to the first embodiment includes N first to Nth (N: natural number) N processors 5 and a single shared memory 6.

The shared memory 6 comprises first to third memory pools having mutually independent addresses. This specific description will be described later. Then, the first embodiment
In (1), when any processor 5 is accessing any memory pool 7, exclusive control is performed to prevent another processor 5 from accessing this memory pool 7.

FIG. 3 is a block diagram of the internal structure of the memory pool in the first embodiment. The memory pool 7 in this embodiment is composed of an exclusive control area 8 and a data area 9.

The exclusive control area 8 is an area for storing exclusive control information performed when an arbitrary processor 5 accesses the memory pool 7, and is a flag bit as a status display means according to the present invention. 8a and a processor ID storage unit 8b.

The flag bit 8a indicates the memory pool 7 concerned.
It indicates whether or not there is a processor 5 that is accessing the device, that is, whether or not exclusive control is being performed. When exclusive control is being performed, "1" is set, and when it is accessible, "0" is set. .

The processor ID storage section 8b is an area for storing a processor ID for identifying the processor 5 accessing the memory pool 7, and when there is no processor 5 accessing the memory pool 7, that is, the memory pool 7 is Reset state if accessible ”
0 ".

Next, FIG. 4 is a block diagram of the internal configuration of the processor according to the first embodiment. The processor 5 according to the first embodiment includes a task 10 assigned to the processor 5, an operating system unit 14, an access counter 11, a timer 12, and a buffer 13.

The task 10 issues an arbitrary processing instruction to the processor 5. The operating system unit 14 manages the basic operation of the processor 5.

The access counter 11 is for counting the number of times that the processor 5 has issued an access request to a specific memory pool 7 in the exclusive control state by another processor 5.

When an access request is made to the memory pool 7 under exclusive control, the timer 12 measures the waiting time until the access request is made again. Buffer 13
When the processor 5 issues an access request to the memory pool 7 under exclusive control, the processor ID for identifying the processor under exclusive control is read from the processor ID storage unit 8b and stored therein. It is a thing.

Next, the operation process of exclusive control automatic cancellation in the first embodiment will be described with reference to the flowchart of FIG. When task 10 of processor 5 in the first embodiment issues a shared memory acquisition system call (step 5)
01), the operating system unit 14 in the processor 5 locks the bus connecting the shared memory 6 and the processor 5 (step 502).

Next, the operating system section 1
4 refers to the flag bit 8a of the exclusive control area 8 by accessing the corresponding memory pool 7 in the shared memory, and is under exclusive control (flag bit 8a is "1") or accessible (flag bit 8a is " 0 ") is recognized (step 503). Here, when the flag bit 8a is "1", that is, when the exclusive control is being performed, the operating system unit 14 reads the processor ID of the processor ID storage unit 8b in the exclusive control area 8 and stores it in the processor 5 concerned. To be stored in the buffer 13 (only for the first time)
At the same time, the value of the access counter 11 is incremented (step 504). Further, the lock of the bus connecting the processor 5 and the shared memory 7 is released (step 505).

The operating system unit 14
Starts the timer 12 and enters a sleep state for a fixed time. After the timer 12 has finished measuring time, the access counter 1
The value of 1 is referred to, and it is determined whether or not it has reached a specific value (step 507).

Here, if the specified value is not reached, the above-mentioned processing from step 502 is repeated, and if the specified value is reached, the operating system unit 14 of the processor 5 locks the shared memory 6 with the bus. After that, the exclusive control area of the corresponding memory pool 7 in the shared memory 6 is accessed, the value of the flag bit 8a is set to "0", and the processor ID storage unit 8b is reset ("
0 ") (step 509).

Then, the operating system unit 14 sets the value of the flag bit 8a in the exclusive control area of the corresponding memory pool 7 to "1", and further writes its own processor ID in the processor ID storage unit 8b (step 510). .

The operating system unit 14 unlocks the bus connecting the processor 5 and the shared memory 6 (step 511), and performs the processing related to the system call (step 512).

After the above processing is completed, the operating system unit 14 converts the value of the flag bit 8a of the exclusive control area in the memory pool 7 from "1" to "0" and resets the processor ID storage unit 8b ( "0") (step 513).

When the value of the flag bit 8a is "0" in the above step 503, the operating system section 14 performs the processing of the above step 510 and thereafter.
Therefore, according to the first embodiment, when the same processor accesses a specific memory pool for a predetermined time or longer, another processor recognizes this and recognizes that a failure has occurred in the processor. Exclusive control of the memory pool can be released. As a result, the processing of the multiprocessor system can be continued without affecting other normal processors.

[0073]

Second Embodiment The configuration of a multiprocessor system according to the second embodiment is composed of N processors 5 and a single shared memory 6.

The configuration of each processor 5 is the same as that of the first embodiment.
And is composed of a task 10, an operating system unit 14, an access counter 11, a timer 12, and a buffer 13.

FIG. 6 shows the internal configuration blocks of the memory pool 7 in the second embodiment. The memory pool 7 according to the second embodiment has a counter 8c in the exclusive control area 8 as compared with the first embodiment. Other configurations are the same as those in the first embodiment described above, the exclusive control unit 8 has a flag bit 8a and a processor ID storage unit 8b, and the data area 9 is composed of a plurality of memory pools.

The counter 8c corresponds to the memory pool 7
Is incremented by the processor 5 that is permitted to access the memory pool, that is, incremented for each processor 5 that exclusively controls the memory pool 7.

FIG. 7 is a flow chart showing the operation process of exclusive control automatic cancellation in the second embodiment. In the processor 5, when the task 10 assigned to itself issues a shared memory acquisition system call (step 70).
1) The operating system unit 14 of the processor 5 locks the bus connecting the processor 5 and the shared memory 6 (step 702).

The operating system section 14 is
An access request is made to the memory pool 7 related to the system call, and the flag bit 8a in the exclusive control area 8 of the memory pool 7 is referred to determine whether or not the memory pool 7 is under exclusive control (step 703). .

Here, when the memory pool 7 is under exclusive control, that is, when the flag bit 8a is "1", the operating system unit 14 determines the processor ID and the counter of the processor ID storage unit in the exclusive control area. The counter value of 8c is stored in the buffer 13 (only for the first time), and the access counter 11 of itself is incremented (step 704).

The operating system unit 14
Unlocks the bus connecting the processor 5 and the shared memory 6 (step 705), activates the timer 12, and enters a sleep state for a specific time (step 70).
6).

After the timer 12 finishes measuring the time, the operating system unit 14 refers to the access counter 11 to determine whether or not the access request to the memory pool 7 has been made a specified number of times (step 707). here,
If the number of times is less than the specified number of times, the processing from step 702 described above is repeated.

On the other hand, if the specified number of times has been reached, the processor ID and the counter 8 in the processor ID storage section 8b are counted.
The counter value of c is compared with the processor ID and the counter value stored in the buffer 13 (step 7
08), if any one of them does not match, the new processor ID and the counter value are stored in the buffer 13, the access counter 11 of its own is reset and incremented by one, and then the processes of step 702 and thereafter are repeated. .

On the other hand, if they match each other, the operating system unit 14 locks the shared memory 6 by bus and then sets the flag bit 8a of the exclusive control area 8 of the corresponding memory pool 7 in the shared memory 6 to "1". From "0"
And the processor ID storage unit 8b is reset (step 709).

Further, the operating system unit 14 sets the flag bit 8a in the exclusive control area 8 of the corresponding memory pool 7 to "1", writes the processor ID of itself in the processor ID storage unit 8b, and sets the counter 8c. Increment (step 710).

The operating system unit 14
Releases the bus lock of the shared memory 6 (step 71
1) Perform processing related to the system call. (Step 712).

After the above processing is completed, the operating system unit 14 changes the flag bit in the exclusive control area 8 from "1" to "0" and resets the processor ID storage unit 8b (step 713).

Therefore, according to the second embodiment, it is possible to determine whether the same processor is accessing the specific memory pool multiple times or continuously accessing the specific memory pool for a predetermined time or longer. When the access is continued for a predetermined time or longer, it is possible to recognize that the processor has a failure. As a result, another normal processor can access the memory pool.

[0088]

Third Embodiment A multiprocessor system according to the third embodiment is composed of N processors 5 and a single shared memory 6.

The configuration of each processor 5 is the same as that of the first embodiment.
And is composed of a task 10, an operating system unit 14, an access counter 11, a timer 12, and a buffer 13.

FIG. 8 shows internal configuration blocks of the memory pool 7 in the third embodiment. The memory pool 7 in the third embodiment has two processor ID storage units in the exclusive control area 8 as compared with the first embodiment. Here, one is the first processor ID storage 8b and the other is the second processor ID storage 8d. Also,
The flag bit 8a in the third embodiment has a double digit, and “00” can access the memory pool 7.
"01" indicates that exclusive control is in progress, and "11" indicates that dual exclusive control is in progress (double access state).

The other structure is the same as that of the first embodiment, and the data area 9 is composed of a plurality of memory pools. The first processor ID storage unit 8b stores the processor ID of the processor that exclusively controls the memory pool 7.

On the other hand, the second processor ID storage section 8d
The processor ID of the processor in which a failure has occurred during exclusive control of the memory pool 7 is stored. Figure 9
FIG. 16 is a flowchart showing a process of shared memory access request processing in the third embodiment.

In the third embodiment, when the task 10 assigned to the processor 5 issues an acquisition system call for the shared memory 6 (step 901), the operating system unit 14 of the processor 5 sends the processor 5 and the shared memory 6 to each other. The bus to be connected is locked (step 902).

Next, the operating system unit 14
Refers to the exclusive control area 8 in the corresponding memory pool 7 of the shared memory 6 to determine whether the flag bit 8a is "00" (step 903).

Here, when the flag bit 8a is "00", the flag bit 8a of the corresponding memory pool 7 in the shared memory 6 is set to "01", and its own processor ID is stored in the first processor ID storage unit 8b. Store (step 91)
0).

The operating system unit 14
Releases the bus lock of the shared memory 6 (step 91
1), the memory pool 7 is accessed to execute the process related to the system call (step 912).

On the other hand, when the flag bit 8a of the memory pool 7 is other than "00" in step 903, the processor ID stored in the first processor ID storage section 8b is stored in the buffer 13 (1 The value of the access counter 11 is incremented by one at the same time (step 904).

The operating system unit 14
Releases the bus lock of the shared memory 6 (step 905) and starts the timer 12 (step 90).
6). Here, the operating system unit 14 suspends its operation while the timer 12 measures a certain time.

When the timer 12 finishes measuring the fixed time, the operating system section 14 collates the processor ID in the first processor ID storage section 8b with the processor ID registered in the buffer 13 (step 907).
If they do not match, the above-described processing from step 902 is performed.

On the other hand, if they match, the operating system unit 14 determines whether or not the value of the access counter 11 has reached the designated value (step 908). When the value of the access counter 11 reaches the designated value, the operating system unit 14 determines that the processor 5 corresponding to the processor ID in the first processor ID storage unit 8b has failed. In this case, the flag bit 8a of the corresponding memory pool 7 in the shared memory 6 is set to "11",
The processor ID of the first processor ID storage unit 8b is set to the second
The processor ID storage unit 8d stores the new processor ID of its own processor 5 in the first processor ID storage unit 8b (step 909).

Next, the operating system unit 14
The processing from step 911 onwards is performed. If the value of the access counter 11 has not reached the specified number of times in step 908, the processing from step 902 onward is repeated.

Next, FIG. 10 is a flow chart showing the process of shared memory return processing. When a task in the processor 5 issues a shared memory return system call (step 1001), the operating system unit 14 locks the bus connecting the processor 5 and the shared memory (step 1002).

Next, the operating system section 1
4 refers to the flag bit 8a in the exclusive control area 8 and determines whether "01" is set or "11" is set (step 1003).

When the flag bit 8a is "01", the issuer of this system call is the processor 5 corresponding to step 910 in FIG. 9 described above, and the operating system unit 14 of this processor 5 is
The bus lock to the shared memory 6 is released (step 100
9), the process related to the system call is performed (step 1010). And the operating system section 1
4 sets the flag bit "01" in the exclusive control area to "0"
0 "and the first processor ID storage unit 8b
Is reset to "0". At this time, in the exclusive control area, "00" is set in the flag bit 8a, and the first bit
The processor ID storage unit 8b and the second processor ID storage unit 8d are in the reset state "0".

On the other hand, in step 1003 described above,
If the flag bit 8a is set to "11", it means the shared memory return processing from the processor corresponding to the above step 909 of FIG. 9, and the operating system unit 14 releases the bus lock to the shared memory 6. Then (step 1004), the flag bit "11" of the exclusive control area 8 is changed to "01" (step 100).
5).

Next, the operating system unit 14
Determines whether the processor ID of the processor 5 matches the processor ID of the first processor ID storage unit 8b of the exclusive control area 8 or the processor ID of the second processor ID storage unit 8d (step 1006). .

Here, the processor I of the processor 5 is
If D matches the processor ID of the second processor ID storage unit 8d, the processor 5 is the processor in which the failure has occurred in FIG. 9 described above, and the shared memory return processing is performed after the processor 5 recovers from the failure. It is something that will be done. On the other hand, the processor ID of the processor 5
Is matched with the processor ID of the first processor ID storage unit 8b, the processor 5 automatically cancels the exclusive control by the failed processor in FIG. 9 and accesses the memory pool 7. It is a processor.

In step 1006 described above, when the processor ID matches the processor ID of the second processor ID storage unit 8d, the operating system unit 14 of the processor 5 resets the second processor ID storage unit 8d to "0". "(1008), and the memory pool 7 is returned.

On the other hand, in step 1006 described above,
When the processor ID and the processor ID in the first processor ID storage 8b match, the operating system unit 14 of the processor 5 determines that the second processor ID
The processor ID of the storage unit 8d is stored in the first processor ID storage unit 8b, the second processor ID storage unit 8d is reset to "0", and the memory pool 7 is returned (step 1007).

Therefore, according to the third embodiment, it is possible for another normal processor to access the same memory pool while maintaining the exclusive control state of the faulty processor, and the fault has occurred. When the processor recovers, it can continue the processing before the failure.

[0111]

Fourth Embodiment A multiprocessor system according to the fourth embodiment is composed of N processors 5 and a single shared memory 6.

The configuration of each processor 5 is the same as that of the first embodiment.
And is composed of a task 10, an operating system unit 14, an access counter 11, a timer 12, and a buffer 13. Here, in the fourth embodiment, a function of determining whether or not there is a memory pool under exclusive control by the processor 5 is added to the operating system unit 14 described above. That is, the memory pool that was in the exclusive control state at the time when the processor 5 failed is detected after restarting, and this exclusive control is automatically released.

The operation process of the processor 5 in the fourth embodiment will be described with reference to the flowchart of FIG. The operating system unit 14 sequentially accesses the memory pool 7 in the shared memory 6 from the upper level and refers to the flag bit 8a of each memory pool 7 (step 110).
1).

When an arbitrary memory pool 7 is accessed, the operating system section 14 determines whether the flag bit 8a of the memory pool 7 is "1" (step 1102). Here, the flag bit 8a
Is 0, the next memory pool 7 is accessed, and if the flag bit 8a is 1, the first processor ID storage unit 8b in the memory pool 7 is accessed. Then, the processor ID stored in the first processor ID storage unit 8b is compared with the processor ID of the own processor 5 (step 1103).

If both processor IDs do not match, the next memory pool 7 is accessed. If both processor IDs match, the memory pool 7 concerned is accessed.
Will be returned. That is, the return system call for the memory pool 7 is issued and the exclusive control of the memory pool 7 is released (step 1104).

Next, the operating system section 1
4 resets the flag bit 8a and the processor ID storage 8b in the exclusive control area 8 in the memory pool 7 and sets both to "0" (step 1105).

Each operating system unit 14
Determines whether the memory pool 7 is the lowest memory pool 7 of the shared memory 6 (step 11).
06).

If the memory pool 7 is the lowest,
The return process ends. On the other hand, if there is a memory pool 7 lower than the memory pool 7, the memory pool 7 is accessed, and the processing from step 1102 above is repeated.

As described above, according to the fourth embodiment, the faulty processor automatically searches for the memory pool in the exclusive control state of its own processor after completion of the fault debugging process, and performs the exclusive control on the memory pool. Can be released.

[0120]

According to the present invention, in a multiprocessor system in which a single shared memory is shared by a plurality of processors, if a failure occurs while any processor is accessing the shared memory, another normal processor is activated. Recognizing this, the exclusive control of the faulty processor is automatically released, and the normal processor can continuously execute the processing. This improves the processing capability of the multiprocessor system as a whole.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a schematic configuration block diagram of a multiprocessor system according to the first embodiment.

FIG. 3 is a block diagram of an internal configuration of a memory pool according to the first embodiment.

FIG. 4 is an internal configuration block diagram of a processor according to the first embodiment.

FIG. 5 is a flowchart showing an operation process of exclusive control automatic cancellation in the first embodiment.

FIG. 6 is a block diagram of an internal configuration of a memory pool according to the second embodiment.

FIG. 7 is a flowchart showing an operation process of exclusive control automatic cancellation in the second embodiment.

FIG. 8 is a block diagram of an internal configuration of a memory pool according to the third embodiment.

FIG. 9 is a flowchart showing a processing process when a shared memory access request is made in the third embodiment.

FIG. 10 is a flowchart showing a process of shared memory return processing according to the third embodiment.

FIG. 11 is a flowchart showing the operation process of the processor in the fourth embodiment.

FIG. 12 is a diagram showing a specific example of a conventional multiprocessor system.

[Explanation of symbols]

1-shared memory 2-processor 2a-buffer 2b-access counter 2c-collation means 4-memory pool 4a-status display means 4b-first processor ID storage unit 4c-counter 4d- Second processor ID storage unit 5 Processor 6 Shared memory 7 Memory pool 8 Exclusive control area 8a Flag bit 8b Processor ID storage unit 1c Processor storage unit 8c Counter 8d ··· Second processor ID storage unit 9 · · Data area 9a · · Memory pool (1) 9b · · Memory pool (2) 10 · Task 11 · Access counter 12 · · Timer 13 · · Buffer 14 ·・ Operating system department

Front Page Continuation (72) Inventor Mitsuo Yamazaki 3-9-18 Shin-Yokohama, Kohoku Ward, Yokohama City, Kanagawa Prefecture Fujitsu Communication Systems Limited

Claims (6)

[Claims] 1. A shared memory (1) having a plurality of memory pools (4) and a plurality of processors (2) are provided to exclusively control access from any processor (2) to the memory pool (4). In a multiprocessor system for preventing access from another processor (2), whether or not each memory pool (4) is being accessed by any processor (2) The processor includes a status display unit (4a) and a processor ID storage unit (4b) that stores a processor ID that identifies each processor (2), and each processor (2) includes the processor ID storage unit (4b). ), The buffer (2a) for copying / storing the processor ID registered in), and the number of times the access request is issued to the memory pool (4). An access counter (2b) for counting, and when the processor (2) accesses an arbitrary memory pool (4) of the shared memory (1), a status display means (4a) included in the memory pool (4). And determines whether or not the memory pool (4) is in the access state, and increments the access counter (2b) and stores the processor ID when the memory pool (4) is in the access state. The processor ID registered in the section (4b) is copied into the buffer (2a), and after a lapse of a predetermined time, the status display means (4a) is referred to again,
In the case of the access state, the access counter (2
b) is incremented again, and when the count value of the access counter (2b) reaches a specific value that is arbitrarily set, the processor ID copied in the buffer (2a) and the processor ID storage unit (4b) are registered. When the two coincide with each other, the occurrence of a failure in the processor corresponding to the processor ID is recognized, the status display means (4a) is changed to an empty state, and the first processor ID A shared memory exclusive control method in which the processor ID of the storage unit (4b) is rewritten to its own processor ID. 2. Each memory pool (4) of the shared memory (1) is provided with a counter (4c) that is incremented when access by any processor (2) is permitted, and any processor (2) is provided. Refers to the status display means (4a) when accessing the memory pool (4), and if the memory pool (4) is being accessed by another processor (2), the processor ID storage unit The counter (4c) together with the processor ID of (4b)
Is stored in the buffer (2a), the access is tried a certain number of times, and then the buffer (2
The processor ID and the counter value of a) are compared with the processor ID of the first processor ID storage unit (4b) and the counter value of the counter (4c), and when they match, the processor (2) is 2. The shared memory exclusive control system according to claim 1, wherein the occurrence of a failure in the processor (2) corresponding to the processor ID is recognized. 3. A shared memory (1) having a plurality of memory pools (4) and a plurality of processors (2) for exclusively controlling access from any processor (2) to the memory pool (4). In a multiprocessor system for preventing access from another processor (2), whether or not each memory pool (4) is being accessed by any processor (2) A status display unit (4a) shown, a first processor ID storage section (4b) for storing a processor ID of a processor (2) accessing the memory pool (4), and an access to the memory pool (4). A second processor ID storage section (4d) for storing the processor ID of the processor (2) in which a failure has occurred, and The (2), the first processor I
An arbitrary processor is provided with a buffer (2a) for copying / storing the processor ID registered in the D storage unit (4b) and an access counter (2b) for counting the number of times an access request is issued to the memory pool (4). (2) refers to the status display means (4a) when accessing the memory pool (4), and determines whether the memory pool (4) is in an access status by another processor (2). , If the memory pool (4) is accessible,
If the processor ID of its own processor (2) is stored in the first processor ID storage unit (4b) and the memory pool (4) is being accessed by another processor (2), the first processor ID The processor ID stored in the storage unit (4b) is copied to the buffer (2a), the access counter (2b) is incremented, and the access is repeated a specific number of times, and then the processor ID of the buffer (2a) is stored. Processor I of the first processor ID storage unit (4b)
If the IDs of both are matched, the first processor I
Sharing the processor ID of the D storage unit (4b) in the second processor ID storage unit (4d) and registering its own processor ID in the first processor ID storage unit (4b) Memory exclusive control method. 4. The status display means (4a) comprises the first
When the processor ID is stored in the processor ID storage unit (4b), the access state by the processor (2) corresponding to the processor ID is displayed, and the first processor ID storage unit (4b) and When the processor IDs are stored in both of the two processor ID storage units (4d), the two processors (2) corresponding to the two processor IDs indicate that the dual access state is set. The shared memory exclusive control method according to claim 3. 5. The processor (2) refers to the first processor ID storage unit (4b) and the second processor ID storage unit (4d) at the end of access to the memory pool (4), If the processor ID is stored only in the first processor ID storage section (4b), this processor ID
After confirming the match between the
When D is erased and a processor ID is stored in both the first processor ID storage unit (4b) and the second processor ID storage unit (4d), the self processor ID and the first processor ID The processor IDs of the processor ID storage unit (4b) and the second processor ID storage unit (4d) are compared with each other, and if the processor IDs of the second processor ID storage unit (4d) match, When the processor ID is deleted and the processor ID in the first processor ID storage unit (4b) matches, the processor ID is deleted and the processor ID in the second processor ID storage unit (4d) is changed. The first processor ID storage unit (4
The shared memory exclusive control method according to claim 3, wherein the shared memory exclusive control method is stored in b). 6. A shared memory (1) having a plurality of memory pools (4), and a plurality of processors (2) for exclusively controlling access from any processor (2) to the memory pool (4). In a multiprocessor system for preventing access from another processor (2), whether or not each memory pool (4) is being accessed by any processor (2) And a processor ID storage unit (4b) for storing the processor ID of the processor (2) accessing the memory pool (4). A matching unit (2c) for matching the processor ID registered in the processor ID storage unit (4b) with the own processor ID, Processor (2), when it is raised again up from a failure, the shared each memory pool memory (1) (4)
Access to the status display means (4a) of each memory pool (4) to determine whether or not the access status of the memory pool (4) is displayed. When the status display means (4b) is displaying the access status, the processor ID stored in the processor ID storage section (4b) of the memory pool (4) is compared with its own processor ID, When the processor IDs match, the state display means (4a) of the memory pool (4) is changed to the accessible state and the processor ID storage unit (4)
A shared memory exclusive control method characterized by erasing the own processor ID stored in b).