JPH06149934A - Layout pattern generator - Google Patents

Abstract

(57) [Summary] [Object] To obtain a layout pattern generator capable of inspecting ROM coordinate data and ROM address information before creating ROM layout pattern data. [Arrangement] Means 25 for displaying the layout pattern data on a display screen and reading the coordinates designated by the mouse at any point, and means 26 for calculating the ROM address address corresponding to the designated coordinates and displaying it on the screen. ing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a mask ROM built-in type L
The present invention relates to a layout pattern generator that creates a layout pattern for writing a ROM code in SI.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing the structure of a conventional layout pattern generator. In the figure, 1 is R
A means for reading the coordinate values (ROM coordinate data) of the OM rectangle, and a means for reading the ROM address information.
The coordinate data and the ROM address information are created by the designer himself while viewing the layout pattern diagram and the logic circuit diagram. 3 is a data storage means for storing the read data, 4 is a data control unit for controlling the read data,
Reference numeral 5 is a screen display means for displaying the read data on the display. 6 is ROM code data reading means 7
R corresponding to the ROM code data read by
ROM layout pattern creating means for creating ROM layout pattern data at the OM position, 8 means for outputting a list of truth value data used when creating ROM layout pattern data, and 9 output plot drawing of the created ROM layout pattern data. Is a means to do.

Next, the operation will be described. First, the basic operation of the ROM block in the LSI, which is the background of the conventional technique, will be described with reference to FIG. FIG. 9 shows a model of the logic circuit of the ROM block part in the LSI. Here, it is assumed that 64 ROM rectangles for one bit are arranged. A0
A4 of the address signal line 10 consisting of 8 bits of A7
~ A7 is the X decoder 11, A0 to A3 is the Y decoder 1
2 is output. Based on the input signal, the X decoder 11 selects the select signal line 13 (X
Select one from 0 to X7). Similarly, the Y decoder 12 operates the select signal line 14 (Y0 to Y0) in the Y coordinate direction.
Select one of Y7). The ROM rectangle 15 is laid out at the intersection of the selected select signal line in the X coordinate direction and the select signal line in the Y coordinate direction.

Next, the operation of the conventional layout pattern generator will be described with reference to the flowchart of FIG. First, the ROM coordinate data is read (S1). R
As shown in FIG. 11, the OM coordinate data includes the coordinate value 16 of the lower left apex of the ROM area, the length 17 and the width 1 of the ROM rectangle.
8, the number of ROM rectangles in the X direction is 19, the number of ROM rectangles in the Y direction is 20, there is an arrangement interval 21 of ROM rectangles in the X direction, and an arrangement interval 22 of ROM rectangles in the Y direction. Then, FIG.
The ROM address information shown in is read (S2). This R
The OM address information is a combination of 8 bits of the address signal lines A0 to A7 corresponding to the position of the ROM rectangle (represented by a matrix of transistors starting from the lower left apex of the ROM area), and the designer himself / herself is a logic circuit diagram. Create while watching. Next, the ROM code data shown in FIG. 13 is read (S3). In FIG. 13, 23 is a ROM address address and 24 is ROM code data corresponding to the ROM address address 23. In this example, the number of bits of the ROM code data is 1 bit.

Next, based on the ROM address information, the values of the read ROM code data are rearranged so as to correspond to the positions of the ROM rectangles in the layout pattern (hereinafter, referred to as the following).
The rearranged ROM code data of "0" and "1" is referred to as truth value data) (S4). FIG. 14 shows an example of truth value data. Next, check the values of all truth value data, and if the value is "1", R in the layout pattern corresponding to the data
The coordinates of the OM rectangle are obtained from the ROM address information and the ROM coordinate data, and a ROM rectangle layout pattern (ROM layout pattern data) is created at that position. If the value of the truth value data is "0", ROM layout pattern data is not created (S5). After the ROM layout pattern data is created, the truth value data list (truth value list) and the ROM code data list shown in FIG. 15 are output (S6). Also, a plot of the created ROM layout pattern data is output (S7). FIG.
FIG. 14 shows an example of a plot diagram of the ROM rectangular layout pattern data created from the truth value data shown in FIG. Finally, in order to check whether there is an error in the ROM address information or the ROM coordinate data, the truth value list and the plot diagram of the layout pattern data are visually inspected, and the ROM position of "1" in the truth value list is checked. Check if the ROM rectangle is created at the correct coordinate position (S8), and RO
If there is a problem in the M address position, the ROM address information or the ROM coordinate data is corrected (S9), and the above process is repeated. If there is no problem, the process ends.

[0006]

Since the conventional layout pattern generator is constructed as described above, when checking whether there is an error in the read ROM address information and ROM coordinate data, the input ROM code data is checked. After creating ROM layout pattern data corresponding to, ROM code data list, truth value list and ROM
In addition to it being necessary to visually check the layout pattern data plot diagram, the ROM layout pattern data had to be created again after correcting the error.
Therefore, there are problems that the inspection requires a lot of time, an inspection error occurs, and the like. Further, since it is necessary to convert all the ROM code data into truth value data and temporarily hold the truth value data, a large memory space is required.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a layout pattern generator capable of inspecting ROM address information and ROM coordinate data before creating ROM layout pattern data. . Further, the ROM layout pattern data can be sequentially created for each address of the ROM code data.

[0008]

A layout pattern generating apparatus according to the present invention includes means for displaying layout pattern data on a display, input means for designating an arbitrary point on the display, and the input means. It is provided with means for calculating the ROM address address of the LSI built-in ROM corresponding to the point.

Further, a means for reading an arbitrary address address, a means for calculating the coordinate value of the ROM rectangle of the LSI built-in ROM on the layout pattern data corresponding to the read address address, and a ROM for confirmation at the calculated coordinate position. It is provided with a means for creating a rectangle.

Further, when the ROM layout pattern data is created, a means for calculating the coordinate value of the ROM rectangle corresponding to each address address of the input ROM code data is provided.

[0011]

When an arbitrary point on the display according to the present invention is designated by the input means, the ROM address address is calculated from the coordinate value of the point, the data bit value is output, and the output value and the address address for the designated point. It is possible to inspect the ROM address information by collating with and.

When a certain address is entered,
The ROM address is calculated by calculating the coordinate value corresponding to that address address, creating a ROM rectangle for confirmation in that part, and collating the position with respect to the input address address and the position of the created ROM rectangle for data confirmation. Allows inspection of information.

Further, a coordinate value is calculated for each address address of the input ROM code data, and ROM layout pattern data is sequentially created in that portion.

[0014]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numerals 1 to 7 are the same as or equivalent to those of the conventional one, and the description thereof will be omitted. Reference numeral 25 is a means for reading instructed mouse coordinates when a point on the display is indicated by a mouse, and 26 is means for calculating a ROM address address corresponding to the read mouse coordinates.

Next, the operation will be described with reference to the flowchart of FIG. First, after reading the ROM coordinate data and ROM address information as in the conventional method (T
1 to T2), based on the data, a coordinate value table (address coordinate table) of the transistor matrix for the data bit value of the ROM address is created (T3).
The address coordinate table is composed of a table of the relationship between the address bits selecting the transistor column and the X coordinate value, and a table of the relationship between the address bits selecting the transistor row and the Y coordinate value. FIG. 3 is a table of address bit values (A4 to A7) for selecting a row of address ROM transistors and a table of X coordinate values indicating the lower left apex of the ROM rectangle of each row, and FIG. A3) and a table of Y coordinate values indicating the lower left apex of the ROM rectangle of each row.

Next, the coordinate value of the ROM transistor designated by the mouse is read by the mouse coordinate reading means (T4). Using the read coordinate values as (MX, MY) and the address coordinate table, first, the following equation (1)
After calculating the column number n of the transistor satisfying the above condition, the bit value (A4 to A7) in the X direction of the ROM address is obtained from the column number n (T5). X (n) ≧ MX ≧ X (n) + width of ROM rectangle ... (1) Subsequently, after calculating the row number m of the transistor satisfying the following equation (2), the row address m is used to calculate the ROM address address. Y
The bit value (A0-A3) of the direction is obtained (T6). Y (m) ≧ MY ≧ Y (m) + ROM rectangle length (2) Next, the bit values in the X and Y directions are combined to form A0 to A7.
, And obtain the address address of the ROM rectangle (T
7) This is displayed on the screen (T8). Check if the address displayed on the screen is correct for the ROM transistor designated by the mouse (T9), and if necessary, correct the ROM address information or ROM coordinate data (T10). Repeat the process. If no correction is necessary and the confirmation of another address is continued, the process returns to T4. When all the confirmation is completed, the ROM code data is read (T11), and the ROM layout pattern data is created using the confirmed ROM address information and the ROM coordinate data (T12). As described above, the ROM address information and the ROM coordinate data can be inspected before the ROM layout pattern data is created.

Example 2. In the first embodiment, the ROM
For checking address information and ROM coordinate data,
Although the method of calculating and displaying the address address corresponding to the ROM transistor on the display pointed by the mouse was shown, the ROM coordinate value corresponding to the input ROM address address of the inspection target is calculated and the coordinate is used for confirmation. ROM of
A method of creating a rectangular polygon may be used. FIG. 5 is a block diagram showing a layout pattern generator according to the second embodiment. In the figure, 1 to 7 are the same as or equivalent to a conventional one. Reference numeral 27 is a unit for reading the ROM address of the inspection target, and 28 is a unit for calculating the coordinate value of the ROM rectangle of the read ROM address of the inspection target.

Next, the operation will be described with reference to the flowchart of FIG. First, an address coordinate table is created in the same manner as in Example 1 (T1 to T3). Next, the ROM address to be inspected is read from the keyboard, for example (U1), and the ROM address is divided into X-direction bits and Y-direction bits (U2). Next, the address coordinate table described above is searched based on the bits in the X and Y directions to obtain the X coordinate value and the Y coordinate value of the ROM transistor at the ROM address to be inspected (U3, U4). RO to be inspected by the coordinate value and the width and length of the ROM rectangle input as ROM coordinate data
The coordinate value, width and length of the ROM rectangle at the M address are calculated (U5). Next, R for confirmation is added to the calculated coordinate value.
The OM rectangular polygon is displayed on the screen (U6). The position of the displayed ROM rectangle is confirmed (U7), and if correction is necessary, the ROM address information or the ROM coordinate data is corrected (U8), and the above processing is repeated. U if no correction is necessary and you want to continue checking other address
Return to 1. When all confirmation is completed, the ROM code data is read (U9), and ROM layout pattern data is created using the confirmed ROM address information and ROM coordinate data (U10). By the above processing, the RO before the ROM layout pattern data is created
It is possible to inspect the M address information and the ROM coordinate data.

Example 3. The above-mentioned conventional device, Example 1
In 2 and 2, when the ROM layout pattern data is created, all the ROM code data are rearranged in the order of the ROM address to create the truth value data.
The memory space can be reduced by successively creating the ROM layout pattern data for each ROM address of the M code data. The operation is shown in FIG.
This will be described with reference to the flowchart of FIG. First, an address coordinate table is created in the same manner as in the first embodiment (T
1-T3). Next, read the ROM code data (V
1) As for the first ROM address, the address coordinate table is searched in the same manner as in the second embodiment to obtain the coordinate value of the ROM rectangle (U2 to U5). Here, if the ROM code data of this ROM address is "1" (when V2 is YES), ROM layout pattern data is created (V3), and if it is "0" (when V2 is NO), it is not created. Next, it is judged whether the ROM address is the final address (V4), and if it is not the final address, the address is incremented by 1 and the process returns to U2. If it is the final address, the process ends.
By the above processing, it is not necessary to hold the truth value data, and the memory space of the device is reduced.

[0020]

As described above, according to the present invention, the ROM
Since the ROM address information and the ROM coordinate data can be inspected before the layout pattern data is created, a ROM layout pattern free from inspection errors can be obtained. Further, since the ROM code data can be sequentially converted into ROM layout pattern data for each address, there is an effect that the memory space of the device is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a layout pattern generator according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an operation according to the first embodiment of the present invention.

FIG. 3 is a first example, a second example and a third example of the invention.
It is a figure which shows the address coordinate table of the X direction produced by.

FIG. 4 is a first example, a second example and a third example of the invention.
It is a figure which shows the address coordinate table of the Y direction produced by.

FIG. 5 is a block diagram showing a layout pattern generator according to a second embodiment of the present invention.

FIG. 6 is a flowchart showing an operation according to the second embodiment of the present invention.

FIG. 7 is a flowchart showing an operation according to the third embodiment of the present invention.

FIG. 8 is a block diagram showing a conventional layout pattern generator.

FIG. 9 is a diagram showing a model of a logic circuit of a ROM block which is the background of the conventional technique.

FIG. 10 is a flowchart showing an operation of a conventional layout pattern generation device.

11 is a diagram showing ROM coordinate data read by the ROM rectangle coordinate value reading means in FIG. 8;

12 is a diagram showing ROM address information read by a ROM address information reading means shown in FIG. 8;

FIG. 13 is a diagram showing ROM code data.

FIG. 14 is a diagram showing a list of truth value data conventionally created by the layout pattern generators according to the first and second embodiments of the present invention.

FIG. 15 is a diagram showing truth value data conventionally created by the layout pattern generators according to the first and second embodiments of the present invention.

FIG. 16: RO created by a layout pattern generator
It is a figure which shows M layout pattern data.

[Explanation of symbols]

 1 ROM coordinate data reading means 2 ROM address information reading means 5 Screen display means 6 ROM layout pattern data creating means 7 ROM code data reading means 25 Mouse coordinate reading means 26 ROM address address calculating means 27 ROM address address reading means 28 ROM rectangular Coordinate value calculation means

Claims (3)

[Claims] 1. Position information of a ROM rectangle on layout pattern data corresponding to a ROM address (hereinafter,
The ROM that has been input with the coordinate data in the ROM area on the layout pattern data (hereinafter referred to as ROM coordinate data) as basic data.
In a layout pattern generating device for creating ROM layout pattern data at a ROM position corresponding to code data, a means for displaying the layout pattern data on a display, an input means for designating an arbitrary point on the display, and an instruction by the input means. Means for calculating the ROM address address of the ROM with built-in LSI corresponding to the specified point based on the basic data, and before creating the ROM layout pattern data, the address address for the specified point and the calculated ROM A layout pattern generator capable of inspecting the basic data by collating with an address address. 2. A layout pattern generator for creating ROM layout pattern data at a ROM position corresponding to input ROM code data, using ROM address information and ROM coordinate data as basic data, and means for reading an arbitrary address address. LSI on the layout pattern data corresponding to the address
A means for calculating the coordinate value of the ROM rectangle of the built-in ROM based on the basic data and a means for creating a ROM rectangle for confirmation at the calculated coordinate position are provided, and the reading is performed before the ROM layout pattern data is created. A layout pattern generating device capable of inspecting the basic data by collating the position of the ROM rectangle with respect to the subaddress and the position of the created ROM rectangle for confirmation. 3. A layout pattern generator that creates ROM layout pattern data at a ROM position corresponding to input ROM code data using ROM address information and ROM coordinate data as basic data, when creating the ROM layout pattern data, A layout pattern generating device comprising means for calculating a coordinate value of a ROM rectangle corresponding to each address address of the input ROM code data, and successively creating ROM layout pattern data of the ROM rectangle for each address address.