JPH06151699A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06151699A JPH06151699A JP29622292A JP29622292A JPH06151699A JP H06151699 A JPH06151699 A JP H06151699A JP 29622292 A JP29622292 A JP 29622292A JP 29622292 A JP29622292 A JP 29622292A JP H06151699 A JPH06151699 A JP H06151699A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- substrate
- electrode
- lead
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
(57)【要約】
【目的】3個の半導体チップの一面の電極を共通に接続
し、他面の電極をそれぞれリード端子と接続する半導体
装置のチップからの放熱を良好にし、部品点数を減ら
し、組立てを簡単にする。
【構成】銅基板の一面上に各チップの一方の電極を固着
し、他方の電極にリードフレームのリード部をろう付け
し、基板の他面とリード部の端部を露出させて樹脂でモ
ールドする。基板の他面を冷却体上に密着させて取り付
ければ、良好な放熱が行われる。
(57) [Abstract] [Purpose] Three semiconductor chips are commonly connected to the electrodes on one side, and the electrodes on the other side are connected to lead terminals respectively to improve heat dissipation from the semiconductor device chip and reduce the number of parts. , Easy to assemble. [Structure] One electrode of each chip is fixed on one surface of a copper substrate, the lead portion of the lead frame is brazed to the other electrode, the other surface of the substrate and the end of the lead portion are exposed, and molded with resin. To do. If the other surface of the substrate is attached in close contact with the cooling body, good heat dissipation is performed.
Description
【0001】[0001]
【産業上の利用分野】本発明は、それぞれ両面に電極を
有する3個以上の半導体素体の一方の電極を相互に接続
し、他方の電極に個々に接続した端子導体を外部に引き
出してなる半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a structure in which one electrode of three or more semiconductor elements each having electrodes on both sides is connected to each other and a terminal conductor individually connected to the other electrode is drawn to the outside. The present invention relates to a semiconductor device.
【0002】[0002]
【従来の技術】例えば図3に示すように、一定電圧以上
の電圧がいずれの方向にでも印加された場合にオンから
オフへ移行する双方向特性をもつシリコンサージアブソ
ーバ21を3個接続した半導体装置を組立てる場合、図2
に示すような構造が知られている。すなわち、1本のリ
ード端子31の頭部上にシリコンサージアブソーバチップ
1の一面の電極をろう付けし、そのチップの他面の電極
上に接続板34をろう付けし、その接続板34の上に他のシ
リコンサージアブソーバチップ2、3の一面の電極をろ
う付けする。そのチップ2、3の他面の電極をそれぞれ
リード端子32、33の頭部と接続片35を用いて接続したの
ち、各リード端子31、32、33の端部を露出させて樹脂4
によりモールドする。2. Description of the Related Art For example, as shown in FIG. 3, a semiconductor in which three silicon surge absorbers 21 having a bidirectional characteristic are connected to each other when a voltage higher than a certain voltage is applied in any direction. Figure 2 when assembling the device
The structure shown in is known. That is, an electrode on one surface of the silicon surge absorber chip 1 is brazed on the head of one lead terminal 31, and a connecting plate 34 is brazed on the electrode on the other surface of the chip. Then, the electrodes on one surface of the other silicon surge absorber chips 2 and 3 are brazed. After the electrodes on the other surface of the chips 2 and 3 are connected to the heads of the lead terminals 32 and 33, respectively, using the connecting pieces 35, the end portions of the lead terminals 31, 32 and 33 are exposed to expose the resin 4
To mold.
【0003】[0003]
【発明が解決しようとする課題】しかし、図2に示した
構造には次の欠点がある。 (1) 3個のチップ1、2、3は樹脂4に包囲されてお
り、放熱はリード端子31、32、33を通じて行われるだけ
であるため、冷却されにくく、また冷却も均一でない。However, the structure shown in FIG. 2 has the following drawbacks. (1) Since the three chips 1, 2, 3 are surrounded by the resin 4 and heat is radiated only through the lead terminals 31, 32, 33, it is difficult to cool and the cooling is not uniform.
【0004】(2) 3個のチップ1、2、3が2平面上に
分かれているため、組立が複雑である。 (3) 3本のリード端子31、32、33のほかに接続板34、2
個の接続片35が必要なため、部品点数が多く、コストが
高くなる。 本発明の目的は、上記の欠点を除去し、放熱良好で、組
立てが簡単であり、しかも部品点数の少ない半導体装置
を提供することにある。(2) Since the three chips 1, 2, 3 are separated on two planes, the assembly is complicated. (3) In addition to the three lead terminals 31, 32, 33, the connection plates 34, 2
Since the individual connecting pieces 35 are required, the number of parts is large and the cost is high. An object of the present invention is to eliminate the above-mentioned drawbacks, to provide a semiconductor device which has good heat dissipation, is easy to assemble, and has a small number of parts.
【0005】[0005]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明の半導体装置は、それぞれ両面に電極を有
する3個以上の半導体素体の一方の電極を共通の導電性
基板上に固着し、各半導体素体の他方の電極にそれぞれ
リード端子の一方の端部を結合し、各リード端子の他方
の端部および導電性基板の一面の少なくとも一部を露出
させて各半導体素体を樹脂により被覆してなるものとす
る。そして、導電性基板の一面の露出している部分に取
り付け用の穴が明けられたこと、各半導体素体の一方の
電極が導電性基板の他面上に固着されたこと、さらには
各リード端子が樹脂被覆工程までは一体に連結されてお
り、樹脂被覆工程終了後切り離された帯状導体からなる
ことが有効である。In order to achieve the above object, the semiconductor device of the present invention has one electrode of three or more semiconductor elements each having electrodes on both sides on a common conductive substrate. One end of each lead terminal is fixed to the other electrode of each semiconductor element, and the other end of each lead terminal and at least a part of one surface of the conductive substrate are exposed to expose each semiconductor element. Is coated with a resin. Then, a mounting hole is formed in the exposed portion of the one surface of the conductive substrate, one electrode of each semiconductor element is fixed on the other surface of the conductive substrate, The terminals are integrally connected until the resin coating step, and it is effective that the terminals are made of strip conductors separated after the resin coating step.
【0006】[0006]
【作用】3個以上の半導体素体が共通の導電性基板に固
着されているため、各素体に発生した熱は、その基板を
通じて基板の露出面から、あるいはその露出面に接触さ
せることができる冷却体へ放熱することができ、均一な
冷却が可能になる。そして、各半導体素体を基板の一面
上に固着することにより組立てが簡単になり、基板と各
リード端子の露出部を用いて各素体の特性測定も容易で
ある。また接続片が不要なため部品点数も少なくてす
む。Since at least three semiconductor elements are fixed to a common conductive substrate, the heat generated in each element can be brought into contact with the exposed surface of the substrate through the substrate or to the exposed surface. The heat can be radiated to the cooling body, which enables uniform cooling. Then, by assembling each semiconductor element on one surface of the substrate, the assembly is simplified, and the characteristics of each element can be easily measured by using the exposed portions of the substrate and the lead terminals. Also, since no connecting piece is required, the number of parts can be reduced.
【0007】[0007]
【実施例】以下図を引用して本発明の実施例について述
べる。図1は本発明の一実施例を示し、図4、図5が用
いた部品である。すなわち、図4に示した銅基板5の上
に図1に示すようにシリコンサージアブソーバチップ
1、2、3の下面電極をはんだを用いて固着し、各チッ
プの上面電極に図5に示したリードフレーム10の帯状リ
ード部11、12、13の頭部をはんだ付けする。そして、樹
脂4をモールドして各チップ1、2、3を被覆する。こ
の際、チップが基板5の表面上に存在するため、基板の
裏面51は全面露出させることができる。このあと、リー
ドフレーム10の樹脂4の外に出ている連結部14を切離
し、図1の状態にする。リード部11、12、13は平板なの
で、自在に折り曲げて外部との接続を行うことができ
る。この状態で、リード部11、12、13の一つと基板露出
面51を用いて各チップの特性をチェックすることができ
る。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention, which is a component used in FIGS. That is, the bottom electrodes of the silicon surge absorber chips 1, 2 and 3 are fixed on the copper substrate 5 shown in FIG. 4 with solder as shown in FIG. 1, and the top electrodes of the chips are shown in FIG. The heads of the strip-shaped lead portions 11, 12, 13 of the lead frame 10 are soldered. Then, the resin 4 is molded to cover the chips 1, 2, and 3. At this time, since the chip exists on the front surface of the substrate 5, the back surface 51 of the substrate can be entirely exposed. After that, the connecting portion 14 of the lead frame 10 which is exposed to the outside of the resin 4 is cut off to obtain the state shown in FIG. Since the lead parts 11, 12, and 13 are flat plates, they can be freely bent and connected to the outside. In this state, the characteristics of each chip can be checked by using one of the lead portions 11, 12, 13 and the exposed substrate surface 51.
【0008】図6は別の実施例を基板裏面側から見た図
で、この場合は基板5の裏面だけを露出させ、表面側は
全面樹脂4によって被覆しており、チップに対する保護
を強化してある。図7はこの半導体装置を冷却体6の上
に取付けた状態を示し、基板5および樹脂4に明けられ
た貫通孔7を利用し、取り付けねじ8で固定している。
図1に示した実施例でも、同様に基板5に明けられた貫
通孔7を利用して基板5の裏面を冷却体に密着させれ
ば、チップ1、2、3から基板5の裏面51までの熱抵抗
は、図2の従来の半導体装置のチップから樹脂4の表面
までの熱抵抗の1/10であるため、極めて良好な放熱が
できる。以上、チップ3個の実施例について述べたが、
4個以上の場合も同様に実施できることはいうまでもな
い。FIG. 6 is a view of another embodiment viewed from the back surface side of the substrate. In this case, only the back surface of the substrate 5 is exposed and the front surface side is entirely covered with the resin 4 to enhance protection for the chip. There is. FIG. 7 shows a state in which this semiconductor device is mounted on the cooling body 6, and the through holes 7 formed in the substrate 5 and the resin 4 are used to fix the semiconductor device with mounting screws 8.
In the embodiment shown in FIG. 1 as well, if the back surface of the substrate 5 is brought into close contact with the cooling body using the through holes 7 formed in the board 5 as well, from the chips 1, 2, 3 to the back surface 51 of the substrate 5. Since the thermal resistance of 1 is 1/10 of the thermal resistance from the chip of the conventional semiconductor device of FIG. 2 to the surface of the resin 4, very good heat dissipation can be performed. As mentioned above, the embodiments with three chips have been described.
It goes without saying that the same operation can be performed in the case of four or more.
【0009】[0009]
【発明の効果】本発明によれば、複数個の半導体素体の
一方の電極の相互の接続を導電性基板で行い、その基板
の一面を露出させることにより、冷却体への熱伝導を向
上させることができ、信頼性の高い半導体装置を得た。
また他方の電極をリードフレームのリード部と接続する
ことにより、チップ以外の部品点数も従来の6個から2
個に減少し、コストダウンでき、組立も簡単になって組
立工数が低減された。According to the present invention, one electrode of a plurality of semiconductor elements is connected to each other by a conductive substrate, and one surface of the substrate is exposed to improve heat conduction to a cooling body. Thus, a highly reliable semiconductor device can be obtained.
Also, by connecting the other electrode to the lead part of the lead frame, the number of parts other than the chip can be reduced from the conventional 6 to 2
The number of parts has been reduced, the cost has been reduced, the assembly has been simplified, and the number of assembly steps has been reduced.
【図1】本発明の一実施例のシリコンサージアブソーバ
半導体装置の透視斜視図FIG. 1 is a perspective view of a silicon surge absorber semiconductor device according to an embodiment of the present invention.
【図2】従来のシリコンサージアブソーバ半導体装置の
透視斜視図FIG. 2 is a perspective view of a conventional silicon surge absorber semiconductor device.
【図3】図1、図2の半導体装置の等価回路図FIG. 3 is an equivalent circuit diagram of the semiconductor device shown in FIGS. 1 and 2.
【図4】図1の半導体装置に用いる部品の基板の斜視図4 is a perspective view of a substrate of a component used in the semiconductor device of FIG.
【図5】図1の半導体装置に用いる部品のリードフレー
ムの斜視図5 is a perspective view of a lead frame of a component used in the semiconductor device of FIG.
【図6】本発明の別の実施例のシリコンサージアブソー
バ半導体装置の斜視図FIG. 6 is a perspective view of a silicon surge absorber semiconductor device according to another embodiment of the present invention.
【図7】図6の半導体装置の冷却体への取付状態を示す
断面図7 is a cross-sectional view showing how the semiconductor device of FIG. 6 is attached to a cooling body.
1 シリコンサージアブソーバチップ 2 シリコンサージアブソーバチップ 3 シリコンサージアブソーバチップ 4 樹脂 5 銅基板 6 冷却体 7 貫通孔 10 リードフレーム 11 リード部 12 リード部 13 リード部 1 Silicon Surge Absorber Chip 2 Silicon Surge Absorber Chip 3 Silicon Surge Absorber Chip 4 Resin 5 Copper Substrate 6 Cooling Body 7 Through Hole 10 Lead Frame 11 Lead Part 12 Lead Part 13 Lead Part
Claims (4)
導体素体の一方の電極を共通の導電性基板上に固着し、
各半導体素体の他方の電極にそれぞれリード端子の一方
の端部を結合し、各リード端子の他方の端部および導電
性基板の一面の少なくとも一部を露出させて各半導体素
体を樹脂により被覆してなることを特徴とする半導体装
置。1. One of electrodes of three or more semiconductor elements each having electrodes on both sides is fixed on a common conductive substrate,
One end of each lead terminal is coupled to the other electrode of each semiconductor element, and the other end of each lead terminal and at least a part of one surface of the conductive substrate are exposed, and each semiconductor element is made of resin. A semiconductor device characterized by being covered.
り付け用の穴が明けられた請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein a mounting hole is formed in an exposed portion of one surface of the conductive substrate.
他面上に固着された請求項1あるいは2記載の半導体装
置。3. The semiconductor device according to claim 1, wherein one electrode of each semiconductor element is fixed on the other surface of the conductive substrate.
連結されており、樹脂被覆工程終了後切り離された帯状
導体からなる請求項1、2あるいは3記載の半導体装
置。4. The semiconductor device according to claim 1, 2 or 3, wherein each lead terminal is integrally connected until the resin coating step and is made of a strip-shaped conductor which is cut off after the resin coating step is completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29622292A JPH06151699A (en) | 1992-11-06 | 1992-11-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29622292A JPH06151699A (en) | 1992-11-06 | 1992-11-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06151699A true JPH06151699A (en) | 1994-05-31 |
Family
ID=17830763
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29622292A Pending JPH06151699A (en) | 1992-11-06 | 1992-11-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06151699A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6307272B1 (en) * | 1998-05-27 | 2001-10-23 | Hitachi, Ltd. | Semiconductor device and method for manufacturing the same |
| WO2008111524A1 (en) | 2007-03-09 | 2008-09-18 | Omron Corporation | Package manufacturing method, package, optical module and die for integral molding |
-
1992
- 1992-11-06 JP JP29622292A patent/JPH06151699A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6307272B1 (en) * | 1998-05-27 | 2001-10-23 | Hitachi, Ltd. | Semiconductor device and method for manufacturing the same |
| US6479327B2 (en) | 1998-05-27 | 2002-11-12 | Hitachi, Ltd. | Semiconductor device and method for manufacturing the same |
| WO2008111524A1 (en) | 2007-03-09 | 2008-09-18 | Omron Corporation | Package manufacturing method, package, optical module and die for integral molding |
| US8218917B2 (en) | 2007-03-09 | 2012-07-10 | Omron Corporation | Package manufacturing method, package, optical module and die for integral molding |
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