JPH06151702A - Multichip module - Google Patents

Abstract

(57) [Abstract] [Purpose] In a multi-chip module in which a semiconductor chip is mounted on a substrate, the size of the substrate is reduced and the wiring length on the substrate is shortened, thereby increasing the speed of the microprocessor. [Structure] An insulating layer 6 is provided so as to cover the semiconductor chips 2 and 3 mounted on a substrate 1, and a second-layer semiconductor chip 4 is mounted on the insulating layer 6. At this time, a via hole 7 is opened in the insulating layer 6 so that the semiconductor chip 4 of the second layer can make contact with the wiring layer 5 on the substrate 1 and is electrically connected to the metal wiring 8 on the insulating layer 6. Furthermore, the insulating layer 6,
The via hole 7 and the metal wiring 8 are sequentially formed, and the semiconductor chips are vertically stacked in a plurality of layers to form a multi-chip module.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module in which a plurality of semiconductor chips such as microprocessors and memories are mounted on the same substrate, and more particularly to a multi-chip module in which semiconductor chips are vertically stacked.

[0002]

2. Description of the Related Art In recent years, multi-chip modules have been used as a method for high-density mounting with the increase in speed of microprocessors and downsizing of devices. A conventional multi-chip module generally uses a ceramic substrate such as alumina as a substrate, and also uses a silicon substrate. An example of a conventional multi-chip module is shown in the perspective view of FIG. In the example of FIG. 3, a plurality of thin film wirings are formed on a substrate 1 made of ceramic or the like by using a metal such as copper as the wiring layer 5 and a resin such as polyimide as an insulating layer between the wiring layers 5, and the substrate 1 A plurality of semiconductor chips 2 and 3 are mounted on the upper surface by a flip-chip method, and the substrate 1 is LS-mounted.
It is mounted on the ceramic package 11 for I.

This multi-chip module is a method of mounting individual semiconductor chips without enclosing them in a package, as compared with the case where individual LSI packages are mounted on a printed wiring board. Wider and allows high-density mounting. Also, because there are no package leads, the wiring length between semiconductor chips can be shortened,
Since the delay time due to the wiring can be shortened, it has the advantage that the microprocessor can be speeded up and is widely used.

[0004]

In the above-described conventional multi-chip module, the semiconductor chips are mounted along the plane of the substrate, so that the number of semiconductor chips mounted on the substrate increases in proportion to the number of semiconductor chips mounted on the substrate. There is a problem that the area increases. In addition, as the number of semiconductor chips mounted on the board increases, the area of the wiring layer for connecting the semiconductor chips also increases in proportion to the increase in the board area and the increase in the wiring length. There is a problem in that the propagation delay time of the signal is increased.

[0005]

A multi-chip module of the present invention includes a first-layer semiconductor chip mounted on a substrate, an insulating layer formed in a region covering a part or all of the semiconductor chip, and a substrate on the substrate. A via hole for making contact with a wiring is formed in an insulating layer, a metal wiring layer formed on the insulating layer that conducts through the via hole, and a second-layer semiconductor chip mounted on the metal wiring layer. The semiconductor chip has a structure in which a plurality of layers of semiconductor chips are vertically stacked on the substrate by sequentially laminating the insulating layer, the via hole, and the metal wiring layer.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of an embodiment of the present invention. The structure of the multi-chip module of this embodiment will be described below with reference to the drawings.

As shown in FIG. 1, semiconductor chips 2 and 3 are mounted on a substrate 1 made of ceramic or the like. A surface of the substrate 1 on which the semiconductor chips 2 and 3 are mounted and a part of the wiring layer 5 are formed on the upper surface of the substrate 1, and a wiring layer 5 (including a power supply layer and a ground layer) is formed inside the substrate. ,
Further, lead terminals extending from the wiring layer 5 and connected to the package are led out to the lower surface side of the substrate. The semiconductor chips 2 and 3 are fixed to the semiconductor chip mounting surface on the substrate 1 with an adhesive, and then the semiconductor chips 2 and 3 are connected to the wiring layer 5 formed on the substrate 1 by wire bonding.

Next, in order to vertically stack the semiconductor chips,
An insulating layer 6 is formed of a resin such as polyimide so as to cover the semiconductor chips 2 and 3 mounted on the substrate 1,
The semiconductor chip 4 of the second layer is mounted on it. At this time, a via hole 7 is formed in the insulating layer 6 by a normal exposure technique so that the semiconductor chip 4 can make contact with the wiring layer 5 on the substrate 1, and a conductor such as aluminum is formed in the via hole 7 to form the via hole on the insulating layer 6. The contact is made with the formed metal wiring 8.
The insulating layer 6 may be formed not in the entire region of the substrate but only in the region where the second-layer semiconductor chip 4 is overlaid. By repeating this vertical stacking technique, the semiconductor chips of the third and subsequent layers can be stacked.

FIG. 2 is a diagram for explaining the effect of one embodiment of the present invention. That is, FIG. 2A is a top view when the semiconductor chips are arranged in a plane, and FIG. 2B is a top view when the semiconductor chips are stacked in three layers. FIG. 2 shows an example of a multi-chip module composed of one CPU 9 and three cache memories 10 as a semiconductor chip.

In FIG. 1A, since all the semiconductor chips are mounted in a plane, the size of the ceramic package 11 is 40 mm × 40 mm, and the area of the module is 1.
It will be 600 mm ² , and from the wiring dimensions shown in the figure, the CPU
The length of the wire connecting 9 and the cache memory 10 is 38 mm in the case of the longest wire. On the other hand, in FIG. 3B, three cache memories are mounted vertically, so if the dimensions of the ceramic package 11 are 40 mm × 20 mm, the area of the module is 800 mm ^2, which is 1/2 of that of FIG.
Therefore, the length of the wiring connecting the CPU 9 and the cache memory 10 is about 8 to 10 mm (8 mm + the thickness of the insulating layer 1 mm × the number of insulating layers 0 to 2), which is about 1/4 of the figure (A).

Although the semiconductor chip is mounted on the substrate by wire bonding in this embodiment, the flip chip is mounted on the substrate by connecting the electrode terminals formed on the wiring layer on the substrate to the bumps of the flip chip. Face down bonding can also be performed. Also in this case, flip chip vertical stacking can be realized by the same stacking technique as in the present embodiment.

[0012]

As described above, according to the present invention, the semiconductor chips are vertically stacked and mounted on the substrate. Therefore, the area of the module is smaller than that of the conventional multi-chip module in which the semiconductor chips are mounted flat. The size can be greatly reduced and can be reduced to a fraction of the total area of the mounted semiconductor chips. Further, as the module area is reduced, the wiring length between the semiconductor chips can be shortened, and the signal propagation delay time on the wiring can be shortened, so that the microprocessor can be speeded up.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention.

2A and 2B are views for explaining the effect of one embodiment of the present invention. FIG. 2A is a top view when semiconductor chips are mounted on a plane, and FIG. 2B is a top view when they are stacked. is there.

FIG. 3 is a perspective view of a conventional multi-chip module.

[Explanation of symbols]

 1 Substrate 2, 3, 4 Semiconductor Chip 5 Wiring Layer 6 Insulating Layer 7 Via Hole 8 Metal Wiring 9 CPU 10 Cache Memory 11 Ceramic Package

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display area H01L 25/04

Claims (2)

[Claims] 1. In a multi-chip module in which a plurality of semiconductor chips are mounted on a substrate on which wiring is provided and the substrate is mounted in a package, the first-layer semiconductor chip mounted on the substrate and the semiconductor chip A metal wiring formed on an insulating layer formed in a region covering a part or the whole and a via hole for making contact with a wiring on a substrate, and formed on the insulating layer, and conducting on the insulating layer A multi-chip module having a layer and a second-layer semiconductor chip mounted on the metal wiring layer. 2. A multi-chip module characterized in that the same insulating layer, via holes, and metal wiring layers as those for mounting the second-layer semiconductor chip are repeatedly formed, and the semiconductor chips are vertically stacked in a plurality of layers.