JPH06152609A - Information transmission system - Google Patents

Information transmission system

Info

Publication number
JPH06152609A
JPH06152609A JP4312563A JP31256392A JPH06152609A JP H06152609 A JPH06152609 A JP H06152609A JP 4312563 A JP4312563 A JP 4312563A JP 31256392 A JP31256392 A JP 31256392A JP H06152609 A JPH06152609 A JP H06152609A
Authority
JP
Japan
Prior art keywords
transmitter
signal line
pulse
microcomputer
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4312563A
Other languages
Japanese (ja)
Inventor
Yukio Koyanagi
裕喜生 小柳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NSC Co Ltd
Original Assignee
Nigata Semitsu Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nigata Semitsu Co Ltd filed Critical Nigata Semitsu Co Ltd
Priority to JP4312563A priority Critical patent/JPH06152609A/en
Publication of JPH06152609A publication Critical patent/JPH06152609A/en
Pending legal-status Critical Current

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  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To prevent runaway of a transmission microcomputer by connecting lots of transmitters in parallel with a signal line to both ends for which a receiver and a termination resistor are connected and sending a signal inputted to the transmitter to the receiver through the signal line so as to reduce power consumption. CONSTITUTION:A reset pulse whose pulse width or level differs from that of each of count pulses more than the maximum value of an address of a transmitter is inserted to each count pulse as a composite pulse train in which the period of the count pulse is set longer than the program execution time of a transmission microcomputer superimposed on a power supply voltage fed from a receiver 1 to a transmitter 4. When the transmitter 4 detects the reset pulse, the transmitter microcomputer is reset and the transmitter address is set, then the standby mode is set, the transmitter 4 whose address reaches '0' by decrementing '1' from the address set by a succeeding count pulse transmits input information to the signal line, the transmitter is set to the standby mode, thus the transmitter 4 whose address is smaller sends sequentially input information to the signal line. Thus, the power consumption is reduced and the runaway of the transmitter microcomputer is prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、多数の送信機を2本の
信号線に並列に接続しその一端を受信機に接続し、他端
を終端抵抗で終端し、送信機に入力した接点信号(オ
ン、オフ)、アナログ信号、デジタル信号を信号線によ
って受信機に伝送する情報伝送方式である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact connected to a plurality of transmitters in parallel with two signal lines, one end of which is connected to a receiver and the other end of which is terminated by a terminating resistor, and which is input to the transmitter. This is an information transmission system in which signals (on / off), analog signals, and digital signals are transmitted to a receiver through signal lines.

【0002】[0002]

【従来の技術】従来は、送信機に受信機能を持たせ、夫
々異なったアドレスを持つ送信機に受信機よりアドレス
信号を送り、送られたアドレス信号と一致したアドレス
を持つ送信機が入力情報を信号線に送出する、所謂ポー
リング方式であった。
2. Description of the Related Art Conventionally, a transmitter has a receiving function, an address signal is sent from a receiver to a transmitter having a different address, and a transmitter having an address matching the sent address signal is input information. Is a so-called polling method in which the signal is sent to the signal line.

【0003】[0003]

【発明が解決しようとする課題】ポーリング方式の場
合、個々の送信機に受信機能を、受信機に送信機能を持
たせる必要があり、この為構造が複雑になり、常時アド
レスの一致を監視するので消費電流も大きくなった。ま
た個々の送信機のアドレスを受信機より順次信号線に送
出し、送信機はこれを受信して自己のアドレスとの一致
を確認後自己の入力情報を信号線上に送出するので、信
号線の使用効率が悪い欠点があった。
In the polling method, it is necessary for each transmitter to have a reception function and the receiver to have a transmission function, which complicates the structure and constantly monitors for address coincidence. Therefore, the current consumption has also increased. In addition, the address of each transmitter is sent from the receiver to the signal line in sequence, and the transmitter receives this and after confirming that it matches its own address, it sends its own input information on the signal line. There was a drawback that the usage efficiency was poor.

【0004】[0004]

【課題を解決するための手段】上記課題を解決するため
に、本発明においては、受信機端子より2本の信号線を
延ばし、その終端に終端抵抗を接続し、受信機端子と終
端抵抗との間に、0以外の多数の異なったアドレスを持
つ送信機を並列接続し、送信機への入力情報を受信機に
伝送しうる構成とし、受信機より送信機に供給する電源
電圧に、送信機アドレスの最大値より多い一定数のカウ
ントパルス毎にカウントパルスをカウントパルスととパ
ルス幅又は振幅の異なるりセットパルスと置換え、且つ
カウントパルスの周期を送信用マイコンのプログラム実
行時間の最大値より長くした、複合パルス列を重畳し、
送信機にてりセットパルスを検出して、送信用マイコン
をりセットした後、送信機アドレス値をセット後待機モ
ードとし、続くカウントパルス毎にセットされた送信機
アドレス値より1を減算し、その値が0以外の送信機は
待機モードに、0の送信機は入力情報を信号線に送出後
待機モードとなるようにし、これを繰り返し、すべての
送信機の入力情報を、繰り返し順次受信機に伝送する如
くした。また送信用マイコンの電源を信号線より定電流
回路又は抵抗を介して大容量コンデンサに蓄積された電
力で賄い、信号線よりのりセット信号により送信用マイ
コンを一定周期で強制的にリセット、プログラム実行待
機モードとし、送信用マイコンの暴走を防止すると共
に、供給電流を時間的に平均化し小さくした。
In order to solve the above problems, according to the present invention, two signal lines are extended from a receiver terminal, and a terminating resistor is connected to the end of the signal line. Between the transmitters, a number of transmitters with different addresses other than 0 are connected in parallel so that the input information to the transmitter can be transmitted to the receiver. Replace the count pulse with a count pulse and a reset pulse with a different pulse width or amplitude for each fixed number of count pulses greater than the maximum value of the machine address, and set the cycle of the count pulse to the maximum value of the program execution time of the transmitting microcomputer. Superimpose a long, complex pulse train,
After detecting the reset pulse by the transmitter and resetting the transmitting microcomputer, set the transmitter address value to the standby mode, subtract 1 from the transmitter address value set for each subsequent count pulse, Transmitters with a value other than 0 are in standby mode, transmitters with 0 are in standby mode after sending input information to the signal line, and this is repeated to repeatedly input the input information of all transmitters in sequence. It was transmitted to. In addition, the power supply of the transmission microcomputer is supplied from the signal line with the electric power stored in the large-capacity capacitor via the constant current circuit or the resistor, and the transmission microcomputer is forcibly reset at a fixed cycle by the glue set signal from the signal line, and the program is executed. The standby mode was set to prevent runaway of the transmitting microcomputer and average the supply current over time to reduce it.

【0005】[0005]

【実施例】実施例について図面を参照して説明する。図
1は本発明の基本構成を示すブロック図である。1は受
信機、2、3は信号線、4、4’等は送信機、5は終端
抵抗である。送信機4、4’等はすべて0を除く互いに
異なったアドレスを持ち、且つ単独または複数の情報入
力端子を有する。図2は本発明の送信機の実施例の構成
図である。6、7は信号線との接続端子8、9は送信用
トランジスタ、10は電源直列抵抗、11は電源保持用
大容量コンデンサであり、三端子レギュレータ12、を
介して送信用マイコン14のプラス電源13となる。送
信用トランジスタ8、9は情報送信時は、送信用マイコ
ンの出力22がHIGHとなりトランジスタ17、1
7’がオンとなりA級動作となる。その他の時は抵抗1
0と直列の、大容量コンデンサ11の充電回路を構成す
る。信号線には、後述の如く電源電圧に振幅またはパル
ス幅の異なるリセットパルスの間に多数のカウントパル
スがある複合パルスが重畳されている。信号線端子6よ
り重畳パルス中のリセッとパルス分離整形回酪15によ
りリセットパルスとカウントパルスを分離、整形しし、
送信用マイコンのリセット端子18にリセット信号を出
力し、カウント端子16にカウントパルスを出力する。
開放時LOWの送信用マイコンのアドレス端子19に
は、アドレススイッチ21が接続され、その共通接点側
は送信用マイコンの出力端子20に接続されている。送
信用マイコンはリセット後出力端子20をHIGHに
し、入力端子19より自己のアドレスを読み込む。この
ような構成にすれば、定常時の電力消費を削減しうる。
送信用マイコンは、リセットパルスに続くカウントパル
スにより、読み込んだ自己アドレスを順次1づつ減算し
て行く。その結果が0以外の時は送信用マイコンは次の
カウントパルスが来るまで待機モードで信号線に対して
ハイインピーダンスとなり、減算結果が0の送信用マイ
コンは入力情報を信号線に出力する。出力モードとなる
と、まず送信用マイコンは情報入力端子23の入力値を
読み込む。次いで切替え出力端子22をHIGHにし、
切替え出力トランジスタ8、9をA級動作とする。読み
込まれた入力値はA/D変換され、出力24、25およ
びローパスフィルター26、26’によりトーン信号の
組み合わせとなり、レベルシフト用ダイオード27、コ
ンデンサ28を介して出力トランジスタを駆動し信号線
に情報を送出する。図3は本発明の受信機の実施例の構
成図である。29、30は信号線の接続端子であり、入
力したトーン信号は入力絶縁トランス31より入力アン
プ32を通り信号処理マイコン33の情報入力端子34
に入力する。信号処理用マイコン33の処理プログラム
は、入力値の上下に閾値を設け、上下の閾値の外の値は
すべて接点信号として処理し、上下の閾値の間の値をア
ナログ値として判定する如くすることにより、送信機
は、同一構成で接点入力とアナログ入力の双方に対応す
ることが可能となった。信号処理用マイコンはパルス出
力端子36より、信号線駆動トランジスタ37、38、
39により信号線を駆動する。抵抗40、41、42は
信号線に対する負荷抵抗となる。送信機に対する電源の
供給は電池45よりトランジスタ38、抵抗40、4
1、42を介して行われる。従って抵抗41と42の接
続点の電圧をコンパレーター35で監視すれば、信号線
の断線が検出できる。入力した情報はアナログ値はセン
サ特性に応じた補正及び変換を行い、外部インターフェ
イスドライバー43を介して外部インターフェイス端子
44に出力する。 外部インターフェイスにパソコンを
接続し用途に応じた処理を行わせる事が出来る。図4は
本発明の信号線の電圧波形の一例をを示した波形、タイ
ミング図で、46は受信機より送られる電圧波形であ
り、スイッチオン時に立ち上がり、これが一定電圧以上
になるとリセットパルス47、47’カウントパルス4
8、48’を電源電圧に重畳して出力する。リセットパ
ルスは図の如くカウントパルスとパルス幅を変えるか、
または振幅を変えて区分できるようにする。各パルスの
間隔はその間の送信機プログラム実行時間の最大値より
大きく取る。リセットパルス間のカウントパルスの数は
接続する送信機アドレスの最大値以上とする。49、5
1、53、55はアドレス順に各送信機よりのトーン信
号50、50’、52、52’、54、54’55の送
出タイミングを示す。各信号は重複せず送出される。
EXAMPLES Examples will be described with reference to the drawings. FIG. 1 is a block diagram showing the basic configuration of the present invention. 1 is a receiver, 2 and 3 are signal lines, 4 and 4'are transmitters, and 5 is a terminating resistor. The transmitters 4, 4 ', etc. all have different addresses except 0 and have a single or a plurality of information input terminals. FIG. 2 is a block diagram of an embodiment of the transmitter of the present invention. Reference numerals 6 and 7 denote connection terminals for signal lines, 8 and 9 are transmission transistors, 10 is a power supply series resistor, 11 is a power supply large-capacity capacitor, and a positive power supply for the transmission microcomputer 14 via a three-terminal regulator 12. It becomes 13. When transmitting information, the transmission transistors 8 and 9 have the output 22 of the transmission microcomputer set to HIGH, so that the transistors 17 and 1
7'is turned on and class A operation is performed. At other times, resistance 1
A charging circuit for the large-capacity capacitor 11 in series with 0 is configured. As will be described later, a composite pulse having a number of count pulses between reset pulses having different amplitudes or pulse widths is superimposed on the signal line. From the signal line terminal 6, the reset pulse and the count pulse are separated and shaped by the reset and pulse separation shaping 15 in the superimposed pulse,
A reset signal is output to the reset terminal 18 of the transmission microcomputer, and a count pulse is output to the count terminal 16.
An address switch 21 is connected to the address terminal 19 of the transmitting microcomputer which is LOW when opened, and the common contact side thereof is connected to the output terminal 20 of the transmitting microcomputer. After resetting, the transmission microcomputer sets the output terminal 20 to HIGH and reads its own address from the input terminal 19. With such a configuration, it is possible to reduce power consumption in a steady state.
The transmitting microcomputer sequentially subtracts the read self address by one by the count pulse following the reset pulse. When the result is other than 0, the transmitting microcomputer has a high impedance with respect to the signal line in the standby mode until the next count pulse arrives, and the transmitting microcomputer having the subtraction result of 0 outputs the input information to the signal line. In the output mode, the transmitting microcomputer first reads the input value of the information input terminal 23. Next, the switching output terminal 22 is set to HIGH,
The switching output transistors 8 and 9 are operated in class A. The read input value is A / D converted and becomes a combination of tone signals by the outputs 24 and 25 and the low-pass filters 26 and 26 ′, and drives the output transistor through the level shift diode 27 and the capacitor 28 to send information to the signal line. Is sent. FIG. 3 is a block diagram of an embodiment of the receiver of the present invention. Reference numerals 29 and 30 are connection terminals of signal lines, and the input tone signal passes from the input isolation transformer 31 to the input amplifier 32 and the information input terminal 34 of the signal processing microcomputer 33.
To enter. The processing program of the signal processing microcomputer 33 sets thresholds above and below the input value, processes all values outside the upper and lower thresholds as contact signals, and determines values between the upper and lower thresholds as analog values. As a result, the transmitter can support both contact input and analog input with the same configuration. The signal processing microcomputer uses the pulse output terminal 36 to connect the signal line drive transistors 37, 38,
The signal line is driven by 39. The resistors 40, 41, 42 serve as load resistors for the signal lines. The power supply to the transmitter is from the battery 45 to the transistor 38, resistors 40, 4
1 and 42. Therefore, if the voltage at the connection point between the resistors 41 and 42 is monitored by the comparator 35, the disconnection of the signal line can be detected. An analog value of the input information is corrected and converted according to the sensor characteristic, and is output to the external interface terminal 44 via the external interface driver 43. It is possible to connect a personal computer to the external interface and perform processing according to the application. FIG. 4 is a waveform and timing chart showing an example of the voltage waveform of the signal line of the present invention, and 46 is a voltage waveform sent from the receiver, which rises when the switch is turned on, and when this becomes a certain voltage or more, a reset pulse 47, 47 'count pulse 4
8, 48 'are superimposed on the power supply voltage and output. The reset pulse changes the count pulse and pulse width as shown in the figure, or
Or change the amplitude so that it can be divided. The interval between each pulse is set to be larger than the maximum value of the transmitter program execution time between them. The number of count pulses between reset pulses should be greater than the maximum value of the connected transmitter address. 49, 5
Reference numerals 1, 53, 55 denote the timings of sending tone signals 50, 50 ', 52, 52', 54, 54'55 from the respective transmitters in the order of addresses. Each signal is transmitted without duplication.

【0006】[0006]

【発明の効果】以上説明したように、本発明は情報伝送
および送信機電源供給が2本の信号線のみで可能であ
り、送信機はアナログ電圧入力と接点入力双方に対応で
き、かつ消費電流を極めて少なくすると共に送信機のマ
イコンの暴走を防止しうるものである。また、1つの送
信機よりの情報伝送に必要な時間が通常のポーリング方
式に比べ短縮することが出来る。
As described above, according to the present invention, the information transmission and the power supply of the transmitter can be performed by only two signal lines, the transmitter can support both the analog voltage input and the contact input, and the current consumption can be reduced. It is possible to prevent the runaway of the microcomputer of the transmitter while minimizing the number of times. Further, the time required for information transmission from one transmitter can be shortened as compared with the normal polling method.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の基本構成を示すブロック図FIG. 1 is a block diagram showing the basic configuration of the present invention.

【図2】本発明の送信機の実施例の構成図FIG. 2 is a configuration diagram of an embodiment of a transmitter of the present invention.

【図3】本発明の受信機の実施例の構成図FIG. 3 is a block diagram of an embodiment of a receiver of the present invention.

【図4】本発明の信号線の電圧波形の一例を示す波形、
タイミング図
FIG. 4 is a waveform showing an example of a voltage waveform of a signal line of the present invention,
Timing diagram

【符号の説明】[Explanation of symbols]

1 受信機 2、3 信号線 4、4’ 送信機 5 終端抵抗 6、7 信号線との接続端子 8、9 送信用トランジスタ 10 電源直列抵抗 11 電源保持用大容量コンデンサ 12 三端子レギュレータ 13 電源 14 送信用マイコン 15 リセットパルス分離整形回路 16 送信用マイコンのカウント端子 17、17’送信切替えトランジスタ 18 送信用マイコンのリセット端子 19 送信用マイコンのアドレス端子 20 送信用マイコンの出力端子 21 アドレススイッチ 22 送信用マイコンの切替え出力端子 23 情報入力端子 24、25 送信用マイコンの情報出力端子 26、26’トーン信号生成用ローパスフィルター 27 ドライブ信号レベルシフトダイオード 28 ドライブコンデンサ 29、30 受信機の信号線接続端子 31 受信機の入力絶縁トランス 32 受信機の入力アンプ 33 受信機の信号処理マイコン 34 受信機の信号処理マイコンの情報入力端子 35 断線検出コンパレーター 36 受信機の信号処理マイコンのパルス出力端
子 37、38、39 受信機の信号線駆動トランジスタ 40、41、42 受信機の信号線負荷抵抗 43 外部インターフェイスドライバー 44 外部インターフェイス端子 45 受信機電源 46 受信機より送られる電圧波形 47、47’リセットパルス 48、48’カウントパルス 49、51、53、55 各送信機の送信タイミング図 50、50’、52、52’、54、54’、55 ト
ーン信号
1 Receiver 2, 3 Signal Line 4, 4'Transmitter 5 Termination Resistor 6, 7 Connection Terminal with Signal Line 8, 9 Transmission Transistor 10 Power Supply Series Resistor 11 Power Supply Large Capacitor 12 Three-Terminal Regulator 13 Power Supply 14 Transmission microcomputer 15 Reset pulse separation and shaping circuit 16 Transmission microcomputer count terminal 17, 17 'Transmission switching transistor 18 Transmission microcomputer reset terminal 19 Transmission microcomputer address terminal 20 Transmission microcomputer output terminal 21 Address switch 22 Transmission Microcomputer switching output terminal 23 Information input terminal 24, 25 Transmission microcomputer information output terminal 26, 26 'Tone signal generation low-pass filter 27 Drive signal level shift diode 28 Drive capacitor 29, 30 Receiver signal line connection terminal 31 Reception Input of machine Edge transformer 32 Input amplifier of receiver 33 Signal processing microcomputer of receiver 34 Information input terminal of signal processing microcomputer of receiver 35 Disconnection detection comparator 36 Pulse output terminal of signal processing microcomputer of receiver 37, 38, 39 Signal line driving transistor 40, 41, 42 Signal line load resistance of receiver 43 External interface driver 44 External interface terminal 45 Receiver power supply 46 Voltage waveform sent from receiver 47, 47 'Reset pulse 48, 48' Count pulse 49, 51, 53, 55 Transmission timing diagram of each transmitter 50, 50 ', 52, 52', 54, 54 ', 55 Tone signal

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H04L 29/12 8220−5K H04L 13/00 317 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H04L 29/12 8220-5K H04L 13/00 317

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】受信機端子より2本の受信機情報入力兼送
信機用電源出力線(以下信号線と称す)を延ばし、その
終端に終端抵抗を接続し、受信機端子と終端抵抗との間
に0を除く多数の異なったアドレスを持つ送信機を並列
接続し、送信機への入力情報を受信機に伝送する情報伝
送方式において、受信機より送信機に供給する電源電圧
に、送信機アドレスの最大値より多い一定のカウントパ
ルス数毎にカウントパルスとパルス幅又は振幅の異なる
りセットパルスを挿入し、且つカウントパルスの周期を
送信用マイコンのプログラム実行時間の最大値より長く
した複合パルス列を重畳し、送信機にてこのうちりセッ
トパルスを検出して送信用マイコンをりセット、送信機
アドレス値をセット、待機モードとし、続くカウントパ
ルス毎にセットされた送信機アドレス値より1を減算
し、その値が0以外の送信機は待機モードに、0の送信
機は入力情報を信号線に送出後待機モードとなるように
し、これを繰り返し、すべての送信機の入力情報を、繰
り返し順次受信機に伝送する如く構成した情報伝送方
式。
1. A receiver information input / transmitter power supply output line (hereinafter referred to as a signal line) is extended from a receiver terminal, and a terminating resistor is connected to the end of the line to connect the receiver terminal and the terminating resistor. In an information transmission system in which a number of transmitters having different addresses except 0 are connected in parallel and the input information to the transmitter is transmitted to the receiver, the transmitter is connected to the power supply voltage supplied from the receiver to the transmitter. A composite pulse train in which a count pulse and a reset pulse with a different pulse width or amplitude are inserted for each fixed number of count pulses greater than the maximum value of the address, and the cycle of the count pulse is longer than the maximum program execution time of the transmitting microcomputer. Is set, the transmitter detects this set pulse, sets the transmitter microcomputer, sets the transmitter address value, sets the standby mode, and sets each subsequent count pulse. 1 is subtracted from the transmitter address value, the transmitters whose value is other than 0 are set to the standby mode, and the transmitters of 0 are set to the standby mode after sending the input information to the signal line. An information transmission system configured to repeatedly transmit the input information of the transmitter to the receiver in sequence.
【請求項2】送信用マイコンの電源を信号線より定電流
回路又は抵抗を介して大容量コンデンサに蓄積された電
力で賄い、信号線よりのりセット信号により送信用マイ
コンを一定期間ごとにリセット、プログラム実行後待機
モードとし、供給電流を時間的に平均化し、減少しめた
情報伝送方式。
2. The power source of the transmission microcomputer is supplied from the signal line with electric power stored in a large-capacity capacitor via a constant current circuit or a resistor, and the transmission microcomputer is reset at regular intervals by a glue set signal from the signal line, An information transmission method in which the standby mode is set after program execution, and the supply current is averaged over time to reduce it.
【請求項3】送信機に夫々異なったアドレスを付与し、
信号線よりのリセットパルスによりアドレスをセット
し、信号線よりのカウントパルスによりセット値をカウ
ントダウンし、この値が一定値に達した送信機より入力
情報を送信する情報伝送方式。
3. A different address is given to each transmitter,
An information transmission method in which an address is set by a reset pulse from the signal line, the set value is counted down by a count pulse from the signal line, and input information is transmitted from the transmitter when this value reaches a certain value.
【請求項4】信号線の電圧の積分値を送信用マイコンに
て監視し、この値が一定以上で且つ信号線に重畳したリ
セットパルスが来た時、送信用マイコンをリセットする
情報伝送方式。
4. An information transmission system for monitoring an integrated value of a voltage of a signal line by a transmission microcomputer, and resetting the transmission microcomputer when this value is a certain value or more and a reset pulse superimposed on the signal line is received.
【請求項5】情報入力に対し上下に閾値を設け、上下の
閾値より外の入力は接点入力として判定し、上下の閾値
の間の入力はアナログ入力として判定する如く構成し、
同一構成で接点入力とアナログ入力に対応しうる情報送
信機。
5. An information input is provided with upper and lower thresholds, inputs outside the upper and lower thresholds are determined as contact inputs, and inputs between the upper and lower thresholds are determined as analog inputs.
An information transmitter that can support contact input and analog input with the same configuration.
JP4312563A 1992-10-12 1992-10-12 Information transmission system Pending JPH06152609A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4312563A JPH06152609A (en) 1992-10-12 1992-10-12 Information transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4312563A JPH06152609A (en) 1992-10-12 1992-10-12 Information transmission system

Publications (1)

Publication Number Publication Date
JPH06152609A true JPH06152609A (en) 1994-05-31

Family

ID=18030722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4312563A Pending JPH06152609A (en) 1992-10-12 1992-10-12 Information transmission system

Country Status (1)

Country Link
JP (1) JPH06152609A (en)

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