JPH06160465A - Semiconductor device evaluation method - Google Patents
Semiconductor device evaluation methodInfo
- Publication number
- JPH06160465A JPH06160465A JP31164692A JP31164692A JPH06160465A JP H06160465 A JPH06160465 A JP H06160465A JP 31164692 A JP31164692 A JP 31164692A JP 31164692 A JP31164692 A JP 31164692A JP H06160465 A JPH06160465 A JP H06160465A
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- Prior art keywords
- voltage
- gate
- pinch
- idss
- current
- Prior art date
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- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
(57)【要約】
【目的】 ショットキー接合ゲートを有する半導体装置
の高周波特性を、正確にかつ短時間に評価する。
【構成】 ドレイン／ソース間に５Ｖを印加したときの
ゲート電圧（ピンチオフ電圧Ｖｐ１）を測定する。ゲー
ト／ドレイン間に逆方向電圧を印加した後、再度ゲート
電圧（ピンチオフ電圧Ｖｐ２）を測定する。Ｖｐ１とＶ
ｐ２から逆方向電圧を印加する前後のピンチオフ電圧の
差ΔＶｐを求める。また、飽和ドレイン電流Ｉｄｓｓに
対する高周波利得Ｐ１ｄＢを測定し、ピンチオフ電圧の
差ΔＶｐとＰ１ｄＢ／Ｉｄｓｓとの相関を得る（図
２）。この結果、ΔＶｐとＰ１ｄＢ／Ｉｄｓｓには良好
な相関が見られる。
(57) [Abstract] [Purpose] Accurately and in a short time evaluate the high frequency characteristics of a semiconductor device having a Schottky junction gate. [Structure] A gate voltage (pinch-off voltage Vp1) when 5 V is applied between the drain and the source is measured. After applying a reverse voltage between the gate and the drain, the gate voltage (pinch-off voltage Vp2) is measured again. Vp1 and V
The difference ΔVp of the pinch-off voltage before and after applying the reverse voltage is calculated from p2. Further, the high frequency gain P1dB with respect to the saturated drain current Idss is measured to obtain the correlation between the pinch-off voltage difference ΔVp and P1dB / Idss (FIG. 2). As a result, there is a good correlation between ΔVp and P1dB / Idss.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ショットキー接合ゲー
トを有するＦＥＴ（ＭＥＳＦＥＴ）における高周波特性
の評価方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for evaluating high frequency characteristics of an FET (MESFET) having a Schottky junction gate.
【０００２】[0002]
【従来の技術】化合物半導体結晶を用いた電界効果トラ
ンジスタ、例えばＧａＡｓＭＥＳＦＥＴは、高周波特性
にすぐれており、その製造方法において、高周波利得、
最大出力、混変調特性などの高周波特性（ＲＦ特性）の
評価が不可欠である。2. Description of the Related Art A field effect transistor using a compound semiconductor crystal, for example, GaAs MESFET, has excellent high frequency characteristics.
It is essential to evaluate high frequency characteristics (RF characteristics) such as maximum output and cross modulation characteristics.
【０００３】このため、製造されたＭＥＳＦＥＴのＲＦ
特性を評価し、その特性の優劣を見極めている。また、
これと同時に、直流特性（電流／電圧特性、例えばドレ
イン飽和電流、ピンチオフ電圧など）を評価し、ＭＥＳ
ＦＥＴの選別を行っている。Therefore, the RF of the manufactured MESFET is
The characteristics are evaluated and the superiority or inferiority of the characteristics is determined. Also,
At the same time, the DC characteristics (current / voltage characteristics such as drain saturation current, pinch-off voltage, etc.) are evaluated, and the MES
We are selecting FETs.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、ＭＥＳ
ＦＥＴのＲＦ特性を評価するには、実際に回路を組み立
てて測定しなければならないため、手間や時間が掛かっ
てしまう。[Problems to be Solved by the Invention] However, MES
In order to evaluate the RF characteristics of the FET, it is necessary to actually assemble and measure the circuit, which takes time and effort.
【０００５】また、評価回路や条件によって測定値が異
なるため、ＲＦ特性を一義的に決定できない。すなわ
ち、ＭＥＳＦＥＴの活性層がキャリア濃度一定の箱型プ
ロファイルの場合、ゲート電極、ソース／ドレインとな
るオーミック電極、ゲート長やゲート幅、パッシベーシ
ョン膜など、全ての構造が等しければ、ＲＦ特性は活性
層の厚さによって決定される。Further, since the measured values differ depending on the evaluation circuit and conditions, the RF characteristics cannot be uniquely determined. That is, when the active layer of the MESFET has a box-shaped profile with a constant carrier concentration, if all structures such as the gate electrode, the ohmic electrode serving as the source / drain, the gate length and the gate width, and the passivation film are the same, the RF characteristic is the active layer. Is determined by the thickness of.
【０００６】ところが、現実にはこれら全ての構造を等
しくすることができないため、活性層の厚さのみによっ
てＲＦ特性を一義的に決定することができない。However, in reality, all these structures cannot be made equal, and therefore the RF characteristics cannot be uniquely determined only by the thickness of the active layer.
【０００７】本発明の目的は、実際に回路を組み立てな
くとも、正確にかつ短時間に高周波特性を評価すること
ができる評価方法を提供することにある。An object of the present invention is to provide an evaluation method capable of accurately evaluating a high frequency characteristic in a short time without actually assembling a circuit.
【０００８】[0008]
【課題を解決するための手段】上記課題を解決するため
に、本発明は、ショットキー接合ゲートを有する半導体
装置の高周波特性の評価方法において、該半導体装置の
電流／電圧特性を測定した後、前記ショットキー接合ゲ
ートに逆方向電圧を印加し、再度該半導体装置の電流／
電圧特性を測定して、逆方向電圧を印加する前後の電流
／電圧特性の変化を算出する工程を含むものである。In order to solve the above problems, the present invention provides a method for evaluating the high frequency characteristics of a semiconductor device having a Schottky junction gate, after measuring the current / voltage characteristics of the semiconductor device, Reverse voltage is applied to the Schottky junction gate, and the current of the semiconductor device
It includes the step of measuring the voltage characteristic and calculating the change in the current / voltage characteristic before and after applying the reverse voltage.
【０００９】上記電流／電圧特性としては、ピンチオフ
電圧、ドレイン電流値などがある。また、逆方向電圧と
しては、ゲートが破壊されない程度の逆方向電流が流れ
る程度以下の電圧とする。The current / voltage characteristics include a pinch-off voltage and a drain current value. Further, the reverse voltage is set to a voltage equal to or lower than a flow amount of a reverse current that does not damage the gate.
【００１０】[0010]
【作用】本発明においては、ＲＦ特性が、ゲート／半導
体界面や半導体表面の欠陥準位によって大きく影響され
る性質があり、またこの欠陥準位の変化が電流／電圧特
性の変化と相関があることを利用している。In the present invention, the RF characteristics have the property of being greatly influenced by the defect level at the gate / semiconductor interface or the semiconductor surface, and the change in this defect level correlates with the change in the current / voltage characteristics. I'm taking advantage of that.
【００１１】すなわち、ＭＥＳＦＥＴのゲートに逆方向
電圧を印加すると、欠陥準位の荷電状態が変化すること
によって活性層における空乏層形状が変化し、その結果
電流／電圧特性も変化する。That is, when a reverse voltage is applied to the gate of the MESFET, the shape of the depletion layer in the active layer changes due to a change in the charge state of the defect level, and as a result, the current / voltage characteristic also changes.
【００１２】一方、ＲＦ特性においても、空乏層形状が
変化することによってその特性が変化することが知られ
ている。On the other hand, it is known that the RF characteristics also change when the shape of the depletion layer changes.
【００１３】従って電流／電圧特性の変化を測定するこ
とで、このような欠陥準位と相関する値を測定すること
ができ、これによりＲＦ特性を評価することができる。Therefore, by measuring the change in the current / voltage characteristic, it is possible to measure the value correlated with such a defect level, and thereby the RF characteristic can be evaluated.
【００１４】[0014]
【実施例】以下、本発明の実施例について説明する。EXAMPLES Examples of the present invention will be described below.
【００１５】まず、評価対象とするＧａＡｓＭＥＳＦＥ
Ｔの製造方法を説明する。First, GaAs MESFE to be evaluated
A method of manufacturing T will be described.
【００１６】半絶縁性ＧａＡｓ基板上に、厚さ１５０ｎ
ｍ、キャリア濃度２×１０17ｃｍ-3のｎ型活性層をエピ
タキシャル成長させた後、リソグラフィ技術及び真空蒸
着技術を用いてゲート電極とオーミック電極を形成す
る。150 n thick on a semi-insulating GaAs substrate
After epitaxially growing an n-type active layer having m and a carrier concentration of 2 × 10 17 cm −3 , a gate electrode and an ohmic electrode are formed by using a lithography technique and a vacuum evaporation technique.
【００１７】ここで、オーミック電極としては、ＡｕＧ
ｅ（２００ｎｍ）／Ｎｉ（４０ｎｍ）を用い、真空蒸着
後にオーミック性を得るためにアニールを行った。Here, AuG is used as the ohmic electrode.
Using e (200 nm) / Ni (40 nm), annealing was performed to obtain ohmic properties after vacuum deposition.
【００１８】また、ゲート電極としては、Ａｌ（３００
ｎｍ）を用い、真空蒸着を行う前にウェットエッチング
を行い、リセス構造とした。なお、ゲート長を０．５μ
ｍ、ゲート幅を４００μｍとした。As the gate electrode, Al (300
nm), and wet etching was performed before vacuum deposition to form a recess structure. The gate length is 0.5μ
m and the gate width was 400 μm.
【００１９】この後、ＭＥＳＦＥＴの保護膜としてＰ−
ＣＶＤ（プラズマＣＶＤ）法によってＳｉＮのパッシベ
ーション膜を１５０ｎｍ堆積させる。After that, as a protective film for the MESFET, P-
A SiN passivation film is deposited to a thickness of 150 nm by the CVD (plasma CVD) method.
【００２０】さらに、ＧａＡｓ基板を厚さ５０μｍに加
工し、ダイシングソーで分離し、パッケージングした。Further, the GaAs substrate was processed to a thickness of 50 μm, separated with a dicing saw, and packaged.
【００２１】このように製造されたＧａＡｓＭＥＳＦＥ
Ｔの電気的特性は、Ｉｄｓｓ＝９０〜１１０ｍＡ、Ｖｐ
＝−３．５〜−２．５Ｖ、Ｖｇｄ０＝−２０〜−１５Ｖ
であった。GaAs MESFE manufactured in this way
The electrical characteristics of T are Idss = 90 to 110 mA, Vp
= -3.5 to -2.5V, Vgd0 = -20 to -15V
Met.
【００２２】次に、このＭＥＳＦＥＴのＲＦ特性の評価
方法について説明する。Next, a method of evaluating the RF characteristics of this MESFET will be described.
【００２３】まず、ドレイン／ソース間に５Ｖを印加
し、ドレイン電流Ｉｄが飽和ドレイン電流Ｉｄｓｓの１
％となるときのゲート電圧を測定し、これをピンチオフ
電圧Ｖｐ１とする。First, 5 V is applied between the drain and the source, and the drain current Id is 1 of the saturated drain current Idss.
The gate voltage when it becomes% is measured, and this is defined as the pinch-off voltage Vp1.
【００２４】次に、ゲート／ドレイン間に逆方向電圧を
印加し、逆方向電流（１０μＡ／４００μｍゲート幅）
を１秒間流す。Next, a reverse voltage is applied between the gate and the drain to generate a reverse current (10 μA / 400 μm gate width).
For 1 second.
【００２５】この後、再度上述した方法でゲート電圧を
測定し、これをピンチオフ電圧Ｖｐ２とする。これらＶ
ｐ１とＶｐ２との差から、逆方向電圧を印加する前後の
変化ΔＶｐを求める。After that, the gate voltage is measured again by the above-mentioned method, and this is set as the pinch-off voltage Vp2. These V
From the difference between p1 and Vp2, the change ΔVp before and after applying the reverse voltage is obtained.
【００２６】また、このピンチオフ電圧の差ΔＶｐの測
定とは別に、ピンチオフ電圧と相関のあるＲＦ特性を以
下のように測定する。In addition to the measurement of the pinch-off voltage difference ΔVp, the RF characteristic correlated with the pinch-off voltage is measured as follows.
【００２７】ドレイン電圧Ｖｄを５Ｖとし、ドレイン電
流Ｉｄが飽和ドレイン電流Ｉｄｓｓの５０％となるよう
に直流電源によってバイアス条件を定め、周波数１４．
５ＧＨｚでＩｄｓｓに対する高周波利得Ｐ１ｄＢ（１ｄ
Ｂ利得圧縮時出力電力）を測定する。The drain voltage Vd is set to 5 V, the bias condition is set by the DC power supply so that the drain current Id becomes 50% of the saturated drain current Idss, and the frequency is set to 14.
High frequency gain P1dB (1d for Idss at 5 GHz
Output power at B gain compression) is measured.
【００２８】測定された、Ｉｄｓｓに対するＰ１ｄＢの
関係を図１に示す。また、ピンチオフ電圧の差ΔＶｐ
と、図１から得られるＰ１ｄＢ／Ｉｄｓｓとの相関を図
２に示す。FIG. 1 shows the measured relationship of P1 dB with respect to Idss. Also, the difference in pinch-off voltage ΔVp
And the correlation with P1dB / Idss obtained from FIG. 1 are shown in FIG.
【００２９】図１からＩｄｓｓとＰ１ｄＢには相関が見
られないが、図２から分かるように、ΔＶｐとＰ１ｄＢ
／Ｉｄｓｓには良好な相関が見られる。From FIG. 1, there is no correlation between Idss and P1dB, but as can be seen from FIG. 2, ΔVp and P1dB
A good correlation is seen in / Idss.
【００３０】従って、ΔＶｐを求めることによってＭＥ
ＳＦＥＴのＲＦ特性を容易に評価することができる。Therefore, by obtaining ΔVp, ME
The RF characteristics of the SFET can be easily evaluated.
【００３１】[0031]
【発明の効果】以上のように、本発明によれば、実際に
回路を組み立てる手間や時間を掛けなくとも、ゲートに
逆方向電圧を印加する前後の電流／電圧特性の変化を測
定することにより、正確にかつ短時間に高周波特性を評
価することができる。As described above, according to the present invention, the change in the current / voltage characteristic before and after the reverse voltage is applied to the gate can be measured without spending time and effort for actually assembling the circuit. The high frequency characteristics can be evaluated accurately and in a short time.
【図１】飽和ドレイン電流Ｉｄｓｓと高周波利得Ｐ１ｄ
Ｂとの関係を示すグラフである。FIG. 1 is a saturation drain current Idss and a high frequency gain P1d.
It is a graph which shows the relationship with B.
【図２】ピンチオフ電圧の差ΔＶｐとＰ１ｄＢ／Ｉｄｓ
ｓとの相関を示すグラフである。FIG. 2 shows a difference ΔP in pinch-off voltage and P1dB / Ids.
It is a graph which shows the correlation with s.
Claims (1)
装置の高周波特性の評価方法において、 該半導体装置の電流／電圧特性を測定した後、前記ショ
ットキー接合ゲートに逆方向電圧を印加し、再度該半導
体装置の電流／電圧特性を測定して、逆方向電圧を印加
する前後の電流／電圧特性の変化を算出する工程を含む
ことを特徴とする半導体装置の評価方法。1. A method for evaluating a high frequency characteristic of a semiconductor device having a Schottky junction gate, wherein a current / voltage characteristic of the semiconductor device is measured, a reverse voltage is applied to the Schottky junction gate, and the semiconductor is then again measured. A method for evaluating a semiconductor device, comprising a step of measuring a current / voltage characteristic of the device and calculating a change in the current / voltage characteristic before and after applying a reverse voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31164692A JPH06160465A (en) | 1992-11-20 | 1992-11-20 | Semiconductor device evaluation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31164692A JPH06160465A (en) | 1992-11-20 | 1992-11-20 | Semiconductor device evaluation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06160465A true JPH06160465A (en) | 1994-06-07 |
Family
ID=18019787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31164692A Pending JPH06160465A (en) | 1992-11-20 | 1992-11-20 | Semiconductor device evaluation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06160465A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117452173A (en) * | 2023-11-14 | 2024-01-26 | 忱芯科技(上海)有限公司 | A power semiconductor turn-off characteristic testing circuit, method and device |
-
1992
- 1992-11-20 JP JP31164692A patent/JPH06160465A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117452173A (en) * | 2023-11-14 | 2024-01-26 | 忱芯科技(上海)有限公司 | A power semiconductor turn-off characteristic testing circuit, method and device |
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