JPH06161832A - Trace controller - Google Patents

Abstract

PURPOSE:To store double operational history information as much as conventional information and therefore to facilitate the analysis of a fault cause by providing required information when information is read from a tracer memory for analyzing the fault. CONSTITUTION:Both of a master processor and a slave processor are provided with master side and slave side tracer memories 14 and 20 for storing the operational history information of those processors, master side and slave side selectors 10 and 16 for selecting internal history information designated by an instruction signal between the two kinds of internal history information to be inputted, and master side and slave side trace control parts 15 and 21 for controlling the write operation of information from the selectors 10 and 16 inside the tracer memories 14 and 20, and an instruction is applied so that the internal history information of various contents can be stored in the matser processor side tracer memory 14 and the slave processor side tracer memory 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trace control device for tracing operation history information of a processor having a functional redundancy monitor function.

[0002]

2. Description of the Related Art A conventional trace control device for tracing operation history information of a processor of an information processing device generally collects information for analyzing a failure of the processor when the failure occurs. However, the processor uses a functional redundancy monitor (FRM: Functional Redundancy Monita).
In the case of the r) configuration, the tracer memories of the two processors forming the FRM function both employ the control method of storing the same content information.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As mentioned above, FR
A conventional trace control device for tracing operation history information of a processor having an M function has a tracer memory of a master processor and a tracer memory of a slave processor that store the same contents of information. Since there are two units, the amount of information that can be stored is half the amount of hardware,
It has the drawback that the hardware cannot be used effectively. Therefore, even if the information is read from the tracer memory to analyze the failure, the cause of the failure may not be analyzed because the necessary information is not stored in the tracer memory.

[0004]

A trace control device of the present invention specifies a tracer memory for storing operation history information of a processor having a functional redundancy monitor configuration and an instruction signal of two input internal history information. Selector that selects the internal history information of the
And a trace control unit for controlling an operation of writing information from the selector in the tracer memory.

[0005]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of an information processing apparatus adopting the embodiment of FIG.

In FIG. 2, a bus 5 transmits information between the master processor 1 and the slave processor 2 and other processors (not shown). When the master processor 1 and the slave processor 2 are operating normally, the FRM function circuit 8 performs the same processing as the master processor 1 that actually performs various processing and the master processor 1 to create comparison data and the like. The contents of processing with the slave processor 2 to be performed are compared to check the correctness of the operation of these two processors.

The master side trace unit 3 in the master processor 1 receives the master instruction signal 6 from the master processor 1
The internal trace information on the side is stored in the tracer memory, the address of the tracer memory is generated, and the trace information is read. The slave side trace unit 4 in the slave processor 2 stores the internal trace information on the slave processor 2 side in the tracer memory in response to the slave instruction signal 7, generates the address of the tracer memory, and reads the trace information.

As shown in FIG. 1, the master side trace section 3 includes a master side selector 10 and a master side tracer memory 1.
4 and the master side trace control unit 15, the master side selector 10 uses the master instruction signal 6 to generate the first master internal history information 11 and the second master internal history information 11 indicating the operation history information on the master processor 1 side. Either one of the internal history information 12 is selected. The master-side tracer memory 14 stores the master internal trace information 13 input from the master-side selector 10 in the address generated by the master-side trace control unit 15. The master side trace control unit 15 controls the start and stop of the storage of the master internal trace information 13 in the master side tracer memory 14.

The slave side trace unit 4 has a slave side selector 16, a slave side tracer memory 20, and a slave side trace control unit 21, and the slave side selector 16 receives a slave instruction signal 7 to send data to the slave processor 2 side. One of the first slave internal history information 17 and the second slave internal history information 18 indicating the operation history information of is selected. The slave side tracer memory 20 stores the slave internal trace information 19 input from the slave side selector 16 at the address generated by the slave side trace control unit 21. The slave side trace control unit 21 controls the start and stop of the storage of the slave internal trace information 19 in the slave side tracer memory 20.

Next, the operation of the trace control device configured as described above will be described.

When the master processor 1 and the slave processor 2 having the FRM function are operating normally, the information indicating the operation history of the master processor 1 and the information indicating the operation history of the slave processor 2 are exactly the same. The master side trace unit 3 inputs two pieces of information, the first master internal history information 11 and the second master internal history information 12, to the master side selector 10. Similarly, the slave side trace unit 4 includes the first slave internal history information 17
And the second slave internal history information 18 are input to the slave side selector 16. At this time, the master internal history information 11 and the slave internal history information 17 are the same information, and the master internal history information 12 and the slave internal history information 18 are the same information.

The master instruction signal 6 is the master side selector 10
To the slave side selector 16 when the first master internal history information 11 is selected, the slave instruction signal 7 instructs the slave side selector 16 to select the second slave internal history information 18. give. (When the master instruction signal 6 instructs the master side selector 10 to select the second master internal history information 12,
The slave instruction signal 7 gives an instruction to the slave side selector 16 to select the first slave internal history information 17. ) The master selector 10 selects the first master internal history information 11 from the first master internal history information 11 and the second master internal history information 12, and sets it as the master internal trace information 13 on the master side. Output to the tracer memory 14. The master side tracer memory 14 is
The input master internal trace information 13 is stored in the address generated by the master side trace control unit 15. Next, the slave side selector 16 selects the second slave internal history information 18 from the first slave internal history information 17 and the second slave internal history information 18 by the slave instruction signal 7, and then selects the second slave internal history information 18 from the slave internal history information 18. The trace information 19 is output to the tracer memory 20 on the slave side. The slave side tracer memory 20 stores it in the address generated by the slave side trace control unit 21. By the above operation, it is possible to store information having different contents in the master side tracer memory 14 and the slave side tracer memory 20.

[0014]

As described above, the trace control apparatus of the present invention has a tracer memory for storing operation history information of both the master processor and the slave processor and two internal history information to be input. The tracer memory on the master processor side and the tracer memory on the slave processor side are provided with a selector for selecting the internal history information designated by the instruction signal of 1 By giving an instruction to store the internal history information having a different content from the memory, there is an effect that it is possible to store the operation history information twice as large as the conventional one, and therefore, in order to analyze the failure. Since the necessary information can be obtained when the information is read from the tracer memory, There is an effect that is the analysis becomes easier.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of an information processing apparatus adopting the embodiment of FIG.

[Explanation of symbols]

 1 Master Processor 2 Slave Processor 3 Master Side Trace Unit 4 Slave Side Trace Unit 5 Bus 6 Master Indication Signal 7 Slave Indication Signal 8 FRM Function Function Circuit 10 Master Side Selector 11 ・ 12 Master Internal History Information 13 Master Internal Trace Information 14 Master Side Tracer memory 15 Master side trace control unit 16 Slave side selector 17/18 Slave internal history information 19 Slave internal trace information 20 Slave side tracer memory 21 Slave side trace control unit

Claims (1)

[Claims] 1. A tracer memory for storing operation history information of a processor having a functional redundancy monitor configuration, and a selector for selecting one of two input internal history information which is specified by an instruction signal. A trace control unit that controls a write operation of information from the selector in the tracer memory.