JPH0215340A - Control system for state history memory device - Google Patents

Abstract

PURPOSE:To reduce labor and time required for fault analysis by adding an address coincidence detecting circuit for detecting coincidence between a storage starting resist setting up an optional instruction and an executing program to the title system. CONSTITUTION:In order to execute a program instruction A, a fetch address signal 12 for an instruction A is inputted from a control unit 5 to an address coincidence detecting circuit 16. At that time, the address signal 12 coincides with a signal outputted from a storage start address register 15. An address coincidence signal 17 is inputted from the detecting circuit 16 to the control unit 5 and the unit 5 sends a storage stop signal 81 to a state history storage device 6. At the time of generating a fault, an operator stops an information processor by a device stop signal 91 through a service processor 7 and reads out state history information 11 precedently stored in the storage device 6 to utilize the information 11 for the analysis of a fault.

Description

[Detailed Description of the Invention] [Summary] In an information processing device, the storage of a state history device is stopped for the purpose of simplifying failure analysis of a program having a loop during development and testing of the information processing device. a memory stop state register that holds a first setting state; a first state coincidence detection means that outputs a signal when a match between the setting state held in the memory stop state register and the running state is detected; a storage stop state register that holds a second setting state for starting storage of the state history device; and a second storage stop state register that outputs a signal when a match between the setting state held in the storage start state register and the running state is detected. stop storing the state history by a signal from the first state match detection means and the first state match detection means;
The present invention is configured to provide a control method for a state history storage device having the above-mentioned state history storage device that starts storing the state history in response to a signal from the second state coincidence detection means.

[Industrial application field]

The present invention relates to a control method for a state history storage device for performing failure analysis of an information processing device.

[Conventional technology]

When developing and testing information processing equipment, etc., if the equipment malfunctions or does not work as intended, the history of various internal state changes within the information processing equipment may be stored as information for investigating the cause of the failure. . State history storage devices used for such purposes are typically F , I F
It consists of O memory, etc., and sequentially records the internal state that is considered necessary to find the cause of the failure, and when a failure occurs in the device, it is stopped and the status history at the time of failure and before that is saved, and then The status history of each part of the device is read from this status history storage device via a service processor, etc.
The information is effectively used to investigate the cause of the failure. However, this state history storage device has a limited storage capacity, and past history information exceeding a certain limit is outdated by storing new history information. Therefore, in order to obtain effective state history information, it is important to select the type of internal state and the timing at which to start and stop storing the history.

When executing a program, if instruction B does not move to the next instruction, consider that there is a problem with instruction B or between the instruction executed before instruction B and instruction B. Status B history information at the time of execution of the above-mentioned instruction may be obtained and analyzed.

The start and stop of storage in the state history storage device has also been controlled by microprograms or instructions from a service processor. However, in a microprogram, if a failure always occurs with a certain instruction B, it is possible to analyze the failure by programming the state history storage device to stop storing the microprogram words executed by that instruction B. However, for a failure that occurs only when instruction B is executed immediately after another instruction, if instruction B is executed alone before instructions A and B are executed in conjunction,
At that point, the state history storage device is stopped,
I can't get the information I need. Furthermore, since the service processor has slower processing power than the monitored device of the information processing device, it cannot control the information processing device in the way necessary to save the state history. Furthermore, even if the operator notices the failure after command B is executed and stops the state history storage device through the service processor, several seconds have passed since the abnormality occurred in command B. The state history storage device has a limited storage capacity and can only store the state up to several seconds ago, making it impossible to obtain the necessary information.

Therefore, it is necessary to stop storing the state history storage device at the address of a certain target program or at a preset state of each part of the device. Conventionally, the entire information processing device is stopped when the program address or the preset state of each part of the device matches, and the state history device also stops writing, and at that time, the state B
A function was provided for recording the information stored in the history storage device in the service processor, and then restarting the state history storage device and executing the continuation of the program.

FIG. 3 is a block diagram of a conventional information history storage system. In the figure, 1 is a storage management unit, 2 is a storage stop address register, 3 is an address-number configuration circuit, 4 is a main storage device, 5 is a control unit, 6 is a state history storage device, 7 is a service processor, and 8 is a 10 is a device stop signal, 9 is a device restart signal, 1o is a storage start signal, II is state history information, 12 is a fetch address, 13 is an address match signal, 14 is fetch data, and 60 is information on the monitored device.

In order to obtain state history information for failure analysis in the case of a failure that occurs when instruction B is executed, the storage stop address register 2, in which the address of instruction B is set, and the storage stop address register 2 are required. An address-number construction circuit 3 is provided for detecting a match between the designated address and the address of the instruction being fetched.

Normally, the execution of the program is as described in 1. The α device 4 sends fetch data 14 to the control unit 5 using the fetch address 12, and the control unit 5 controls the interpretation and execution of instructions of the arithmetic unit. At this time, the state history storage device 6 stores information 60 of the monitored device of the information processing device as needed.

In order to execute instruction B of the program, the fetch address signal 12 of instruction B is input from the control unit 5 to the address-number construction circuit 3 inside the storage management unit 1 at the address of instruction B. At this time, the fetch address signal 12 matches the signal from the storage stop address register 2 set to the address of instruction B. Then, the address matching signal 13 is inputted from the address-number output circuit 3 to the control unit 5, and from there, a device stop signal 8 is sent to each part of the monitored device of the information processing device and the state history storage device 6. Each part of the monitoring device is stopped, the state history storage device is stopped, and the storage of state times is stopped. Therefore, the operator of the information processing device stores the state history information 11 in the state history storage device 6 in another location via the service processor 7. Then service processor 7
A storage start signal 10 is sent to the state history storage device 6 via the state history storage device 6 to instruct the state history storage device 6 to start storage, and then the information processing device is caused to continue the program from the instruction following instruction B. After that, if a failure occurs, the status history information 11 read earlier via the service processor 7 is used to analyze the cause.

However, if there is a failure in the loop of a program that has a loop that includes instruction B, and it is not known in which loop instruction B causes the failure, when analyzing the failure, as described above, At the address of instruction B, the operation of the information processing device is stopped once, and the information history storage device 6 is
The state history information 11 is read out via the service processor 7 and saved in another location. Then, after giving an instruction to the information history storage device 6 to start storing,
If the information processing device is restarted and a failure occurs thereafter, the status history information read earlier is used for failure analysis.

However, if no failure occurs, the above operation must be repeated because it is a loop and instruction B is executed again. In other words, after the operation of the information history storage device and each part of the monitored device of the information processing device is stopped by command B until a failure occurs, the operator operates the service processor to read the state history information and It is necessary to repeatedly store the information in another location, give permission to the information history storage device to start storage via the service processor, and then have the information processing device continue executing the program.

[Problem to be solved] As shown in the conventional example, in a program that has a loop that includes instruction B, instruction B in the loop has a failure, and in what loop does instruction B cause the failure? In cases where the fault is unknown, the task of analyzing the fault requires the operator of the information processing device to spend a great deal of effort and time. Furthermore, in the conventional example, storage of the state history device was stopped using a fetch address, but this can also be done using a store address or the contents of a general-purpose register. In that case as well, the above problem occurred.

Therefore, the present invention provides an efficient control method for a state history storage device that does not require a great deal of effort and time to analyze a fault included in a loop.

[Means for Solving the Problems] An information processing device having a state history storage device for recording the state of each part of the device includes a storage stop state register that holds a first setting state for stopping storage of the state history storage device. and a first one that outputs a signal when it detects a match between the setting state held in the memory stop state register and the running state.
a state-number configuration means, a storage start state register that holds a second setting state for starting storage in the state history storage device, and a setting state and an execution state held in the storage start state register. There is provided a control method for a nine-device device that records a state history, characterized in that it includes a second state-number configuration means that outputs a signal when a match is detected.

[Operation] If there is a failure in instruction B in the loop of a program that has a loop including instruction B, and it is not known in which loop instruction B will cause the failure, the memory stop state register The address of instruction B or the state of a certain part of the device at that time is set in . The storage start status register contains one of the instructions in the loop and instruction B.
Sets the address of the instruction A that is always executed before the instruction A is executed, or the state of a certain part of the device at that time. -For boat fishing, this command A can be the first command in the loop. The storage start state register and the second state-number construction circuit are
Instruction A starts storing the state history storage device. Then, the memory stop state register and the first state-number construction circuit are as follows:
Command B stops storage in the state history storage device. Command B
At the time when the process is executed, the status of each part of the device is stored in the status history storage device. Here, if a failure occurs, the operator stops the information processing device via the service processor. Then, the state history information is read from the state history storage device whose storage was stopped earlier and the failure is analyzed.

If no failure occurs in command B, the operator does not stop the information processing device. Therefore, since the program is in a loop, the information processing device executes instruction A again. At this time, the storage start state register and the second state-number configuration circuit cause the information history storage device to start storing the information in response to the instruction A. Again, the memory stop state register and the first state-number construction circuit are as follows:
Command B stops storage in the information history storage device. This operation continues in this manner until a failure occurs.

Only after a failure occurs does the operator stop the information processing device via the service processor.

Although it takes time to stop the information processing device, since the state history storage device is stopped from storing at the time of execution of instruction B, the necessary state H layer information remains in the state history storage device. In this way, it is possible to perform processing for failure analysis without operator intervention until a failure occurs.

〔Example〕

FIG. 1 is a block diagram of an embodiment of a control method for a state history storage device of the present invention, and FIG. 2 is a block diagram of the control unit of FIG. 1. In the figure, 1 is a storage management unit, 2 is a storage stop address register, 3 is an address-number configuration circuit, 4 is a main storage device, 5 is a control unit, 6 is a state B history storage device, 7 is a service processor, 10 is a storage start signal, 11 is state history information, 12 is a fetch address, 13
is the address match signal, 14 is the fetch data, 15 is the storage start address register, and 16 is the fetch address 12.
17 is an address-defeat signal, 18 is a selection circuit, 1
9 is an AND circuit, 20 is an OR circuit, 21 is an instruction decoder, 22 is an operand valid signal, 23 is an instruction buffer, 2
4 is an arithmetic circuit, 60 is information on the monitored device, 81 is a storage stop signal, and 91 is a device stop signal.

This example is for failure analysis when there is a failure in instruction B in the loop of a program that has a loop including instruction B, and it is not known in which loop instruction B causes the failure. , a memory halt address register 2 in which the address of instruction B is set as a memory halt state register, and an address as a first state-number configuration means for detecting a match between the memory halt state register 2 and the program being executed. - a memory start circuit 3, and an arbitrary instruction A that is one of the instructions in the loop and is always executed before instruction B is executed as a memory start status register; An address-number construction circuit 16 is provided as a second state-number construction means for detecting a match between the address register 15 and the storage start state register 15 and the program being executed.

Now, in order to execute the instruction A of the program, the fetch address signal 12 of the instruction A is inputted from the control unit 5 to the address-number construction circuit 16 inside the storage management unit 1. At this time, the fetch address signal 12 of instruction A
This matches the signal from the storage start address register 15 set in the instruction A. And address-number configuration circuit 16
An address match signal 17 is input to the control unit 5 from the address matching signal 17 .

FIG. 2 is a block diagram inside the control unit 5. As shown in FIG.

The address match signal 17 input to the control unit 5 in FIG. 2 is input to either the instruction buffer 23. While the arithmetic circuit is executing the next instruction, it prefetches the next instruction from the main memory.After the instruction being executed is finished, the prefetched instruction is input to the arithmetic circuit.Usually, multiple instruction buffers are provided to is on standby.

Assume that the address match signal 17 is input to the instruction buffer 23. Fetch data 14 input from main memory 4 to control unit 5 is also input to command buffer 23 . Address match signal 1 input to instruction buffer 23
7 and fetch data 14 are input to the selection circuit 18' and the selection circuit 18', respectively. The address match signal 17 inputted to the selection circuit 18' is sent to the OR circuit 20',
The fetch data 14 input to the 8th pass is sent to the instruction decoder 2.
1 respectively. Then, the instruction decoder 21 sends the instruction to the arithmetic circuit 23, and the OR circuit 20'' sends the storage start signal 10 to the state history storage bag W6.The reason why the address match signal 17 was input to the instruction buffer 23 earlier is to execute the instruction A. This is to adjust the output timing so that the storage start signal is output at this point in time.Therefore, information 60 of the monitored device is input to the state history storage device 6 at any time.

In order to execute instruction B, the fetch address signal 12 of instruction B is input from the control unit 5 to the address-number construction circuit 16 inside the storage management unit 1. At this time,
The fetch address signal 12 matches the signal from the storage stop address register 2, which is set to the address of instruction B. Then, an address match signal 13 is input from the address/number configuration circuit 3 to the control unit 5.

The address match signal 13 input to the control unit 5 is input to one of the instruction buffers 23, 23' and 23'. For example, assume that the command is input to the command buffer 23. The reason why the address match signal 13 is input to the instruction buffer 23 is to adjust the output timing so that the storage stop signal 81 is output when the instruction B is executed. Fetch data 14 input from main memory 4 to control unit 5 is input to command buffer 23 . The address match signal 13 and fetch data 14 input to the instruction buffer 23 are input to the selection circuit 18 and the selection circuit 18', respectively. The address match signal 13 input to the selection circuit 18 is sent to the OR circuit 2
0, the fetch data 14 input to the selection circuit 18'
are manually input to the instruction decoder 21. Then, the instruction decoder 21 sends an instruction to the arithmetic circuit 23, and the OR circuit 20 sends a storage stop signal 81 to the state history storage device 6. Therefore, the memory stop signal 81 is manually input to the information history storage device 6,
The information history storage device 6 stores the state history of each part of the device.

After that, if a failure occurs, the operator stops the information processing device with a device stop signal 91 via the service processor 7, reads the state history information 11 previously stored in the state history storage device 6, Used for failure analysis.

If no failure occurs after the information history storage device 6 stops storing information, the instruction A is executed again because it is a loop. In order to execute the instruction A of the program, the fetch address signal 13 of the instruction A is inputted from the control unit 5 to the address-number construction circuit 16 inside the storage management unit 1 . At this time, it matches the signal from the storage start address register 15 set in the instruction A. Then, a storage start signal 10 is inputted from the address/number configuration circuit 16 to the state history storage device 6, and the state history of each part of the device is inputted to the state history storage device 6 again at any time. Stop remembering 6.

This operation continues in this manner until a failure occurs. Only after a failure occurs does the operator stop the information processing device using the device stop signal 91 via the service processor 7 and read the state history information 11 previously stored in the state history storage device 6. Intervene and use it to analyze failures.

The present invention has been described above with reference to examples. In the example,
Although instruction addresses are set in the storage stop address register and storage start address register, operand addresses may also be used. For operand addresses,
Since the fetch data becomes operand data, an operand valid signal 22 and an AND circuit 19 are provided in the control unit 5.
．． 19 to distinguish between operands and instructions.

In this embodiment, the state history storage device is stopped or started based on a match with the front address of the instruction, but the store address or the contents of general-purpose registers in each part of the device can also be used to stop or start the state history storage device. It is possible to start or stop storage of the state history device at any time.

Additionally, there are several circuits for detecting address matching in the devices that constitute the information processing device.

For example, the main memory initialization start, end address register, and end address-number circuits that are used only when starting up the device are not used after starting up, so by sharing them with the above device, the present invention can be implemented with almost no increase in physical quantity. It is also possible to realize the following. Further, in this embodiment, two address/number configuration means are provided, but only one may be provided and used in a switched manner.

As described above, the present invention can be modified in various ways in accordance with the gist of the present invention, and these are not excluded from the present invention.

[Effect] According to the present invention, an operator of an information processing device can stop and start storage of the state history storage device without giving a command to stop and start storage of the state history storage device from the service processor. , The number of times the information processing device is started and restarted, and the state history storage device is instructed to stop and start storage during failure analysis is significantly reduced, so the effort required for failure analysis is reduced.
Time decreases.

Further, as described in the embodiment, by sharing the circuit with other circuits, the present invention can be realized with almost no increase in the number of devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of the inside of the control unit in FIG. 1, and FIG. 3 is a block diagram of a conventional system. 1.1゛...Storage management unit 2...Memory stop address register 3...Address-number configuration circuit 4...Main storage device 5.5°...Control unit 6...Status history Storage device 7...Service processor 8...Device stop signal 9...Device restart signal 10...Storage start signal book 12, 13, 14, 15, 16, 17, 18. 19. 20. 21・ 22・ 23. 24・ 60・ 81・ 91・・・State history information・・Fetch address・・Address match signal・・Fetch data・・Storage start address register・・Address-number construction circuit・・Address match signal 18.18”・...Selection circuit 19''...AND circuit 20''...OR circuit...Instruction decoder...Operand valid signal 23'', 231...Instruction buffer...Arithmetic circuit...Monitored device information...Storage Stop signal...Equipment stop signal

Claims (1)

[Scope of Claims] An information processing device having a state history storage device for recording the state of each part of the device, comprising: a memory stop state register that holds a first setting state for stopping storage of the state history storage device; a first state coincidence detection means that outputs a signal when detecting a match between the setting state held in the storage stop state register and the running state; and a second setting state that causes the state history storage device to start storing. a memory stop state register that holds the storage start state register; a second state coincidence detection means that outputs a signal when a match between the setting state held in the memory start state register and the running state is detected; and a first state coincidence detection means. The storage of the state history is stopped by the signal of the means, and the storage of the state history is stopped by the signal of the second state coincidence detection means.
1. A control method for a state history storage device, comprising: the state history storage device described above that starts storing a state history.