JPH0616532B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit having programmable chip functions.

[Technical background of the invention and its problems]

2. Description of the Related Art In recent years, the following LSIs have emerged with the demand for small-quantity and high-mix types of semiconductor integrated circuits.

(1) Standard Cell Method Circuit blocks used in the LSI are registered in advance in a computer, and these circuit blocks are arranged and wired by an automatic process of the computer to obtain a desired final product.

(2) Gate array method The basic circuits constituting the logic gate are arranged and formed in advance on the substrate in an array form, and the wiring pattern is determined on this by automatic wiring similarly to the standard cell method to obtain a desired LSI. .

These have the advantage that the development period is shorter than that of a completely hand-designed LSI. However, even in these methods, a manufacturing process using a lithography technique is required, and there is a problem that it takes several weeks to several months from completion of design to completion of LSI.

On the other hand, the applicant has previously proposed an LSI system in which the chip function is completely field programmable. (Japanese Patent Application No. 58-157718). The basic structure is as shown in FIG. In the figure, circuit blocks 51 ₁ , 5 each composed of one or more logic skill elements
1 _{2, ...,} 51 _N are built in the substrate in a state that ends the wiring process by techniques previously only IC. A wiring region is provided adjacent to the circuit block region 51, and the signal input wiring group 53 and the signal output wiring group 5 intersect each other here.
2 are provided. Each signal input wiring 53 is directly connected to the signal input terminal of the circuit block. Each signal output wiring 52 is connected to a signal output terminal of the circuit block by a T-shaped wiring. Then, the signal output wiring group 52 and the signal input wiring group 5 in this wiring region
At each intersection of 3, there is provided a switch element 54 capable of electrically writing an ON / OFF state for connecting the signal output wiring and the signal input wiring. The switch element 54 is, for example, an E ² PROM or a MOSFET having a 1-bit memory.

According to this method, since the function of the chip is field programmable, the user can obtain a desired LSI having a high logic function remarkably quickly by manually writing the logic function by himself / herself. You can Moreover,
An LSI can be designed in a form in which an input signal and an output signal of a circuit block having a certain logic function are connected, and it is easy for a designer who is familiar with the logic design on the board to understand.

By the way, in this method, as described above, the switch element 54 is provided at each intersection of the signal output wiring group 52 and the signal input wiring group 53. One signal output wiring is MOSFE
FIG. 7 shows a state in which a large number of signal input wirings are connected via a switch element made of T. In this state, for example, consider a case where one MOSFET switch element is ON and all other switch elements are OFF. Even in this case, the diffusion layers of all switch elements along one signal output wiring are connected to this signal output wiring.Therefore, in addition to wiring capacitance, the diffusion layers of multiple switching elements are loaded on the signal output wiring. It is added as capacity. Therefore, if it is left as it is, the propagation delay time of the output signal of one circuit block to another circuit block becomes large, and the LSI
It will hinder the high speed operation.

[Object of the Invention]

In view of the above points, an object of the present invention is to provide a semiconductor integrated circuit in which the function of the chip is programmable, which enables high speed operation by reducing the propagation delay time in the output signal wiring.

[Outline of Invention]

The present invention is characterized in that a means for reducing the load capacity of the wiring is provided in the middle of each signal output wiring of the LSI in which the function of the chip is programmable by the switch matrix described above. For example, as a means for reducing the load capacitance, a buffer circuit, a switch element, or the like is inserted at one place in the middle of the signal output wiring or at a plurality of places if necessary.

〔The invention's effect〕

According to the present invention, it is possible to obtain an LSI having a programmable chip function, which shortens a signal propagation delay time and enables a high-speed logical operation by reducing a load capacitance of a signal wiring connecting circuit blocks. You can

Example of Invention

 Examples of the present invention will be described below.

FIG. 1 shows the configuration of one embodiment. As shown in the figure, a plurality of circuit blocks 11 ₁ , 11 ₂ ,
, 11 _N are formed to form the circuit block region 11. Each circuit block is a 4-input NAND
It is composed of one or more logic function elements such as a gate. This logic function element has, for example, a CMOS configuration,
It is a dedicated IC, that is, a handwritten standard cell in the standard cell system or a pre-wired gate array.

A specific configuration example of the circuit block area is as follows.

(1) Block with two 4-input NAND gates ...... 15 (2) Block with four 2-input NAND gates ...... 14 (3) Block with one 8-input NAND gate ...... 1 (4 ) Blocks with four inverters ...... 100 (5) Blocks of 8-bit registers ...... 19 (6) Blocks with two D-type flip-flops ...... 19 (7) Two 4-input AND gates Blocks with 17 (8) Blocks with 4 2-to-1 data selectors ...
... 13 (9) Blocks with two 4-bit binary counters ... 11 (10) Blocks with two 2-4 line decoders ...
7 (11) Block with 3-8 line decoder ...... 3 (12) Block with 2 4-1 selectors ...... 5 (13) Block with 8-1 selector ...... 4 (14) Blocks with 8-bit serial input-parallel input shift register …… 3 blocks (15) Blocks with 8-bit parallel input-serial output shift register …… 3 blocks (16) 8-bit serial input-direct output shift register Block: 2 blocks (17) Block with two monostable multivibrators
…… 4 pieces (18) Block with 4 2-input OR gates….
… 4 (19) Block with 4 2-input NOR gates
…… 3 (20) Block with two AND-OR inverters ……
3 blocks (21) 64-bit RAM block 3 blocks (22) 2 input EXCLUSIVE-OR gates with 4 blocks 2 blocks (23) 4-bit comparator block 3 blocks (24) J -A block with two K flip-flops ...
… 4 (25) 9-bit even / odd parity generator / checker block… 3 (26) 4-bit binary full adder block… 2
Number (27) Block with 4 2-input multiplexers 5 (28) Block with 4 SR latches 2 (29) ALU block 1 (30) 8-bit address Sable latch block ……
1 (31) Look-Ahead Carry Generator Block ...... One or more 274 circuit blocks consisting of MSI are formed in the circuit block area 11 so that an LSI of all functions can be created from one type of chip. It has become. Each circuit block has an average input number of 8 and an output number of 4. The input section and the output section of the logic function element are the input section and the output section of the circuit block, and the output section is provided with an output buffer (not shown). The output section is fixedly connected to the signal output wiring 32 so as to form a T-shaped path, and the input section is connected to the output wiring 3
2 are connected to the signal input wirings 33 that intersect with each other. A switch element 34 is provided at each intersection of the signal output wiring 32 and the signal input wiring 33.
The switch element 34 is, as described above, the E ² PROM or 1
A signal output wiring 3 such as a MOSFET with a bit memory, which electrically controls the switch element 34 from the outside.
2 and the signal input wiring 33 can be connected. That is, the connection of the input / output unit is basically one switch, and the equipotential wiring length associated with one current path is 2.5 l on average when the length of the side of the wiring region is 1.

Further, in this embodiment, a buffer circuit 35 is inserted at an intermediate position of each signal output wiring 32 as a means for reducing the load capacity of the wiring.

The manner of inserting the buffer circuit 35 into the single signal output wiring 32 is specifically shown in FIG. In FIG. 2, a switch 34 at the intersection of the signal output wiring 32 and the signal input wiring 33 is a MOSFET, and E is used as a buffer circuit 35 inserted in the middle of the signal output wiring 32.
An example is shown in which a / D type MOS inverter is connected in two stages.

According to this embodiment, a high-performance LSI in which the chip function is electrically programmable as in the case of the invention of the prior application can be obtained.

Further, according to this embodiment, the following effects can be obtained.
That is, regarding the half of the signal output wiring 32 on the input terminal side of the buffer circuit 35, the diffusion layer capacitance of the switch element 34 and the input stage gate capacitance of the buffer circuit 35 enter as load capacitance, but the output terminal of the buffer circuit 35 The diffusion layer capacitance of the switch element associated with the side wiring does not become a load. Therefore, the propagation delay time in the signal output wiring becomes short, and an LSI capable of high-speed operation can be obtained. Further, by inserting the buffer circuit 35, the drive capability for the subsequent wirings is increased. In particular, this effect becomes greater as the number of input / output lines increases as the density and integration are further advanced.

In FIG. 2, an E / D-structured inverter is used as the buffer circuit, but it is also possible to use another type of buffer circuit, such as a CMOS structure.

FIG. 3 shows the structure of another embodiment of the present invention in correspondence with FIG. The difference from FIG. 1 is that a switch element 36 serving as a transmission gate is used as the load capacitance reducing means inserted in the middle of the signal output wiring. In the case of the figure, a MOSFET is used as the switch element 36. This M
The gate terminal of the OSFET is derived from the outside as a control line 37 (37 ₁ , 37 ₂ , ...) For controlling ON / OFF.

With such a configuration, when the circuit block related to one signal output wiring is biased to the upper or lower part of the figure after the logic design, the switch element 36 is turned off. For example the output of the circuit blocks 11 ₁ as indicated by a thick line input to the circuit block 11 ₃ in FIG. 3, when the logic design to an output of the circuit block 11 ₃ to the circuit block 11 _1,
The signal output lines by the control lines 37 ₁ and 37 ₂ 32
The switch element 36 of is turned off. As a result, the unnecessary portion of the signal output wiring 32 can be substantially separated, and not only the wiring length can be reduced but also the capacitance of the switch element accompanying the unnecessary wiring can be prevented from entering as a load. it can. Therefore, similar to the previous embodiment, the delay of signal propagation is reduced to enable high-speed operation of the LSI.

FIG. 4 shows a structure of still another embodiment of the present invention in correspondence with FIG. In this embodiment, a tristate buffer circuit 38 is used as a load capacitance reducing means to be inserted at an intermediate position of the signal output wiring 32. The control terminals of these tri-state buffer circuits 38 are led out as control lines 39 (39 ₁ , 39 ₂ , ...) As in the previous embodiment. As is well known, the tri-state buffer circuit 38 has a high impedance output terminal when the control signal is OFF, and outputs the same logical value as the input when the control signal is ON.

With such a configuration, if the circuit block related to one signal output wiring is biased to the upper or lower side after the logic design as in the previous embodiment, the control line 39 causes a tristate.
The output of the buffer circuit 38 has high impedance. For example, when the output of the circuit block 11 ₁ is designed to be input to the circuit block 11 ₃ as shown by the bold line in FIG. 4, the control signal of the control line 39 ₁ is turned off. As a result, the lower half of the signal output wiring is separated as in the previous embodiment. Similarly, when the logic design is such that the output of the lowermost circuit block 11 _N is input to the uppermost circuit block 11 ₁ as indicated by the thick line, the control line 39 of the tristate buffer circuit of this signal output wiring is used. Turn on ₆
In the same manner as in the embodiment of FIG. 1, the unnecessary load capacity of the signal output wiring is reduced and at the same time the wiring driving capacity is increased.

Therefore, according to this embodiment as well, an LSI capable of operating at high speed with a reduced signal propagation delay can be obtained.

FIGS. 5A and 5B show still another embodiment. As the type and number of circuit blocks increase, the number of switch elements in the switch matrix becomes enormous. In order to reduce the number of switch elements, it is useful to make one circuit block into a so-called hierarchical structure, which is composed of a plurality of lower circuit blocks and a switch matrix. FIGS. 5 (a) and 5 (b) apply the present invention to such a case. That is, the circuit block 11 ₁ shown in FIG.
11 _2, ... the figure, respectively, as shown in (b) further plurality of sub-blocks 111, 112, 113, are configured ... as a set of switching matrix 42 for formation between these respective circuits Blocks 11 ₁ , 11 ₂ , ...
Of the lower switch matrix 42, so to speak, the input / output of the lower switch matrix 42 is formed in the area of the upper switch matrix 41.
It will be connected by. In the programmable LSI having such a configuration, in this embodiment,
The lower switch matrix 42 and the upper switch matrix 4 in each circuit block 11 ₁ , 11 ₂ , ...
A buffer circuit 43 for reducing the load capacitance of the wiring is inserted in the connection portion between the two.

Also in this embodiment, the same effect as the previous embodiment can be obtained. It is also useful to use the buffer circuit 43 of this embodiment as a switch element as in the embodiment of FIG. 3 or as a tri-state buffer as in the embodiment of FIG.

The present invention is not limited to the above embodiments. For example, in the case of an LSI with higher density and higher functionality, it is also effective to insert the load capacitance reducing means as shown in each embodiment at a plurality of positions of one signal output wiring.

[Brief description of drawings]

FIG. 1 is a diagram showing an LSI configuration of one embodiment of the present invention, and FIG.
FIG. 4 is a diagram showing a specific configuration of one of the signal output wiring portions, FIG. 3 is a diagram showing an LSI configuration of another embodiment, and FIG.
FIG. 5 is a diagram showing an LSI configuration of yet another embodiment, and FIGS. 5A and 5B are diagrams showing an LSI configuration of yet another embodiment.
FIG. 6 is a diagram showing an LSI configuration according to a prior application which is the basis of the present invention, and FIG. 7 is a diagram showing elements connected to signal output wirings through a number of switch elements. 11 ₁ , 11 ₂ , ..., 11 _N ... Circuit block, 32 ...
… Signal output wiring, 33 …… Signal input wiring, 34 ……
Switch element, 35 ... Buffer circuit (load capacity reducing means), 36 ... Switch element (load capacity reducing means), 3
7 ... Control line, 38 ... Tri-state buffer circuit (load capacity reducing means), 39 ... Control line, 41 ... Upper switch matrix,
42 ... Lower switch matrix, 43 ... Buffer circuit (load capacity reducing means).

Claims (4)

[Claims] 1. A plurality of circuit blocks, each having a logical function itself and having a signal input portion and a signal output portion, which are built in a substrate, and adjacent to a circuit block region formed by the plurality of circuit blocks. And a wiring region formed on the substrate, the circuit block region is composed of a set of a plurality of types of logic function elements, and the wiring region includes a signal input wiring group and a signal output wiring group that intersect with each other. The signal input wiring group is connected to the signal input section of each circuit block, the signal output wiring group is connected to the signal output section of each circuit block, and these connections are connected to the circuit block. Is performed in the wiring regions adjacent to each other, switch elements are respectively provided at intersections of the signal input wiring group and the signal output wiring group,
By controlling the ON / OFF state of the switch element, the input / output relationship between the respective circuit blocks is determined and a desired integrated circuit is constructed, and wiring is provided in the middle of each of the signal output wiring groups. A semiconductor integrated circuit comprising means for reducing load capacity. 2. The semiconductor integrated circuit according to claim 1, wherein the means for reducing the load capacitance of the wiring is a buffer circuit. 3. The semiconductor integrated circuit according to claim 1, wherein the means for reducing the load capacitance of the wiring is a switch element. 4. The semiconductor integrated circuit according to claim 1, wherein the means for reducing the load capacitance of the wiring is a tristate buffer circuit.