JPH06176578A - Semiconductor memory - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a semiconductor memory having a small chip area without impairing high speed. A bit line drive circuit BD0 is provided for each bit line, a power supply voltage of a memory cell is set to be lower than a power supply voltage of a chip, and the bit line drive circuit BD0 has a first emitter connected to a bit line pair. And the second bipolar transistors QPU0 and QPU1, the drains of which are connected to a pair of bit lines and the gates of which are applied with a DC voltage.
First and second bipolar transistors QPU0, QP including channel MOS transistors MCLO, MCL1
Control circuit CNT for generating a signal to be applied to the base of U1
L is shared by a plurality of bit line drive circuits BD0 and BD1. [Effect] The number of elements forming the bit line driving circuit can be significantly reduced as compared with the conventional case.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory having a small chip area.

[0002]

2. Description of the Related Art As a method for realizing a highly integrated and high-speed memory, BiCMOS technology for integrating a bipolar transistor and a MOS transistor on the same chip has been proposed. As a memory to which this technique is applied, for example, there is one described in Japanese Patent Laid-Open No. 3-76096. FIG. 2 shows a circuit diagram of the semiconductor memory described in the above patent publication. In this conventional technique, a voltage V _E (about −2 V) that is smaller than the power supply voltage of the memory chip is applied to the memory cell.
Is applied, the drive amplitude of the word line and the bit line is reduced, and the speed is increased. Further, since the drive amplitude of the word line and the bit line is reduced, the word line drive circuit and the bit line drive circuit can be configured by the ECL circuit, and the speed can be greatly increased. The operation of this circuit will be described below with reference to FIG. W0 is the word line,
B00 to B11 are bit lines, and C00 and C01 are memory cells. BD0 and BD1 are bit line drive circuits,
The bit line is driven to an appropriate potential according to the read and write states. S0 is a sense circuit, and OB is an output circuit. V _E is the power supply potential of the memory cell and is set to about -2V. First, the read operation will be described.
Now, it is assumed that the word line drive signal XS0 has a high potential, the bit line selection signal YS0 has a high potential, and the memory cell C00 is selected. At this time, in order to read the information of the memory cell C00, both write data signals DB0 and DB1 are set to Y.
Drive to a potential higher than S0. As a result, the current source IY
0, IY1, IW0, IW1 current is the transistor QD
Flow from B0, QDB1, pull-up transistor QP
Both the bases of U0 and QPU1 have a high potential, and the potentials of bit lines B00 and B01 both have a high potential. At this time, depending on the information stored in the memory cell C00, QP
The memory cell current and the bias current (IB0 or IB1) flow in either one of U0 and QPU1, and only the bias current flows in the other. Therefore, the bit line B
00 and B01 generate a potential difference of about several tens of mV. This potential difference is amplified by the differential amplifier circuit S0 composed of the bipolar transistors QA0 and QA1 and passed through the output circuit OB.
A data output signal DO is obtained. Next, consider the write operation. As in the previous case, it is assumed that the memory cell C00 is selected. To write information in the memory cell, one of the write data signals DB0 and DB1 is driven to a potential lower than that of the bit line selection signal YS0 according to the information to be written. Now, for example, consider the case where the write data signal DB0 is driven to a low potential. In this case, the current source IW0,
The current IY0 flows from the transistors QW0 and QY0. As a result, the base of the pull-up transistor QPU0 is driven to a low potential and at the same time, the current source I is supplied to the bit line.
A current due to W0 flows, and the bit line B00 is driven to a low potential. As a result, the potential of the bit line is transmitted to the selected memory cell C00 and writing is performed. After the information is completely written in the memory cell, the write data signal DB0 is returned to the high potential. As a result, the current sources IW0, IW0
The current of Y0 flows from the transistor QDB0, the current due to the current source IW0 stops flowing to the bit line, and at the same time the base of the pull-up transistor QPU0 is driven to a high potential, and the bit line B00 returns to a high potential, that is, the read state, Writing is completed. The capacitors CY0 and CY1 connected to the bases of the pull-up transistors QPU0 and QPU1 have a role of preventing overshoot when the bit line is pulled up from a low potential to a high potential.

[0003]

However, this prior art has a problem that the occupied area is large because the number of elements forming the bit line drive circuit BD0 is large. Therefore, an object of the present invention is to provide a semiconductor memory having a small chip area without impairing high speed.

[0004]

In order to achieve the above object, a typical embodiment of the present invention comprises a plurality of word lines,
A plurality of bit line pairs, a memory cell arranged at an intersection of the plurality of word lines and the plurality of bit lines, and a bit line driving circuit for driving the bit line pairs according to reading and writing for each bit line. And a semiconductor memory in which the power supply voltage of the memory cell is set to be lower than the power supply voltage of the chip, the bit line drive circuit includes first and second bipolar transistors having emitters connected to the bit line pair. , First and second P-channel MOS transistors having drains connected to the bit line pair and a DC voltage applied to the gates
A control circuit including a transistor and generating a signal to be applied to the bases of the first and second bipolar transistors is shared by a plurality of bit line drive circuits.
A bit line driving circuit according to a more preferred embodiment of the present invention has a collector connected to the bit line pair, and a current is supplied to the bit line pair according to a signal input to a base or an emitter. , And a fourth bipolar transistor. Further, another preferred embodiment of the present invention is characterized in that a resistor is connected instead of the P-channel MOS transistor. In another preferred embodiment of the present invention, bit line pairs whose positions are replaced by even-numbered places in the memory cell array and bit line pairs whose positions are replaced by odd-numbered places in the memory cell array are alternated. It is characterized in that it is arranged and means for lowering the impedance between the bit line pair is provided.

[0005]

With the above arrangement, the number of elements forming the bit line drive circuit can be greatly reduced as compared with the prior art.
Further, since the bit line is driven by the bipolar transistor, the high speed of the conventional technique is not impaired. Therefore, it is possible to provide a semiconductor memory having a small chip area without impairing high speed. Other objects and features of the present invention will be apparent from the following examples.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a first embodiment of the present invention. In the prior art, pull-up transistors QPU0 and QPU are used.
A circuit for controlling the base potential of 1 (resistors RY0, RY1,
Although the transistors QY0 and QY1 and the capacitors CY0 and CY1) are provided for each bit line drive circuit, in the present invention, the bases of the pull-up transistors QPU0 and QPU1 of the bit line drive circuits BD0 and BD1 are commonly connected, It is controlled by a common control circuit CNTL. This allows
The number of elements forming the bit line drive circuit can be significantly reduced, and the occupied area can be reduced. The bit line drive circuit BD0 of this embodiment includes transistors QW0 and QW1 that control the bit line discharge currents IW0 and IW1 and transistors QPU0 and QPU1 that charge the bit line. CL0 and CL1 are clamp circuits that prevent the potential of the non-selected bit lines from decreasing during writing. The signals DA0, DB0 and DA1, DB1 are signals of the same logic and differ only in potential. For example, the high potential and the low potential of DA0 and DA1 are -0.8V and -1.7, respectively.
V0, DB0 and DB1 are -2.2V,-
It is set to 2.8V. The operation of this circuit will be described below.

First, the read operation will be described.
Now, it is assumed that the word line drive signal XS0 has a high potential, the bit line selection signal YS0 has a high potential, and the memory cell C00 is selected. At this time, in order to read information from the memory cell C00, both the signals DB0 and DB1 are driven to a high potential.
As a result, the currents of the current sources IW0 and IW1 flow from the transistors QDB0 and QDB1. Furthermore, the signal DA0,
Both DA1 are also driven to a high potential. As a result, the bases of the pull-up transistors QPU0 and QPU1 are both at high potential, and the potentials of the bit lines B00 and B01 are both at high potential. At this time, depending on the information stored in the memory cell C00, the memory cell current and the bias current (IB0, or
IB1) flows, and only the bias current flows to the other.
Therefore, a potential difference of about several tens of mV is generated between the bit lines B00 and B01. This potential difference is amplified by the differential amplifier circuit S0 including the bipolar transistors QA0 and QA1, and the data output signal DO is obtained through the output circuit OB.

Next, the write operation will be considered. As in the previous case, it is assumed that the memory cell C00 is selected. To write information in the memory cell, one of the signals DA0 and DB0 or DA1 and DB1 is driven to a low potential depending on the information to be written. Now, for example, the signals DA0, DB0
Consider the case where is driven to a low potential. In this case, the base of the pull-up transistor QPU0 is driven to a low potential, and at the same time, the current of the current source IW0 flows through the bit line B00, so that the bit line B00 is driven to a low potential. As a result, the memory cell C00 in which the potential of the bit line is in the selected state
Is transmitted to and writing is performed. After the information is completely written in the memory cell, the signals DA0 and DB0 are returned to the high potential. As a result, the current of the current source IW0 is
The current flows from DB0 and the current due to the current source IW0 stops flowing to the bit line, and at the same time, the pull-up transistor QPU0
Is driven to a high potential, the bit line B00 returns to a high potential, that is, the read state, and the writing is completed.

In the present invention, since the bases of the pull-up transistors of the plurality of bit line driving circuits are commonly connected, if the signal DA0 is set to a low potential at the time of writing, the bit line driving circuit in the non-selected state, for example, , BD1 also has a low potential at the base of the pull-up transistor, and the potential of the non-selected bit line, for example, B10 is lowered, which may cause a malfunction. To prevent this, clamp circuits CL0 and CL1 are provided. Clamp circuit is a pair of P
The equivalent resistance of the P-channel MOS transistor constituted by the channel MOS transistors MCLO and MCL1 hardly lowers the potential of the bit line with the current (normally about 0.1 mA) flowing through the non-selected bit line, and the bit line discharge current IW0. , IW1 (usually about 2 to 3 mA) is set to a value such that the bit line potential is sufficiently lowered. As a result, even if the base of the pull-up transistor of the bit line drive circuit in the non-selected state is driven to the low potential, the potential of the bit line is clamped to the high potential and the malfunction can be prevented. A DC voltage is applied to the gates of the P-channel MOS transistors MCL0 and MCL1 of the clamp circuit so that they are always activated. This eliminates the need for a timing margin between the control signal of the clamp circuit and the write signal, thus shortening the write cycle time. Also, here, the clamp circuit is a P channel M
Although an example in which it is configured by an OS transistor is shown, the same configuration can be achieved by using a resistor. As described above, in this embodiment, as in the prior art, the bit line is charged and discharged by the bipolar transistor, so that the high speed is not impaired as compared with the prior art. Moreover, since the number of constituent elements can be significantly reduced, a semiconductor memory having a small chip area can be realized.

As the wiring interval in a chip becomes smaller as the memory chip becomes more highly integrated, the parasitic capacitance between the wires sharply increases. For this reason, it is an important design issue to reduce crosstalk noise from adjacent wirings in a highly integrated memory. Especially the read signal of bit line is several tens of meters
Since it is as small as V, it is easily affected by noise. The embodiment shown in FIG. 3 solves this problem. In this example,
In the embodiment of FIG. 1, crosstalk noise reduction circuits NR0, N
R1 is added and bit line pairs are crossed. The noise reduction circuit NR0 is composed of a P-channel MOS transistor MNR0 connected between bit lines and works to reduce the impedance between bit lines. As a result, crosstalk noise between the bit lines B00 and B01 can be reduced. Also, by crossing the bit lines,
Wiring capacitance between adjacent bit line pairs, eg, bit line B0
The capacitance between 1 and B10 can be reduced to 1/4 of that in the embodiment of FIG. 1, and noise can be reduced. In addition, P channel MOS
The gate potential of the transistor MNR0 is set so that the impedance of MNR0 has an appropriate value. Here, an example using a P-channel MOS transistor is shown as a means for lowering the impedance between bit lines, but a resistor may be used instead.

The bias potential VB of the clamp circuits CL0 and CL1 is the bit line potential V without the clamp circuit.
It is necessary to set it almost equal to the bit. The reason for this will be described below. If VB is set too high, the bit line potential becomes high, so the bit line drive amplitude during writing increases,
There is a problem that the time required for writing increases. On the other hand, V
_{If B} is set too low, a current flows from the bit line to the P-channel MOS transistors MCL0 and MCL1, so that the amplitude of the read signal on the bit line is reduced and the information in the memory cell cannot be read. Therefore, V _B
Should be set approximately equal to Vbit. FIG. 4 shows an example of a V _B generating circuit that satisfies this condition.

In this embodiment, dummy memory cells and bit lines are provided, and the bit line potential is output via the voltage follower. This allows V _B to be set equal to V bit. Here, as the dummy cell DC, one in which the input terminals of the two inverters forming the memory cell are connected to the ground potential and V _E , respectively, is used. The high potential of the word line drive signal is applied to the dummy word line DW,
The dummy memory cell DC is brought into a selected state. Further, the noise reduction circuit DNR and the sense circuit DS are connected to the dummy bit lines DB0 and DB1 just like the normal bit lines.
The dummy bit line drive circuit DBD includes a transistor QDP
It is composed of U0 and QDPU1, and the high potentials of the signals DA0 and DA1 are applied to their bases. With such a configuration, the potentials of the dummy bit lines DB0 and DB1 become equal to the potential of the normal bit line. If this is output via the voltage follower VF, the desired V _B can be obtained. It should be noted that the reason why the voltage is output via the voltage follower is to reduce the output impedance of the V _B generating circuit.

[0013]

As described above, according to the present invention, a semiconductor memory having a small chip area can be provided without impairing the high speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional technique.

FIG. 3 is a circuit diagram of a semiconductor memory according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration example of a power supply circuit for generating V _B used in an embodiment of the present invention.

[Explanation of symbols]

C00, C01 ... Memory cells, B00, B01, B1
0, B11 ... Bit line, W0 ... Word line, CL0, CL
1 ... Clamp circuit, S0, S1 ... Sense circuit, BD0,
BD1 ... Bit line drive circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical display location 6741-5L G11C 11/34 354 D (72) Inventor Kazuo Kanaya 1-280, Higashi-Kengokubo, Kokubunji, Tokyo Central Research Laboratory, Hitachi, Ltd. (72) Hiroaki Nanbu, 1-280, Higashi Koikeku, Kokubunji, Tokyo Metropolitan Research Laboratory, Hitachi, Ltd. (72) Yoji Ide, 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Takeshi Kusunagi 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd.

Claims (4)

[Claims] 1. A plurality of word lines, a plurality of bit line pairs,
Each memory cell is provided with a memory cell arranged at an intersection of the plurality of word lines and the plurality of bit lines, and a bit line drive circuit for driving the bit line pair according to reading and writing, and the memory In a semiconductor memory in which a cell power supply voltage is set to be lower than a chip power supply voltage, the bit line drive circuit includes first and second bipolar transistors having emitters connected to the bit line pair, and a drain having the bit line pair. A control circuit for generating a signal to be applied to the bases of the first and second bipolar transistors, the control circuit including a first and a second P-channel MOS transistors each having a gate applied with a DC voltage. A semiconductor memory that is shared by circuits. 2. A bit line driving circuit, wherein a collector is connected to the bit line pair, and a current is supplied to the bit line pair according to a signal input to a base or an emitter.
The semiconductor memory according to claim 1, further comprising a fourth bipolar transistor. 3. The semiconductor memory according to claim 1, wherein a resistor is connected instead of the P-channel MOS transistor. 4. A pair of bit lines whose positions are interchanged in even numbers in the memory cell array and a pair of bit lines whose positions are interchanged in odd numbers in the memory cell array, and which are alternately arranged. 4. The semiconductor memory according to claim 1, further comprising means for reducing an impedance between them.