JPH06177268A - Fabrication of semiconductor device - Google Patents

Fabrication of semiconductor device

Info

Publication number
JPH06177268A
JPH06177268A JP4326933A JP32693392A JPH06177268A JP H06177268 A JPH06177268 A JP H06177268A JP 4326933 A JP4326933 A JP 4326933A JP 32693392 A JP32693392 A JP 32693392A JP H06177268 A JPH06177268 A JP H06177268A
Authority
JP
Japan
Prior art keywords
resin film
semiconductor chip
package
semiconductor device
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4326933A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Yoneda
義之 米田
Kazuto Tsuji
和人 辻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4326933A priority Critical patent/JPH06177268A/en
Publication of JPH06177268A publication Critical patent/JPH06177268A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】 【目的】 プラスチックパッケージを有する半導体装置
の製造方法に関し、捺印の視認性が良好で、かつ、生産
性を向上した半導体装置の製造方法を提供することを目
的とする。 【構成】 モールド金型16a,16bに保持ピン17
を設け、保持ピン17により放熱板12の半導体チップ
11の非搭載面を保持しつつ、樹脂モールドすることに
より放熱板12の非搭載面に樹脂膜14aを形成し、レ
ーザビームLにより樹脂膜14aを除去することにより
パターン19をマーキングする。
(57) [Abstract] [PROBLEMS] To provide a method for manufacturing a semiconductor device having a plastic package, which has good marking visibility and improved productivity. [Structure] Holding pins 17 are provided on the molding dies 16a and 16b.
Is provided, and while holding the non-mounting surface of the semiconductor chip 11 of the heat sink 12 by the holding pin 17, a resin film 14a is formed on the non-mounting surface of the heat sink 12 by resin molding, and the resin film 14a is formed by the laser beam L. The pattern 19 is marked by removing.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
係り、特に、プラスチックパッケージを有する半導体装
置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a plastic package.

【0002】半導体装置にはパッケージに社票や型格、
ロット番号等が捺印されており、これらの捺印により内
蔵されている集積回路を識別している。従って、これら
の捺印は視認性が良好である必要がある。
A semiconductor device has a package with a company name, model number,
Lot numbers and the like are stamped, and these stamps identify the integrated circuit contained therein. Therefore, these markings need to have good visibility.

【0003】[0003]

【従来の技術】従来の半導体装置では社票や型格、ロッ
ト番号等をパッケージに捺印する場合、インクにより、
マーキングが行なわれていた。
2. Description of the Related Art In the conventional semiconductor device, when printing a company slip, model number, lot number, etc. on a package,
The marking was done.

【0004】図11は従来の一例の斜視図を示す。同図
中、1は樹脂パッケージで樹脂パッケージ1の表面から
は放熱板2が露出しており、いわゆる低熱抵抗プラスチ
ックパッケージを構成している。放熱板2は銅(Cu)
やアルミニウム(Al)により構成されており、放熱板
2上にパターン3がインクにより捺印されていた。
FIG. 11 shows a perspective view of a conventional example. In the figure, reference numeral 1 denotes a resin package in which the heat dissipation plate 2 is exposed from the surface of the resin package 1 and constitutes a so-called low thermal resistance plastic package. The heat sink 2 is copper (Cu)
And the pattern 3 was imprinted on the heat dissipation plate 2 with ink.

【0005】[0005]

【発明が解決しようとする課題】しかるに、従来のイン
クによる捺印ではインクの塗布後、インクをパッケージ
表面に定着させるための処理が必要となり、製造工程が
増加し、生産性が悪い。
However, the conventional marking with ink requires a process for fixing the ink on the surface of the package after the ink is applied, resulting in an increase in the number of manufacturing steps and poor productivity.

【0006】また、レーザビームによるプラスチックパ
ッケージに捺印では放熱板が剥きだしになっているいわ
ゆる低熱抵抗プラスチックパッケージに用いる場合、放
熱板にパターンをマーキングすること、リードへの半田
メッキ時に放熱板にも半田がメッキされているため、半
田にパターンがマーキングされ、半導体装置の実装時に
半田溶融温度を大きく越えることによりパターンが消去
されてしまう。このため、放熱板以外の部分にマーキン
グする必要があり、マーキング位置が規制されてしま
う。さらに、樹脂パッケージ上にレーザビームを照射
し、マーキングを行ってもレーザビームによるマーキン
グの色は黒っぽく、樹脂パッケージの色もカーボンによ
り黒色となっており、コントラストが低いため視認性が
悪い等の問題点があった。
In addition, when used in a so-called low thermal resistance plastic package in which a heat sink is exposed in marking a plastic package by a laser beam, marking a pattern on the heat sink, and also on the heat sink at the time of lead plating with solder. Since the solder is plated, a pattern is marked on the solder, and the pattern is erased when the solder melting temperature is greatly exceeded when the semiconductor device is mounted. Therefore, it is necessary to mark the portion other than the heat sink, and the marking position is restricted. Further, even if the resin package is irradiated with a laser beam for marking, the marking color by the laser beam is dark, and the resin package color is also black due to carbon, which causes poor visibility due to low contrast. There was a point.

【0007】本発明は上記の点に鑑みてなされたもの
で、捺印の視認性が良好で、かつ生産性の良好な半導体
装置の製造方法を提供することを目的とする。
The present invention has been made in view of the above points, and it is an object of the present invention to provide a method of manufacturing a semiconductor device which has good visibility of a marking and high productivity.

【0008】[0008]

【課題を解決するための手段】本発明は半導体チップ及
び該半導体チップで生じる熱を放熱する放熱板を該半導
体チップを外部と接続するリードと共に樹脂製のパッケ
ージで一体的にモールドしてなる半導体装置の製造方法
において、前記放熱板表面に樹脂膜を形成する樹脂膜形
成工程と、前記樹脂膜を熱線により局所的に除去し、前
記放熱板を局所的に剥き出すことにより捺印を行なう捺
印工程とを有してなる。
SUMMARY OF THE INVENTION The present invention is a semiconductor in which a semiconductor chip and a heat radiating plate for radiating heat generated in the semiconductor chip are integrally molded in a resin package with leads for connecting the semiconductor chip to the outside. In the method of manufacturing a device, a resin film forming step of forming a resin film on the surface of the heat dissipation plate, and a marking step of locally removing the resin film with a heat ray and locally exposing the heat dissipation plate for imprinting. And have.

【0009】[0009]

【作用】放熱板表面に樹脂膜が形成され、熱線により樹
脂膜を局所的に除去することにより、放熱板を表出さ
せ、パターンをマーキングする。
The resin film is formed on the surface of the heat sink, and the resin film is locally removed by heat rays to expose the heat sink and mark the pattern.

【0010】このため、樹脂膜と放熱板との材質の違い
によりパターンと他の部分とのコントラストを大きくす
ることができ、パターンの視認性を向上させることがで
きる。
Therefore, the contrast between the pattern and other portions can be increased due to the difference in material between the resin film and the heat dissipation plate, and the visibility of the pattern can be improved.

【0011】また、放熱板はほとんどが樹脂膜で覆われ
るため、放熱板を保護できる。このとき、樹脂膜は20
〜50μm と非常に薄いため放熱板の放熱効果を阻害す
ることはない。
Further, since most of the heat sink is covered with the resin film, the heat sink can be protected. At this time, the resin film is 20
Since it is very thin up to 50 μm, it does not interfere with the heat dissipation effect of the heat dissipation plate.

【0012】[0012]

【実施例】図1は本発明の第1実施例の製造工程図を示
す。同図中、11は半導体チップ、12は放熱板、13
はリードフレーム、14はパッケージを示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a manufacturing process diagram of a first embodiment of the present invention. In the figure, 11 is a semiconductor chip, 12 is a heat sink, and 13
Indicates a lead frame, and 14 indicates a package.

【0013】半導体チップ11は例えば、数mm角のシリ
コン結晶基板上に高集積精密度の回路素子を多数形成し
てなる。放熱板12は銅(Cu)、アルミニウム(A
l)、セラミック等の熱伝導の良好な材料を平板状に形
成してなる。
The semiconductor chip 11 is formed, for example, by forming a large number of highly integrated circuit elements on a silicon crystal substrate of several mm square. The heat sink 12 is made of copper (Cu), aluminum (A
l), a material such as ceramic having good heat conduction is formed in a flat plate shape.

【0014】リードフレーム13は銅(Cu)合金、鉄
(Fe)−ニッケル(Ni)合金(例えば42アロイ)
等の材料をエッチングやプレス加工することにより形成
される。パッケージ14はエポキシ系の樹脂材料よりな
り、半導体チップ11,放熱板12,リードフレーム1
3の一部を一体的に封入する。
The lead frame 13 is made of copper (Cu) alloy, iron (Fe) -nickel (Ni) alloy (for example, 42 alloy).
It is formed by etching or pressing a material such as. The package 14 is made of an epoxy resin material, and includes a semiconductor chip 11, a heat sink 12, and a lead frame 1.
Part of 3 is enclosed integrally.

【0015】リードフレーム13は接続リード13a及
び支持リード13bを有し、放熱板12は支持リード1
3bにより保持される。図2に本発明の第1実施例の放
熱板12と支持リード13bとの接続部分の斜視図を示
す。放熱板12には半導体チップ11の搭載面12aに
凸部12a-1が形成されていて、この凸部12a-1に支
持リード13bの先端部に形成された穴部13b-1を係
合させ、凸部12a-1をかしめることにより放熱板12
を支持リード13bに保持する構成とされている。
The lead frame 13 has a connecting lead 13a and a supporting lead 13b, and the heat sink 12 is a supporting lead 1.
Held by 3b. FIG. 2 shows a perspective view of a connecting portion between the heat dissipation plate 12 and the support lead 13b according to the first embodiment of the present invention. The heat sink 12 has a convex portion 12a-1 formed on the mounting surface 12a of the semiconductor chip 11. The convex portion 12a-1 is engaged with a hole 13b-1 formed at the tip of the support lead 13b. , The heat sink 12 by caulking the convex portion 12a-1
Is held by the support lead 13b.

【0016】放熱板12は支持リード13bに保持され
た後、半導体チップ11の搭載面12aに半導体チップ
11が接着剤等により接着される。次に半導体チップ1
1と接続リード13aとがワイヤボンディングされ、金
(Au)材よりなるワイヤ15により接続され、図1
(A)に示すような状態とされる。
After the heat dissipation plate 12 is held by the support leads 13b, the semiconductor chip 11 is bonded to the mounting surface 12a of the semiconductor chip 11 with an adhesive or the like. Next, semiconductor chip 1
1 and the connection lead 13a are wire-bonded and connected by a wire 15 made of a gold (Au) material.
The state is as shown in FIG.

【0017】次に図1(A)に示すように一体的に形成
された半導体チップ11、放熱板12,リードフレーム
13を図1(B)に示すようにモールド金型16a,1
6b内に収納する。モールド金型16b底面には装脱可
能に構成され、放熱板12の半導体チップ11の非搭載
面12bを保持する保持ピン17が装着されている。保
持ピン17は底面からの突出量が20〜50μ程度に設
定され、モールド金型16bの底面から20〜50μの
位置で放熱板12を保持する。
Next, as shown in FIG. 1 (A), the semiconductor chip 11, the heat dissipation plate 12, and the lead frame 13 which are integrally formed are molded into molds 16a, 1 as shown in FIG. 1 (B).
Store in 6b. A holding pin 17 that is configured to be attachable / detachable and that holds the non-mounting surface 12b of the semiconductor chip 11 of the heat dissipation plate 12 is attached to the bottom surface of the molding die 16b. The amount of protrusion of the holding pin 17 from the bottom surface is set to about 20 to 50 μ, and holds the heat dissipation plate 12 at a position of 20 to 50 μ from the bottom surface of the molding die 16b.

【0018】放熱板12はモールド金型16a,16b
内に保持されると支持リード13bの弾性により矢印A
方向に押圧され、保持ピン17に密着する。以上により
モールド金型16bの底面と放熱板12の半導体チップ
11の非搭載面12bとの間に20〜50μの間隙が確
実に保持される。
The heat radiating plate 12 is a mold die 16a, 16b.
When held inside, the elasticity of the support lead 13b causes arrow A
It is pressed in the direction and comes into close contact with the holding pin 17. As described above, a gap of 20 to 50 μ is reliably held between the bottom surface of the molding die 16b and the non-mounting surface 12b of the semiconductor chip 11 of the heat dissipation plate 12.

【0019】次に、モールド金型16a,16b内にエ
ポキシ系樹脂を注入する。樹脂が略固着した後に保持ピ
ン17を引き貫くことにより樹脂製パッケージ14が形
成される。
Next, epoxy resin is injected into the molding dies 16a and 16b. The resin package 14 is formed by penetrating the holding pin 17 after the resin is substantially fixed.

【0020】以上の工程により図1(C)に示すように
パッケージ14には保持ピン17により凹部14bが形
成されると共に、放熱板12の半導体チップ11の非搭
載面12bには20〜50μm の薄い樹脂膜14aが形
成される。
Through the above steps, as shown in FIG. 1C, the recess 14b is formed in the package 14 by the holding pin 17, and the non-mounting surface 12b of the semiconductor chip 11 of the heat sink 12 has a thickness of 20 to 50 μm. A thin resin film 14a is formed.

【0021】次にリード13のパッケージ14より外方
に延出したアウタリード13a-1部分に半田メッキが行
なわれ、その後、樹脂膜14a上に図1(D)に示すよ
うにレーザ発生装置18よりレーザ光Lが捺印しようと
する文字、数字に応じて照射される。レーザ光Lは数m
W程度の出力を有し、レーザ光Lが照射された部位14
a-1では樹脂膜14aが蒸発し、樹脂膜14a下部の放
熱板12が表出する。
Next, the outer lead 13a-1 portion of the lead 13 extending outward from the package 14 is solder-plated, and then the resin film 14a is formed by the laser generator 18 on the resin film 14a as shown in FIG. 1 (D). The laser light L is emitted according to the letters and numbers to be imprinted. Laser light L is several meters
A portion 14 having an output of about W and irradiated with laser light L
At a-1, the resin film 14a evaporates, and the heat dissipation plate 12 below the resin film 14a appears.

【0022】レーザ光Lを社票、ロット番号等の捺印す
べき文字、数字等に応じて樹脂膜14aに照射すること
により捺印すべき文字、数字等に応じて樹脂膜14aが
除去され、放熱板12が表出し、社票、ロット番号等の
捺印が行なわれる。
By irradiating the resin film 14a with the laser beam L according to the letters, numbers, etc. to be stamped such as a company slip, lot number, etc., the resin film 14a is removed in accordance with the letters, numbers, etc. to be stamped, and heat is radiated. The board 12 is exposed, and a company slip, a lot number, etc. are stamped.

【0023】捺印完了後、図1(D)に示すようにリー
ドフレームより切断し、接続リード13aの先端を折曲
することにより半導体装置が完成する。本実施例では接
続リード13aの先端を表面実装用に折曲している。
After the marking is completed, the semiconductor device is completed by cutting from the lead frame and bending the tips of the connecting leads 13a as shown in FIG. 1 (D). In this embodiment, the tips of the connection leads 13a are bent for surface mounting.

【0024】図3は上記の製造工程により製造された半
導体装置の斜視図を示す。図1の工程により製造された
半導体装置によれば、捺印されたパターン19は放射板
12の色となり、カーボンが混入された樹脂よりなるパ
ッケージ14の色とのコントラストによりはっきりと視
認することができるため、捺印された社票、ロット番号
の視認性を向上させることができる。
FIG. 3 is a perspective view of a semiconductor device manufactured by the above manufacturing process. According to the semiconductor device manufactured by the process of FIG. 1, the imprinted pattern 19 has the color of the radiation plate 12 and can be clearly recognized by the contrast with the color of the package 14 made of resin mixed with carbon. Therefore, the visibility of the stamped company slip and lot number can be improved.

【0025】また、放熱板12上はパターン19及び穴
部14b以外は樹脂膜14aで覆われるため、放熱板1
2を保護できる。さらに、放熱板12上に形成される樹
脂膜14aは20〜50μm と薄いと共に樹脂膜14a
の形成時に形成された穴部14b及びパターン19によ
り、放熱板12の放熱効果を阻止することはない。
Since the heat radiation plate 12 is covered with the resin film 14a except the pattern 19 and the hole 14b, the heat radiation plate 1
2 can be protected. Further, the resin film 14a formed on the heat dissipation plate 12 is as thin as 20 to 50 .mu.m and the resin film 14a is
The hole 14b and the pattern 19 formed at the time of forming do not prevent the heat dissipation effect of the heat dissipation plate 12.

【0026】図4は本発明の第2実施例の製造工程図を
示す。同図中、図1と同一構成部分には同一符号を付
し、その説明は省略する。
FIG. 4 shows a manufacturing process diagram of the second embodiment of the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

【0027】本実施例は第1実施例と放熱板の形状が異
なる。図5に第2実施例の放熱板の斜視図を示す。
This embodiment differs from the first embodiment in the shape of the heat sink. FIG. 5 shows a perspective view of the heat sink of the second embodiment.

【0028】放熱板21には凸部21aがプレスや削出
し等の加工法により形成される。凸部21aは高さが2
0〜50μm に形成されている。
A convex portion 21a is formed on the heat dissipation plate 21 by a processing method such as pressing or shaving. The height of the convex portion 21a is 2
The thickness is 0 to 50 μm.

【0029】放熱板21は図4(A)に示すように第1
実施例と同様な方法でリード13に保持され、凸部21
aを有する面が半導体チップ11の非搭載面となるよう
に組み付けられる。
The heat radiating plate 21 has a first
The protrusions 21 are held by the leads 13 in the same manner as in the embodiment.
It is assembled such that the surface having a is the non-mounting surface of the semiconductor chip 11.

【0030】次に、図4(B)に示すように第1実施例
のモールド金型16a,16bの保持ピン16b-1を削
除したモールド金型22a,22b内に保持され、樹脂
が注入され、パッケージ14が形成される。
Next, as shown in FIG. 4B, the molds 16a and 16b of the first embodiment are held in the molds 22a and 22b from which the holding pins 16b-1 are removed, and the resin is injected. , The package 14 is formed.

【0031】このとき、放熱板21の凸部21aはモー
ルド金型21bの底面にリード13の弾性により押圧さ
れる。このため、放熱板21の半導体チップ11の非搭
載面の凸部21a以外の部分にはモールド金型21b底
面と凸部21aの高さ20〜50μm の間隙が生じ、モ
ールド工程によりこの部分に図4(C)に示すように2
0〜50μm の樹脂膜14aが形成される。
At this time, the convex portion 21a of the heat dissipation plate 21 is pressed against the bottom surface of the molding die 21b by the elasticity of the lead 13. For this reason, a gap of 20 to 50 μm in height is formed between the bottom surface of the molding die 21b and the convex portion 21a at a portion other than the convex portion 21a on the non-mounting surface of the semiconductor chip 11 of the heat dissipation plate 21. 2 as shown in 4 (C)
A resin film 14a having a thickness of 0 to 50 μm is formed.

【0032】第1実施例同様に樹脂膜14aにレーザ発
生装置18より捺印パターンに応じてレーザ光Lを照射
することにより捺印が行なわれる。
The marking is performed by irradiating the resin film 14a with the laser beam L from the laser generator 18 according to the marking pattern as in the first embodiment.

【0033】図6に本発明の第2実施例の斜視図を示
す。本実施例では捺印パターン19以外に凸部21aが
外部に表出し、放熱効果が高い。また、製造工程におい
てはパッケージ14のモールド時に保持ピン17が不要
となり、従来のモールド金型での製造が可能となる。
FIG. 6 shows a perspective view of the second embodiment of the present invention. In this embodiment, in addition to the imprint pattern 19, the convex portion 21a is exposed to the outside, and the heat dissipation effect is high. Further, in the manufacturing process, the holding pin 17 is not required when the package 14 is molded, and manufacturing with a conventional molding die is possible.

【0034】図7は本発明の第3実施例の斜視図を示
す。同図中、図4と同一構成部分には同一符号を付し、
その説明は省略する。本実施例は放熱板の形状が第2実
施例と異なる。図8に放熱板の斜視図を示す。放熱板3
1は放熱板21と同様、プレス加工や削出し加工により
半導体チップ11の非搭載面側に凸部31aを形成して
なる。ただし、凸部31aは金型22a,22bの樹脂
の注入口(ゲート)と空気排出孔(ベント)とを結ぶ線
分Iに対称となるように形成されている。以上の構成と
することにより樹脂が20〜50μm 程度の狭い間隙に
もスムーズに注入され、樹脂膜14aの形成状態が良好
なものとなる。
FIG. 7 shows a perspective view of the third embodiment of the present invention. In the figure, the same components as those in FIG.
The description is omitted. This embodiment differs from the second embodiment in the shape of the heat sink. FIG. 8 shows a perspective view of the heat sink. Heat sink 3
Similar to the heat dissipation plate 21, 1 has a convex portion 31a formed on the non-mounting surface side of the semiconductor chip 11 by pressing or shaving. However, the convex portion 31a is formed so as to be symmetrical with respect to a line segment I that connects the resin injection port (gate) of the molds 22a and 22b and the air discharge hole (vent). With the above structure, the resin can be smoothly injected into a narrow gap of about 20 to 50 μm, and the resin film 14a can be formed well.

【0035】図9は本発明の第4実施例の断面図を示
す。同図中、図1と同一構成部分には同一符号を付し、
その説明は省略する。本実施例は半導体チップ11と放
熱板12とが別体で設けられた半導体装置に適用したも
ので、半導体チップ11は支持リード13cと一体的に
形成されたステージ13d上に保持された構成をなす。
FIG. 9 shows a sectional view of the fourth embodiment of the present invention. In the figure, the same components as those in FIG.
The description is omitted. The present embodiment is applied to a semiconductor device in which the semiconductor chip 11 and the heat dissipation plate 12 are provided separately, and the semiconductor chip 11 is held on a stage 13d integrally formed with the support lead 13c. Eggplant

【0036】図10は本発明の第5実施例の断面図を示
す。同図中、図1と同一構成部分には同一符号を付し、
その説明は省略する。
FIG. 10 shows a sectional view of the fifth embodiment of the present invention. In the figure, the same components as those in FIG.
The description is omitted.

【0037】本実施例はTSOP(Thin Small Out-lin
ed Package)の半導体装置に適用したもので支持リード
13cに一体的に形成されたステージ13d上に半導体
チップ11が搭載され薄型化が計られている。本実施例
では放熱板がないため、ステージ13dの半導体チップ
11の非搭載面に樹脂膜14aを第1乃至第3実施例と
同様な工程により形成される。
In this embodiment, TSOP (Thin Small Out-lin)
It is applied to a semiconductor device of an ed package), and the semiconductor chip 11 is mounted on the stage 13d integrally formed with the support lead 13c to achieve a thin structure. In this embodiment, since there is no heat sink, the resin film 14a is formed on the non-mounting surface of the semiconductor chip 11 of the stage 13d by the same process as in the first to third embodiments.

【0038】なお、ステージ13dはリードフレーム1
3と同様なメタル材料により構成されているため、捺印
時には、放熱板と同様にパッケージ14とのコントラス
トの高い、視認性の良好な捺印が可能となる。
The stage 13d is the lead frame 1
Since it is made of the same metal material as that of No. 3, at the time of imprinting, it is possible to imprint with high visibility and good visibility as with the heat dissipation plate.

【0039】なお、第1乃至第5実施例ではリードフレ
ーム13は表面実装型の形状となっているが、これに限
ることはなく、DIP(Dual In-line Package)、SI
P(Single In-line Package)等の樹脂パッケージによ
り封止された半導体装置に幅広く適用できる。
Although the lead frame 13 has a surface mounting type in the first to fifth embodiments, the present invention is not limited to this, and the lead frame 13 is not limited to this, and the DIP (Dual In-line Package), SI
It can be widely applied to semiconductor devices sealed with a resin package such as P (Single In-line Package).

【0040】[0040]

【発明の効果】上述の如く、本発明によれば、放熱板上
に形成された樹脂膜を局所的に除去し、捺印を行なうた
め、樹脂膜と放熱板とのコントラストにより、捺印の視
認性が向上すると共に、放熱板上に樹脂膜が形成される
ため、放熱板を樹脂膜により保護でき、プリント基板等
への搭載時に放熱板と配線とが接触しにくくなり、回路
の保護が行なえる等の特長を有する。
As described above, according to the present invention, since the resin film formed on the heat dissipation plate is locally removed and the marking is performed, the visibility of the marking can be confirmed by the contrast between the resin film and the heat dissipation plate. Since the resin film is formed on the heat dissipation plate, the heat dissipation plate can be protected by the resin film, and the heat dissipation plate and the wiring are less likely to contact each other when mounted on a printed circuit board, etc., and the circuit can be protected. It has features such as

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例の製造工程図である。FIG. 1 is a manufacturing process diagram of a first embodiment of the present invention.

【図2】本発明の第1実施例の要部の斜視図である。FIG. 2 is a perspective view of a main part of the first embodiment of the present invention.

【図3】本発明の第1実施例の斜視図である。FIG. 3 is a perspective view of the first embodiment of the present invention.

【図4】本発明の第2実施例の製造工程図である。FIG. 4 is a manufacturing process drawing of the second embodiment of the present invention.

【図5】本発明の第2実施例の放熱板の斜視図である。FIG. 5 is a perspective view of a heat dissipation plate according to a second embodiment of the present invention.

【図6】本発明の第2実施例の斜視図である。FIG. 6 is a perspective view of a second embodiment of the present invention.

【図7】本発明の第3実施例の斜視図である。FIG. 7 is a perspective view of a third embodiment of the present invention.

【図8】本発明の第3実施例の放熱板の斜視図である。FIG. 8 is a perspective view of a heat dissipation plate according to a third embodiment of the present invention.

【図9】本発明の第4実施例の断面図である。FIG. 9 is a sectional view of a fourth embodiment of the present invention.

【図10】本発明の第5実施例の断面図である。FIG. 10 is a sectional view of a fifth embodiment of the present invention.

【図11】従来の一例の斜視図である。FIG. 11 is a perspective view of a conventional example.

【符号の説明】[Explanation of symbols]

11 半導体チップ 12 放熱板 13 リードフレーム 14 パッケージ 11 semiconductor chip 12 heat sink 13 lead frame 14 package

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップ(11)及び該半導体チッ
プ(11)で生じる熱を放熱する放熱板(12)を該半
導体チップ(11)を外部と接続するリード(13)と
共に樹脂製のパッケージ(14)で一体的にモールドし
てなる半導体装置の製造方法において、 前記放熱板(12)表面に樹脂膜(14a)を形成する
樹脂膜形成工程と、 前記樹脂膜(14a)を熱線により局所的に除去し、前
記放熱板(12)を局所的に剥き出すことにより捺印を
行なう捺印工程とを有することを特徴とする半導体装置
の製造方法。
1. A resin package (1) with a semiconductor chip (11) and a heat radiating plate (12) for radiating heat generated in the semiconductor chip (11) together with leads (13) for connecting the semiconductor chip (11) to the outside. 14) In the method of manufacturing a semiconductor device integrally molded with, a resin film forming step of forming a resin film (14a) on the surface of the heat dissipation plate (12), and locally heating the resin film (14a) by heat rays. And a stamping step of stamping the heat sink (12) locally by exposing the heat sink (12).
【請求項2】 半導体チップ(11)及び該半導体チッ
プ(11)を保持するステージ(13d)を該半導体チ
ップ(11)を外部と接続するリードフレーム(13)
と共に樹脂製のパッケージ(14)で一体的にモールド
してなる半導体装置の製造方法において、 前記ステージ(13d)の前記半導体チップ(11)の
非搭載面に樹脂膜(14a)を形成する樹脂膜形成工程
と、 前記樹脂膜を熱線により局所的に除去し、前記ステージ
(13d)の前記半導体チップ(11)の非搭載面を局
所的に剥き出すことにより捺印を行なう捺印工程とを有
することを特徴とする半導体装置の製造方法。
2. A lead frame (13) for connecting the semiconductor chip (11) and a stage (13d) holding the semiconductor chip (11) to the outside.
A method of manufacturing a semiconductor device integrally molded together with a resin package (14), comprising forming a resin film (14a) on a non-mounting surface of the semiconductor chip (11) of the stage (13d). A forming step and a marking step of locally removing the resin film with a heat ray and locally exposing a non-mounting surface of the semiconductor chip (11) of the stage (13d). A method for manufacturing a characteristic semiconductor device.
【請求項3】 前記樹脂膜形成工程は前記パッケージ
(14)のモールド工程中に同時に実行されることを特
徴とする請求項1又は2記載の半導体装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the resin film forming step is simultaneously performed during a molding step of the package (14).
【請求項4】 前記樹脂膜形成工程は前記パッケージ
(14)のモールド金型(16a,16b)に装着脱自
在に設けられ、前記樹脂膜(14a)の膜厚に対応した
位置に前記放熱板(12)の前記半導体チップ(11)
の非搭載面(12a)を保持する保持ピン(16b-1)
により前記放熱板(12)を前記モールド金型(16
a,16b)内に保持し、前記パッケージ(14)のモ
ールドを行なう工程と、 前記パッケージ(14)の形成後、前記保持ピン(16
b-1)を前記モールド金型(16a,16b)より離脱
させる工程とを有することを特徴とする請求項3記載の
半導体装置の製造方法。
4. The resin film forming step is detachably attached to a molding die (16a, 16b) of the package (14), and the heat dissipation plate is provided at a position corresponding to the film thickness of the resin film (14a). (12) The semiconductor chip (11)
Holding pin (16b-1) that holds the non-mounting surface (12a) of
The heat sink (12) by the mold (16
a, 16b) to mold the package (14), and after the package (14) is formed, the holding pin (16)
4. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of removing b-1) from the molding die (16a, 16b).
【請求項5】 前記樹脂膜形成工程は前記放熱板(1
2)の前記半導体チップ(11)の非搭載面(12a)
に前記樹脂膜(14a)の膜厚に応じた高さの凸部(1
2d)を形成し、前記パッケージ(14)のモールド工
程を実行することにより前記樹脂膜(14a)を形成す
ることを特徴とする請求項1又は3記載の半導体装置の
製造方法。
5. The heat sink (1) in the resin film forming step.
2) Non-mounting surface (12a) of the semiconductor chip (11)
The convex portion (1) having a height corresponding to the film thickness of the resin film (14a)
2. The method of manufacturing a semiconductor device according to claim 1, wherein the resin film (14a) is formed by forming 2d) and performing a molding process of the package (14).
【請求項6】 前記樹脂膜形成工程は前記樹脂膜(14
a)の膜厚を50μm 以下に形成することを特徴とする
請求項1乃至5記載の半導体装置の製造方法。
6. The resin film forming step comprises:
6. The method for manufacturing a semiconductor device according to claim 1, wherein the film thickness of a) is formed to 50 μm or less.
JP4326933A 1992-12-07 1992-12-07 Fabrication of semiconductor device Withdrawn JPH06177268A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4326933A JPH06177268A (en) 1992-12-07 1992-12-07 Fabrication of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4326933A JPH06177268A (en) 1992-12-07 1992-12-07 Fabrication of semiconductor device

Publications (1)

Publication Number Publication Date
JPH06177268A true JPH06177268A (en) 1994-06-24

Family

ID=18193393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4326933A Withdrawn JPH06177268A (en) 1992-12-07 1992-12-07 Fabrication of semiconductor device

Country Status (1)

Country Link
JP (1) JPH06177268A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999050908A1 (en) * 1998-03-26 1999-10-07 Seiko Epson Corporation Method of manufacturing semiconductor device, apparatus for molding semiconductor device, and semiconductor device
KR100308396B1 (en) * 1998-12-03 2001-12-17 마이클 디. 오브라이언 Manufacturing method of semiconductor package
JP2002334975A (en) * 2001-05-08 2002-11-22 Nec Corp Support structure of semiconductor device, CCD semiconductor device, method of manufacturing the same, and package for CCD semiconductor device
US7273769B1 (en) * 2000-08-16 2007-09-25 Micron Technology, Inc. Method and apparatus for removing encapsulating material from a packaged microelectronic device
JP2015088731A (en) * 2013-09-25 2015-05-07 株式会社大真空 Lead type electronic equipment
KR20200040700A (en) 2017-08-18 2020-04-20 나믹스 가부시끼가이샤 Semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999050908A1 (en) * 1998-03-26 1999-10-07 Seiko Epson Corporation Method of manufacturing semiconductor device, apparatus for molding semiconductor device, and semiconductor device
US6821822B1 (en) 1998-03-26 2004-11-23 Seiko Epson Corporation Method of manufacturing semiconductor device, molding device for semiconductor device, and semiconductor device
KR100308396B1 (en) * 1998-12-03 2001-12-17 마이클 디. 오브라이언 Manufacturing method of semiconductor package
US7273769B1 (en) * 2000-08-16 2007-09-25 Micron Technology, Inc. Method and apparatus for removing encapsulating material from a packaged microelectronic device
US7405487B2 (en) 2000-08-16 2008-07-29 Micron Technology, Inc. Method and apparatus for removing encapsulating material from a packaged microelectronic device
JP2002334975A (en) * 2001-05-08 2002-11-22 Nec Corp Support structure of semiconductor device, CCD semiconductor device, method of manufacturing the same, and package for CCD semiconductor device
JP2015088731A (en) * 2013-09-25 2015-05-07 株式会社大真空 Lead type electronic equipment
KR20200040700A (en) 2017-08-18 2020-04-20 나믹스 가부시끼가이샤 Semiconductor device
US11315846B2 (en) 2017-08-18 2022-04-26 Namics Corporation Semiconductor device

Similar Documents

Publication Publication Date Title
US7093744B2 (en) Recognition device, bonding device, and method of manufacturing a circuit device
US6617200B2 (en) System and method for fabricating a semiconductor device
JPH06177268A (en) Fabrication of semiconductor device
JP4667666B2 (en) Chip array module
US20090283897A1 (en) Semiconductor package, method for manufacturing a semiconductor package, an electronic device, method for manufacturing an electronic device
JP2002093982A (en) Semiconductor device and manufacturing method thereof
JP2003197664A (en) Semiconductor device and its manufacturing method, circuit board, and electronic equipment
JPH0719876B2 (en) Semiconductor device
JP2006156674A (en) Semiconductor device and manufacturing method thereof
JPH08264910A (en) Manufacture of printed wiring board with heat sink and method for mounting high-power component on the board
JP2748657B2 (en) Semiconductor device
US7705438B2 (en) Electronic component and leadframe for producing the component
JP3602052B2 (en) Heat sink and method of manufacturing the same, semiconductor package and method of manufacturing the same
JPH0766570A (en) Electronic circuit package and manufacturing method thereof
JP2714691B2 (en) Manufacturing method of electronic component mounting board
JPH08102583A (en) Wiring circuit board
CN100365812C (en) Semiconductor device and method for producing high contrast identification mark
TWI235473B (en) Ball grid array package structure, heat slug structure, and laser mark rework method
JP3733181B2 (en) Semiconductor mounting substrate and manufacturing method thereof
JP3625903B2 (en) Resin package type semiconductor device and manufacturing method thereof
JP2976941B2 (en) Semiconductor device and manufacturing method thereof
JP2702321B2 (en) Semiconductor device manufacturing equipment
JP2008251795A (en) Semiconductor device
KR100515101B1 (en) manufacturing method of semiconductor package and its semiconductor package
JP2001053401A (en) Hybrid integrated circuit device

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20000307