JPH061796B2 - Method of manufacturing thin film device - Google Patents

Method of manufacturing thin film device

Info

Publication number
JPH061796B2
JPH061796B2 JP61164652A JP16465286A JPH061796B2 JP H061796 B2 JPH061796 B2 JP H061796B2 JP 61164652 A JP61164652 A JP 61164652A JP 16465286 A JP16465286 A JP 16465286A JP H061796 B2 JPH061796 B2 JP H061796B2
Authority
JP
Japan
Prior art keywords
inorganic insulating
insulating layer
thin film
layer
film device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61164652A
Other languages
Japanese (ja)
Other versions
JPS6320852A (en
Inventor
吉明 小松原
信夫 向井
功 福井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP61164652A priority Critical patent/JPH061796B2/en
Publication of JPS6320852A publication Critical patent/JPS6320852A/en
Publication of JPH061796B2 publication Critical patent/JPH061796B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) この発明は薄膜装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a method for manufacturing a thin film device.

(従来の技術) 近年、薄膜を用いた表示装置の発展には、めざましいも
のがある。現在、エレクトロルミネセンスや液晶等を用
いた表示装置が商品化されており、表示面積が大きくな
る方向に進んでいる。表示面積が大きくなるに従って、
画表数が多くなり、無機絶縁層を介して上下の配線が交
差する部分が増える。一方、大面積の所に、均一でピン
ホールのない無機絶縁層を形成することは非常に困難で
あり、配線が交差する部分での層間短絡が発生する。
(Prior Art) In recent years, there has been remarkable progress in the development of display devices using thin films. At present, display devices using electroluminescence, liquid crystal, etc. are commercialized, and the display area is increasing. As the display area increases,
The number of screens increases, and the number of portions where the upper and lower wirings intersect with each other via the inorganic insulating layer increases. On the other hand, it is very difficult to form a uniform and pinhole-free inorganic insulating layer in a large area, and an interlayer short circuit occurs at the intersection of wirings.

この対策として従来、第4図に示すように、基板(1)上
の第1導体層(2)として例えばタンタルのような陽極酸
化の可能あ金属を用いてこの表面に陽極酸化膜(3)を形
成し、更にこの上に無機絶縁層(4)と第2導体層(5)を順
次積層させている。
As a countermeasure against this, conventionally, as shown in FIG. 4, an anodizable metal such as tantalum is used as the first conductor layer (2) on the substrate (1), and an anodized film (3) is formed on this surface. Is formed, and the inorganic insulating layer (4) and the second conductor layer (5) are sequentially laminated on this.

また他の方法としては、第5図に示すよに、基板(10)上
の第1導体層(11)として同じく陽極酸化の可能な金属を
用い、この上に無機絶縁層(12)を形成した後、陽極酸化
処理を施してピンホール(13)の部分だけに陽極酸化膜(1
4)を形成し、更にこの上に第2導体層(15)を形成させて
いるものがある。
As another method, as shown in FIG. 5, the same anodizable metal is used as the first conductor layer (11) on the substrate (10), and the inorganic insulating layer (12) is formed thereon. After that, anodic oxidation treatment is applied and only the anodic oxide film (1
4) is formed, and then the second conductor layer (15) is further formed thereon.

(発明が解決しようとする問題点) しかしいずれの方法も、陽極酸化を行うため、使用可能
な金属が限定され、使用してよい材料が制約されるとと
もに、工程が複雑になる等の欠点を有する。
(Problems to be Solved by the Invention) However, in any of the methods, since anodization is performed, usable metals are limited, materials that can be used are restricted, and there are drawbacks such as a complicated process. Have.

この発明は、金属材料を選ばず且つ簡単な工程で、層間
絶縁膜のピンホールをなくし、高い歩留まりの得られる
薄膜装置の製造方法である。
The present invention is a method for manufacturing a thin film device which can obtain a high yield by eliminating pinholes in an interlayer insulating film by a simple process without selecting a metal material.

〔発明の構成〕[Structure of Invention]

(問題点を解決するための手段) この発明は、基板上に形成された第1導体層上に少なく
とも第1無機絶縁層と第2無機絶縁層とを介して配置さ
れた第2導体層とを備えた薄膜装置の製造方法であっ
て、前記第無機絶縁層形成後に前記第1無機絶縁層の表
面のごみや異常成長部分を除去する表面処理工程と、前
記第1無機絶縁層上に第2無機絶縁層を形成する工程と
を備えたことを特徴としている。
(Means for Solving the Problems) The present invention relates to a second conductor layer which is arranged on a first conductor layer formed on a substrate with at least a first inorganic insulating layer and a second inorganic insulating layer interposed therebetween. A method of manufacturing a thin-film device comprising: a surface treatment step of removing dust and abnormal growth portions on the surface of the first inorganic insulating layer after the formation of the first inorganic insulating layer; And a step of forming two inorganic insulating layers.

(作用) 例えばブラシスクラバーを用いた機械的な表面処理によ
り、簡単にピンホールがなくなり且つ導体層の材料を選
択する必要がない。
(Function) For example, mechanical surface treatment using a brush scrubber eliminates pinholes easily and there is no need to select a material for the conductor layer.

(実施例) 以下、この発明の実施例について、薄膜装置が薄膜トラ
ンジスタ(以後TFTと称す)アレイである場合を例にあ
げ、図面を参照して詳細に説明する。
(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings, taking a case where a thin film device is a thin film transistor (hereinafter referred to as TFT) array as an example.

第2図は、この実施例を適用するTFTアレイの数画素分
を示す平面図である。同図からわかるように、ゲート線
(20)と信号線(21)は直交しており、これらの線で囲まれ
た領域にはTFT(22)及びこれに接続する画数電極(23)が
形成されている。
FIG. 2 is a plan view showing several pixels of the TFT array to which this embodiment is applied. As you can see from the figure, the gate line
The signal line (21) and the signal line (21) are orthogonal to each other, and a TFT (22) and a number electrode (23) connected to the TFT (22) are formed in a region surrounded by these lines.

第3図は、第2図のA−B線を矢印方向にみたときの断
面図である。同図において、例えばガラスからなる基板
(30)上に順次、第1導体層(31)としてゲート電極、更に
これを覆うように無機絶縁層(32)としてゲート絶縁膜が
形成されている。そして無機絶縁層(32)上の第1導体層
(31)に対応する位置に、例えばアルモルファスシリコン
からなる半導体層(33)が形成され、更に第2導体層(34)
として半導体層(33)を挟むようにソース電極(35)とドレ
イン電極(36)、及びソース電極(35)に接続する画素電極
(37)が形成されている。なおソース及びドレイン電極(3
5),(36)と半導体層(33)との間には、例えばリを含んだ
アモルファスシリコンからなるオーミックコンタクト層
(38)が介在している。
FIG. 3 is a cross-sectional view when the line AB of FIG. 2 is viewed in the arrow direction. In the figure, for example, a substrate made of glass
A gate electrode is sequentially formed on the (30) as the first conductor layer (31), and a gate insulating film is further formed as the inorganic insulating layer (32) so as to cover the gate electrode. And the first conductor layer on the inorganic insulating layer (32)
A semiconductor layer (33) made of, for example, amorphous silicon is formed at a position corresponding to (31), and a second conductor layer (34) is further formed.
A pixel electrode connected to the source electrode (35), the drain electrode (36), and the source electrode (35) so that the semiconductor layer (33) is sandwiched between them.
(37) is formed. Source and drain electrodes (3
Between the semiconductor layers (5) and (36) and the semiconductor layer (33), for example, an ohmic contact layer made of amorphous silicon containing phosphorus.
(38) is intervening.

次に第1図を用いて、この発明の一実施例について説明
する。まず第1図(a)に示すように基板(30)上に例えばC
rからなる第1.導体層(31)を約1500Åの厚さに形成す
る。次に、無機絶縁層(32)を例えばプラズマCVD法によ
り、複数回例えば2回の段階に分けて形成する。即ち、
最初に第1図(b)に示すように、第1導体層(31)を覆う
ように例えばSiO2からなる第1無機絶縁層(321)を約150
0Åの厚さに形成する。次に第1無機絶縁層(321)上に機
械的な表面処理として、例えばブラシスクラバー或いは
ジェットスクラバー等により第1無機絶縁層(321)につ
いたごみや、異常成長部分の取り除きを行う。続いて、
第1図(c)に示すように、第1無機絶縁層(321)上に例え
ばSiO2からなる第2無機絶縁層(322)約1500Åの厚さに
形成し、更にこうして形成が完了した無機絶縁層(32)上
に順次厚さ約3000Åの半導体層(33)、厚さ約500Åのオ
ーミックコンタクト層(38)を例えばプラズマCVD法によ
り形成する。なお半導体層(33)とオーミックコンタクト
層(38)は、1図(d)に示すように、フォトレジスト(40)
を用いて所定のパターンにする。次にフォトレジスト(4
0)を剥離した後、第1図(e)に示すように、例えばIT
O(Indium Tin Oxide)からなる画素電極(37)を約1000
Åの厚さに例えばスパッタリングにより形成し、フォト
レジスト(41)を用いて所定のパターンにする。続いてフ
ォトレジスト(41)を剥離した後、例えばAlをスパッタリ
ング法で約1μmの厚さに堆積し、その後フォトレジス
トを用いて第1図(f)に示すように、所定のパターンに
ソース及びドレイン電極(35),(36)を形成するととも
に、このソース及びドレイン電極35),(36)をマスクに
してオーミックコンタクト層(38)の一部をエッチングす
る。こうして所望の薄膜装置が得られる。
Next, an embodiment of the present invention will be described with reference to FIG. First, as shown in FIG. 1 (a), for example, C on the substrate (30).
First consisting of r 1. The conductor layer (31) is formed to a thickness of about 1500Å. Next, the inorganic insulating layer (32) is formed, for example, by a plasma CVD method in a plurality of times, for example, in two steps. That is,
First, as shown in FIG. 1 (b), a first inorganic insulating layer (321) made of, for example, SiO 2 is formed to cover the first conductor layer (31) by about 150.
Form to a thickness of 0Å. Next, as a mechanical surface treatment on the first inorganic insulating layer (321), dust attached to the first inorganic insulating layer (321) and abnormal growth portions are removed by, for example, a brush scrubber or a jet scrubber. continue,
As shown in FIG. 1 (c), a second inorganic insulating layer (322) made of, for example, SiO 2 is formed on the first inorganic insulating layer (321) to a thickness of about 1500 Å, and the inorganic layer thus completed is formed. A semiconductor layer (33) having a thickness of about 3000Å and an ohmic contact layer (38) having a thickness of about 500Å are sequentially formed on the insulating layer (32) by, for example, a plasma CVD method. The semiconductor layer (33) and the ohmic contact layer (38) are formed of a photoresist (40) as shown in FIG. 1 (d).
To form a predetermined pattern. Then photoresist (4
After peeling off (0), as shown in FIG.
Approximately 1000 pixel electrodes (37) made of O (Indium Tin Oxide)
It is formed to a thickness of Å, for example, by sputtering, and a predetermined pattern is formed using a photoresist (41). Then, after removing the photoresist (41), for example, Al is deposited to a thickness of about 1 μm by a sputtering method, and then the photoresist is used to form a source and a predetermined pattern as shown in FIG. 1 (f). While forming the drain electrodes (35) and (36), a part of the ohmic contact layer (38) is etched by using the source and drain electrodes 35) and (36) as a mask. Thus, a desired thin film device is obtained.

この実施例では、無機絶縁層(32)の形成の際の各段階の
間、即ち第1無機絶縁層(321)を形成した後の機械的な
表面処理により、第1無機絶縁層(321)上のごみや異状
成長部分が除去されるので、無機絶縁層(32)にこれらに
起因して発生するピンホールがなくなった。この結果、
第1導体層(31)に連なったゲート線(20)ドレイン電極(3
6)に連なった信号線(21)との間に、無機絶縁層(32)のピ
ンホールによる短絡がなくなり、TFTアレイが高い歩留
まりで製造できるようになった。
In this embodiment, the first inorganic insulating layer (321) is subjected to mechanical surface treatment during each step of forming the inorganic insulating layer (32), that is, after forming the first inorganic insulating layer (321). Since the dust and the abnormal growth portion on the top are removed, the inorganic insulating layer (32) has no pinhole caused by these. As a result,
Gate line (20) connected to the first conductor layer (31) Drain electrode (3
The short circuit due to the pinhole of the inorganic insulating layer (32) between the signal line (21) connected to 6) and the signal line (21) disappeared, and the TFT array can be manufactured with a high yield.

なお、ここでは薄膜装置がTFTアレイである場合につい
て述べたが、これが限らず、層間無機絶縁膜を有する装
置であればこの発明は適用可能である。また無機絶縁層
(32)は2段階に分けて形成したが、これに限らず、異な
る材料からなる層を何段階かに分けて形成したものであ
ってもよい。
Although the thin film device is a TFT array here, the invention is not limited to this, and the present invention can be applied to any device having an interlayer inorganic insulating film. Also an inorganic insulating layer
Although (32) is formed in two steps, the present invention is not limited to this, and it may be formed in several steps of layers made of different materials.

〔発明の効果〕〔The invention's effect〕

以上要するに、この発明は導体層間の無機絶縁層を複数
回の段階に分けて形成し、各段階の間に機械的な表面処
理を入れているので、この無機絶縁層に発生するピンホ
ールが少なくなり、性能のよい薄膜装置が得られる。
In summary, since the present invention forms the inorganic insulating layer between the conductor layers by dividing it into a plurality of steps and performs the mechanical surface treatment between the steps, the pinholes generated in the inorganic insulating layer are reduced. Therefore, a thin film device with good performance can be obtained.

【図面の簡単な説明】[Brief description of drawings]

第1図はこの発明の一実施例を示す工程断面図、第2図
はこの発明を適用するTFTアレイの一例を示す平面図、
第3図は第2図のA−B線を矢印方向からみたときの断
面図、第4図と第5図は従来の薄膜装置の製造方法の一
例を示す断面図である。 (30)…基板 (31)…第1導体層 (32)…無機絶縁層 (34)…第2導体層
1 is a process sectional view showing an embodiment of the present invention, FIG. 2 is a plan view showing an example of a TFT array to which the present invention is applied,
FIG. 3 is a cross-sectional view of FIG. 2 taken along the line AB, and FIGS. 4 and 5 are cross-sectional views showing an example of a conventional method for manufacturing a thin film device. (30) ... Substrate (31) ... First conductor layer (32) ... Inorganic insulating layer (34) ... Second conductor layer

フロントページの続き (56)参考文献 特開 昭51−36082(JP,A) 特開 昭51−9259(JP,A) 特開 昭61−97946(JP,A)Continuation of front page (56) References JP-A-51-36082 (JP, A) JP-A-51-9259 (JP, A) JP-A-61-97946 (JP, A)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】基板上に形成された第1導体層上に少なく
とも第1無機絶縁層と第2無機絶縁層とを介して配置さ
れた第2導体層とを備えた薄膜装置の製造方法であっ
て、 前記第1無機絶縁層形成後に前記第1無機絶縁層の表面
のごみや異常成長部分を除去する表面処理工程と、 前記第1無機絶縁層上に第2無機絶縁層を形成する工程
とを備えたことを特徴とする薄膜装置の製造方法。
1. A method of manufacturing a thin film device, comprising: a first conductor layer formed on a substrate; and a second conductor layer disposed at least through a first inorganic insulating layer and a second inorganic insulating layer. A surface treatment step of removing dust and abnormal growth portions on the surface of the first inorganic insulating layer after forming the first inorganic insulating layer; and a step of forming a second inorganic insulating layer on the first inorganic insulating layer. And a method for manufacturing a thin film device.
JP61164652A 1986-07-15 1986-07-15 Method of manufacturing thin film device Expired - Lifetime JPH061796B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61164652A JPH061796B2 (en) 1986-07-15 1986-07-15 Method of manufacturing thin film device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61164652A JPH061796B2 (en) 1986-07-15 1986-07-15 Method of manufacturing thin film device

Publications (2)

Publication Number Publication Date
JPS6320852A JPS6320852A (en) 1988-01-28
JPH061796B2 true JPH061796B2 (en) 1994-01-05

Family

ID=15797247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61164652A Expired - Lifetime JPH061796B2 (en) 1986-07-15 1986-07-15 Method of manufacturing thin film device

Country Status (1)

Country Link
JP (1) JPH061796B2 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS519259A (en) * 1974-07-12 1976-01-24 Hitachi Ltd Haisensono hogohoho
JPS583377B2 (en) * 1974-09-21 1983-01-21 三菱電機株式会社 How to use hand tools
JPS6197946A (en) * 1984-10-19 1986-05-16 Matsushita Electronics Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS6320852A (en) 1988-01-28

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