JPH06181256A - Wafer carrier and semiconductor manufacturing apparatus - Google Patents

Abstract

(57) [Summary] [Purpose] To suppress cracks and the like in semiconductor chips that occur during the dicing process of a semiconductor wafer due to chips and the like of a wafer sheet. In a wafer ring 11 used in a dicing process, which is one process of manufacturing a semiconductor integrated circuit device, a groove 11a is provided in a region corresponding to an outer peripheral edge of the wafer sheet 10, and the outer peripheral edge of the wafer sheet 10 is recessed. Groove 11a
I was able to paste it inside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer carrier and a semiconductor manufacturing apparatus technology, and is effectively applied to a wafer carrier used in a dicing process which is one process of manufacturing a semiconductor integrated circuit device. It is related to technology.

[0002]

2. Description of the Related Art A conventional wafer carrier used in, for example, a dicing process has a wafer ring made of an adhesive resin tape on the back side of a wafer ring made of a flat ring-shaped flat metal, and the adhesive surface of the wafer ring. It is affixed in a state of being exposed from the center of.

As a conventional method for providing a wafer sheet on the back surface of the wafer ring, a sticky resin tape larger than the wafer ring is attached to the back surface of the wafer ring,
There is a method of cutting the resin tape along the outer circumference of the wafer ring, a method of cutting the adhesive resin tape with the same size as the outer diameter of the wafer ring, and then attaching the resin tape to the back surface of the wafer ring. .

Regarding the dicing technology, Realize Co., Ltd., issued September 5, 1986, "Super LSI"
Factory latest technology compilation Part 2 Latest process and automation "P
243 to P250, and describes the dicing process and the automation of the dicing process.

[0005]

However, the present inventor has found that the above-mentioned conventional technique has the following problems.

That is, chips left on the outer periphery of the wafer sheet, foreign matters attached to the outer periphery of the wafer sheet, etc. directly or indirectly through the wafer transfer belt of the dicing apparatus or the wafer of the dicing apparatus. By attaching to the vacuum suction stage, when the semiconductor wafer is placed on the stage during the dicing process, the semiconductor wafer is inclined by the thickness of the chips or the like at the portion where the chips or the like are attached. When the dicing blade is applied, there is a problem that minute cracks or chips are generated in the semiconductor chip in that portion.

In particular, when the chips and the like adhere to the wafer vacuum suction stage of the dicing device, the problem such as the crack of the semiconductor chip is not limited to one semiconductor wafer but is continuous in a plurality of semiconductor wafers. There was a problem that occurred. Further, the problem such as cracking of the semiconductor chip is a significant problem in the case of the full cut method of completely cutting the semiconductor wafer during the dicing process.

Therefore, conventionally, the wafer carrier has to be cleaned in order to remove the chips, foreign matters and the like adhering to the wafer carrier, but this is a troublesome work.

The present invention has been made in view of the above-mentioned problems, and an object thereof is to suppress cracks and the like of semiconductor chips generated during a dicing process of a semiconductor wafer due to chips of a wafer sheet and the like. It is to provide the technology that can.

Another object of the present invention is to provide a technique capable of simplifying the cleaning process of the wafer carrier.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the invention according to claim 1 is a wafer carrier for carrying a semiconductor wafer in a state in which a semiconductor wafer is stuck to a wafer sheet stuck to a wafer ring, wherein the wafer ring comprises the wafer. A wafer carrier structure is provided in which a recess is provided in a region corresponding to the outer periphery of the sheet.

According to a second aspect of the present invention, in a wafer ring to which a wafer sheet is attached, a wafer carrier having a recess which is lower than other areas is placed in a region corresponding to the outer periphery of the wafer sheet. And a mounting table and a wafer dividing means for dividing a semiconductor wafer attached on the wafer sheet into semiconductor chips.

[0015]

According to the above means, even if chips or the like of the wafer sheet are present at the outer peripheral edge of the wafer sheet, the chips or the like are present in the recess on the back surface of the wafer ring,
Since the contact with the outside is hindered, it is difficult to adhere to, for example, the conveyor belt or the stage of the dicing device. That is, it is possible to prevent the chips and the like from directly or indirectly adhering to the back surface of the wafer sheet during the transfer of the wafer carrier.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a cross-sectional view of an essential part of a wafer carrier which is an embodiment of the present invention, FIG. 2 is an overall plan view of a wafer carrier holding a semiconductor wafer, and FIGS. 3 and 4 show a wafer carrier. It is explanatory drawing of the semiconductor manufacturing apparatus used.

The semiconductor manufacturing apparatus of this embodiment shown in FIGS. 3 and 4 is a full-cut dicing type dicing apparatus 1 used in a manufacturing process of a semiconductor integrated circuit device, for example.

The dicing apparatus 1 comprises a loader section 2, a stage 3, and a dicing blade (wafer dividing means) 4.
The cleaning / drying processing section 5, the unloader section 6, and the conveyor belts 7a to 7c.

The loader section 2 is a mechanism section for loading a wafer carrier 9 (described later) holding the semiconductor wafer 8 into the dicing apparatus 1, and the accommodation chamber 2a has a semiconductor wafer 8 therein.
A plurality of wafer carriers 9 holding the above are accommodated. It should be noted that FIG. 4 shows only one wafer transfer body 9 in the accommodation chamber 2a in order to make the drawing easy to see.

The stage 3 is a mounting table for holding the wafer carrier 9 holding the semiconductor wafer 8 by a vacuum suction method. The dicing blade 4 is an extremely thin cutting grindstone for dividing the semiconductor wafer 8 into semiconductor chips.

The cleaning / drying processing section 5 is a processing section for cleaning and drying the semiconductor wafer 8 after the dicing processing.

The unloader unit 6 is a mechanism unit for carrying out the wafer carrier 9 after the dicing process to the outside of the dicing apparatus 1, and a plurality of wafer carriers 9 are housed in the housing chamber.

The transfer belts 7a to 7c are transfer mechanism parts for transferring the wafer transfer body 9 to each part.

Next, the wafer carrier 9 of this embodiment will be described with reference to FIGS.

The wafer carrier 9 of this embodiment is a jig for holding and carrying the semiconductor wafer 8 in the dicing process to the die bonding process, for example.

The wafer carrier 9 is composed of a wafer sheet 10 for holding the semiconductor wafer 8 and a wafer ring 11 made of a flat ring-shaped metal flat plate attached to the outer periphery of the main surface of the wafer sheet 10. There is.

The semiconductor wafer 8 is made of, for example, silicon (S
i) It is made of a single crystal and has a plurality of chip regions 8a formed on its main surface. Each chip area 8a is arranged with a chip dividing line 8b in between.
In this, for example, a semiconductor logic circuit, a semiconductor memory circuit, etc. have already been formed.

The wafer sheet 10 has a thickness of 80 μm, for example.
It consists of a resin tape with a degree of tackiness. Wafer ring 11
For example, the surface of stainless steel is plated with chrome or the like, and the thickness thereof is, for example, about 1 mm.

By the way, in the present embodiment, the wafer ring 11 is provided with a groove 11a at the outer peripheral edge of the wafer sheet 10. That is, the outer peripheral edge of the wafer sheet 10 is attached inside the groove 11a.

Therefore, the wafer carrier 9 of the present embodiment is
Even if the chips 12 or the like of the wafer sheet 10 are present at the outer peripheral edge of the wafer sheet 10, the chips 12 or the like are present in the concave groove 11a on the back surface of the wafer ring 11 and are difficult to contact with the outside. ing. That is, the wafer carrier 9 of this embodiment has a structure in which the chips 12 and the like of the wafer sheet 10 are unlikely to adhere to the carrier belt 7a of the dicing device 1, the stage 3, and the like.

The concave groove 11a is formed, for example, by cutting so as to extend along the circumference of the wafer ring. The depth of the recessed groove 11a is set to be equal to or larger than the thickness of the wafer sheet 10 and to a dimension such that the chips 12 do not move to the outside, and is, for example, about 0.5 mm.

As described above, according to this embodiment, the following effects can be obtained.

(1) In the wafer ring 11, the concave groove 11a is formed at the position of the outer peripheral edge of the wafer sheet 10, so that the wafer sheet 10 is formed at the outer peripheral edge of the wafer sheet 10.
Even if there are chips 12 and the like, those chips 1
Since 2 and the like are present in the concave groove 11a on the back surface of the wafer ring 11 and are prevented from contacting with the outside, they are unlikely to adhere to the conveyor belt 7a of the dicing device 1, the stage 3 or the like. That is, it is possible to prevent the chips 12 and the like from directly or indirectly adhering to the back surface of the wafer sheet 10 during the transfer of the wafer carrier 9.

(2) Due to the above (1), it is possible to suppress cracks and the like in the semiconductor chips that occur during the dicing process of the semiconductor wafer 8 due to the chips 12 and the like, so that the yield of the semiconductor integrated circuit device is improved. And it becomes possible to improve reliability.

(3) Due to the above (1), the necessity of cleaning the wafer transfer body 9 is reduced, so that the cleaning can be simplified.

Although the invention made by the present inventor has been concretely described above based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above-described embodiment, the case where the groove is formed in the wafer ring has been described, but the present invention is not limited to this, and various modifications can be made.
As shown in, the outer peripheral thickness of the wafer ring may be thinner than the inner peripheral thickness to form the low step portion 11b corresponding to the depression. In this case, the low step portion 11b has less restrictions on the position, width, etc., as compared with the restrictions of the concave groove of the above-mentioned embodiment, so that the effect that the formation is easy is obtained.

Further, as shown in FIG. 6, the wafer ring 1
The inner circumference of 1 may be thinner than the outer circumference to form the low step portion 11b corresponding to the depression. In this case, the contact area between the wafer sheet 10 and the wafer ring 11 can be increased as compared with the case of the above-described embodiment and FIG. 5, so that the adhesive force of the wafer sheet 10 is larger than that of the above-described embodiment and the case of FIG. Can also be improved.

Further, in the above-mentioned embodiment, the case where the wafer ring is cut to form the depression is described, but the present invention is not limited to this. For example, the outer peripheral side of the conventional flat wafer ring is described. Alternatively, a ring-shaped metal may be joined to the inner peripheral side by a spot welding method or the like, and as a result, a low step portion corresponding to a recess may be formed on the inner peripheral side or the outer peripheral side of the wafer ring.

In the above embodiment, the case where the wafer ring is made of stainless steel has been described, but the present invention is not limited to this, and various modifications are possible, for example, plastic or the like may be used. In this case, the wafer carrier can be made light and inexpensive.

[0041]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

According to the present invention, even if chips or the like of the wafer sheet are present at the outer peripheral edge of the wafer sheet, the chips or the like are present in the depressions on the back surface of the wafer ring and contact with the outside. Are prevented from being adhered to, for example, the transfer belt of the dicing device, the stage, or the like. That is,
It is possible to suppress the chips and the like from directly or indirectly adhering to the back surface of the wafer sheet during the transfer of the wafer carrier.

Therefore, it is possible to suppress cracks and the like in the semiconductor chips that occur during the dicing process of the semiconductor wafer due to the chips and the like, so that the yield and reliability of the semiconductor integrated circuit device can be improved. Becomes Further, since the necessity for cleaning the wafer carrier is reduced, the cleaning process can be simplified.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a wafer transfer body that is an embodiment of the present invention.

FIG. 2 is an overall plan view of a wafer carrier that holds a semiconductor wafer.

FIG. 3 is an explanatory diagram of a semiconductor manufacturing apparatus using a wafer carrier.

FIG. 4 is an explanatory diagram of a semiconductor manufacturing apparatus using a wafer carrier.

FIG. 5 is a cross-sectional view of an essential part of a wafer carrier which is another embodiment of the present invention.

FIG. 6 is a cross-sectional view of an essential part of a wafer carrier which is another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Dicing apparatus (semiconductor manufacturing apparatus) 2 Loader section 2a Storage chamber 3 Stage (mounting table) 4 Dicing blade (wafer dividing means) 5 Cleaning / drying processing section 6 Unloader section 7a to 7c Transport belt 8 Semiconductor wafer 8a Chip area 8b Chip division Line 9 Wafer carrier 10 Wafer sheet 11 Wafer ring 11a Recessed groove (concave) 11b Lower step (concave) 12 Chips

Claims (2)

[Claims] 1. A wafer carrier for transporting a semiconductor wafer in a state where a semiconductor wafer is stuck to a wafer sheet stuck to a wafer ring, wherein a recess is formed in a region corresponding to an outer periphery of the wafer sheet in the wafer ring. A wafer carrier characterized by being provided. 2. In a wafer ring having a wafer sheet attached thereto, a mounting table on which a wafer carrier having a recess is provided in a region corresponding to an outer periphery of the wafer sheet, and a semiconductor wafer attached onto the wafer sheet. And a wafer dividing means for dividing the wafer into semiconductor chips.