JPH0618364B2 - Time synchronization method for data transmission system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention synchronizes the time of a clock installed at both end stations via a data transmission line in a data transmission system for bidirectional data transmission between remote points. The present invention relates to a time synchronization method of a data transmission system.

[Conventional technology]

With the advancement of power system operation, it becomes necessary to accurately record and analyze the operation time and operation sequence of protection devices and equipment at each electric station over a wide area, and it is also necessary to collect measurement data at different points. The problem has arisen that the data collection points must match.

As a method of solving these problems, a clock circuit is provided in the master station and each slave station of the data transmission system, the operation of the protection device and the device is transmitted together with the code of this time, and all slave stations are set at a predetermined time. A method is conceivable in which measurement is performed all at once, the measurement data is temporarily stored in a memory, and then transmitted to the master station.

In this case, what is important is that the clock circuits of the master station and slave station are synchronized within an error range that is practically acceptable, but the time required for data transmission is far beyond the error range. In order to exceed the limit, special synchronization method is required.

The conventional time synchronization method for this type of data transmission system is
When the clock circuit of the master station reaches a predetermined time, the master station transmits a time setting signal, and the slave station receives this and sets the slave station clock circuit in consideration of the transmission delay time.

[Problems to be solved by the invention]

Since the time synchronization method of the conventional data transmission system is performed as described above, there is no delay in the operation because the time synchronization is performed in real time, and the arithmetic processing circuits of the master station and slave stations suspend other operations. However, there is a problem that the time synchronization operation must be performed exclusively. Further, in a system that constantly cyclically transmits data, there is a problem in that if the time synchronization signal is to be transmitted in real time, the data flow must be temporarily stopped.

The present invention has been made in order to solve the above-mentioned problems, and does not impose an operation interruption or a heavy burden on the arithmetic processing unit of the data transmission system, and keeps the flow even in the case of constant cyclic transmission. It is an object of the present invention to provide a time synchronization method for a data transmission system capable of time synchronization between a master clock and a slave clock.

[Means for solving problems]

A time synchronization method of a data transmission system according to a first invention of this application is that a slave station is preset from a break point of a frame of a code transmitted to the master station in response to a time check command from the master station. The data is transmitted as data in the frame following the delimiter of the time T _S1 of the slave clock before the fixed time ta, and the master station transmits one frame of code from the time T _R0 of the master clock when the reception of the frame is completed. Length tc + fixed time ta
+ Estimated time T of child clock less the total of transmission delay time td
_S10 is calculated, and the difference T _S10 −T _S1 between this and the time T _{S1 of the} child clock that has arrived as data from the child station is transmitted to the child station as time correction data, and when the child station receives it. By correcting the time of the child clock by adding the difference T _S10 −T _S1 , the child clock is synchronized with the master clock.

In a time synchronization method for a data transmission system according to a second invention of this application, a slave station is preset from a break point of a frame of a code transmitted toward the master station in response to a time check command from the master station. The time T _{S1 of the} child clock before the fixed time ta is transmitted as data in the frame following the delimiter, and the master station transmits the time T _S1 of the child clock received as data from the child station. The slave clock estimated time T _R10 is calculated by adding the total of the delay time td + the time ta from the time reading of the slave clock to the code transmission + the length tc of one code frame,
This and the time T of the master clock when the reception of the frame is completed
The difference T _R0 -T _R10 and _R0 transmitted as time correction data to said slave station, said by the slave station modifies the addition of the difference T _R0 -T _R10 to the terminal time of the clock to undergo this The child clock is synchronized with the parent clock.

[Action]

In the time synchronization method of the data transmission system according to the first and second inventions of this application, since the child clock is corrected by the data of the time difference between the parent clock and the child clock as described above, the correction operation need not be performed immediately. Can be done in between other actions.

In addition, reading the time of the master clock and slave clock to obtain the data of the time difference is performed in accordance with the code transmission and reception that is always performed, and is stored in the register.
The burden on the slave station co-processor is light, and it is not necessary to stop the flow of data transmission even in the case of a system that cyclically transmits data.

〔Example〕

FIG. 1 shows a time synchronization method for a data transmission system according to the present invention as a supervisory control and control method.
Data Acquisition (Supervisory Controd An
FIG. 3 is a diagram showing an example of time synchronization between a master clock installed in a master station of a d Data Acquisition (hereinafter referred to as SCADA) system and a slave clock installed in each slave station. In the figure, 0 is the master station of the SCADA system, 1, 2, ...
... is a child station. In the master station 0, the GP is each slave station 1,
2, Display panel that displays the status of, ...
2, a control console for issuing control commands, TW is a typewriter for recording operations and data, CPU ₀ is an arithmetic processing circuit, DO ₀ is an output circuit, DI ₀ is an input circuit, TC
Is a typewriter control circuit, MC is a master clock, RG ₀₁ , RG
₀₂ , ... Are registers, S ₀₁ , S ₀₂ , ... Are code transmission circuits, R ₀₁ , R ₀₂ , ... Are code reception circuits, and M ₀₁ , M ₀₂ ,.
... are modulation circuits, and D ₀₁ , D ₀₂ , ... are demodulation circuits.

In the slave stations 1 and 2, CPU ₁ and CPU ₂ are arithmetic processing circuits, D ₁ and D ₂ are demodulation circuits, M ₁ and M ₂ are modulation circuits, R ₁ and R ₂ are code reception circuits, and S ₁ and S ₂ is a code transmission circuit, DO ₁ and DO ₂ are output circuits, DI ₁ and DI ₂ are input circuits, LC ₁ and LC ₂ are child clocks, and RG ₁ and RG ₂ are registers.

L _1D , L _1U , L _2D , L _2U ... Are the master station 0 and each slave station 1, 2 ...
It is a data transmission line connecting ...

Next, the operation of FIG. 1 will be described with reference to FIG. 2 showing a time chart of codes transmitted and received between the master station 0 and the slave station 1.

First, a case where normal remote monitoring control and operation recording are performed will be described.

In FIG. 1, the arithmetic processing circuit CPU ₁ of the slave station 1 scans the state of the monitored contact (auxiliary contact of protective relay or breaker, etc.) input to the input circuit DI ₁ and stores the state. . Then, if there is a change in the state of the input contact, the address number of the contact and the new state are passed to the code transmission circuit S ₁ . The code transmission circuit S ₁ always transmits a code toward the master station 0. When the address of the state change contact and the new state data are received from the arithmetic processing circuit CPU ₁ , the code transmission circuit S ₁ transmits the code at that time. 0 in the next code frame of
And sends it to the modulation circuit M ₁ to be sent to. An example of the code transmitted by the code transmission circuit S ₁ is shown by S ₁ in FIG. In FIG. 2, D is a frame of the code, and F is a flag indicating a delimiter between the frames D. The pattern of the flag F is fixed, but the length of the frame D varies depending on the contents to be transmitted, including the length. In addition to the data to be transmitted, the contents are usually added with a control portion for ensuring transmission and reception and a code check portion. In addition, as an example of the code format, a high-level data link control (High-Level Data Link Co-ntrol, hereinafter HDLC)
There is that of Prosi-Jure.

Returning to FIG. 1, the modulation circuit M ₁ adapts the code received from the code transmission circuit S ₁ to the signal transmission path and is not easily affected by noise, for example, frequency shift keying (Frequency Shift Keying,
It is modulated into a signal (hereinafter referred to as FSK) and transmitted to the master station 0 via the signal transmission line L _1U . In the master station 0, the demodulation circuit D ₀₁ receives this and demodulates it into a DC pulse, and passes it to the code reception circuit R ₀₁ .

The code reaching the code receiving circuit R ₀₁ is similar to the transmission code S ₁ as indicated by R ₀₁ in FIG. 2, but delayed by the transmission delay time td.

Arithmetic processing circuit CPU ₀ master station 0 reads the received contents by an interrupt signal from a periodic scan or code receiving circuit R _01, if incoming data state change, updates the contents of its storage device The display on the display panel GP is changed via the output circuit DO ₀ . Further, the state change is recorded by the typewriter TW via the typewriter control circuit TC.

Arithmetic processing circuit CPU ₀ master station 0 input is also scanned from the control console CD via an input circuit DI _0, selection of the appliance of the slave station 1, and the corresponding device address is a command from the control,
A code transmission circuit S that encodes a state to be controlled (ON / OFF, etc.)
Give to ₀₁ . Code transmission circuit S ₀₁ is sending a code indicating the S ₀₁ of FIG. 2, the modulation circuit M ₀₁ put it in one frame, the transmission path L _1D, the slave station 1 via the demodulation circuit D ₁ It is transmitted to the code receiving circuit R ₁ . The arithmetic processing circuit CPU ₁ reads the received contents by periodic scanning or an interrupt signal from the code receiving circuit R ₁ , performs code checking and decoding, and gives a control command to the assigned device via the output circuit DO ₁ .

Since the above operation is exactly the same for the slave station 2, the description thereof is omitted. Further, the same additional configuration can be performed for the slave stations 3 and below (not shown) to perform exactly the same operation.

The above is the operation of normal distant monitoring control and operation recording. However, when the operation recording is performed by the master station 0, the data of the time when the state change occurs from each slave station 1, 2, ... without method but to record with a time of master clock MC to the order in which the arithmetic processing circuit CPU ₀ is confirmed in the master station 0 for no sign of protection devices and equipment operation data transmission device as the power system If it is much faster than the required transmission time, it is impossible to accurately determine the operation sequence when the data reaches the master station 0.

In order to solve this, each slave station 1, 2, ...
, C ₁ , LC ₂ , ... Are provided and synchronized with the master clock MC, and when a state change occurs, the slave clock LC ₁ ,
The time of LC ₂ , ... is also transmitted to the master station 0. That is,
When the contact input to the input circuit DI ₁ of the slave station 1 described above has a state change, the arithmetic processing circuit CPU ₁ includes the address number of the contact, the parent state, and the time of the slave clock LC _1. When the data is transmitted to the master station 0, the arithmetic processing circuit CPU ₀ of the master station 0 temporarily stores it in its own storage device, collects data from other slave stations for a certain period of time, and then sorts the data in the order of the added time and typewriter. The operator can know the correct operation time and its order by using the typewriter TW through the control circuit TC.

In this case, the master clock MC of the master station 0 and the slave clocks LC ₁ , LC ₂ , ... Of the slave stations 1, ₂ , ... Must be synchronized with considerable accuracy (for example, within a few milliseconds). The operation of this synchronization will be described below.

Once the arithmetic processing circuit CPU ₀ is a fixed time for the master station 0 (1 hour to 1 day by the accuracy of the atomic clock), each child watches _LC 1, LC
₂ , a time check command for checking the time is sent to each slave station 1, 2, via each code transmission circuit S ₀₁ , S ₀₂ , ....
..

The slave station 1 will be explained. First, as a normal operation, the code transmission circuit S ₁ gives a signal to the register RG ₁ a predetermined time ta before the start of code frame transmission, and then the register R 1
G ₁ repeats the operation of reading the time of the child clock LC _{1 at} the time when this signal arrives and storing it. Code transmission circuit S ₀₁ modulation circuit M ₀₁ When the calculation processing circuit CPU ₀ master station 0 issues a time survey command, the transmission path L _1D, the demodulation circuit D
₁ to the code receiving circuit R ₁ of the slave station 1. This operation is shown as D (TIQ) in the time chart of FIG.

When the calculation processing circuit CPU ₁ of the slave station 1 code receiving circuit _{R 1} is subjected to time survey command D (TIQ), but put the next蓄Wa the obtained data to the code frame to register RG _1, the register RG ₁ As shown in the upper part of S ₁ in FIG. 2, the data includes the time of the slave clock LC ₁ which is ta before the next frame (in this example, when the transmission of the previous frame is completed),
Letting this be T _S1 , in the next frame D (TAS), this T _S1 is used as the time data of the child clock LC ₁ for the code transmission circuit S.
₁ , the modulation circuit M ₁ , the transmission line L _1U , and the demodulation circuit D ₀₁ to the code reception circuit R ₀₁ of the master station 0.

The code arriving at the code receiving circuit R ₀₁ is the same as the transmission code S ₁ as indicated by R ₀₁ in FIG. 2 and is delayed by the transmission delay time td. When the code receiving circuit R ₀₁ completes the reception of the frame in which the time data of the child clock LC ₁ is carried, the time T _R0 of the parent clock MC at that time is read and stored in the register RG ₀₁ .

The arithmetic processing circuit CPU ₀ reads out the time data T _R0 stored in the register RG _01, and from this, the length tc of the code 1 frame which is known in advance + the time ta from the time reading of the slave clock to the code transmission + the transmission delay Subtract the total of time td to give the child clock estimated time T _S10.
S) The difference T from the child clock time T _S1 that arrives due to the frame
_{When S10-} T _S1 is taken, this becomes the time difference between the master clock 0 and the slave clock 1, and this is stored in its own storage device.

Next, the arithmetic processing circuit CPU ₀ uses the time difference as the slave clock correction data through the code transmission circuit S ₀₁ , the modulation circuit M ₀₁ , the transmission line L _1D , and the demodulation circuit D ₁ to receive the code reception circuit R ₁ of the slave station _1.
To transmit. The time chart of this operation is D in Fig. 2.
(TAJ).

Arithmetic processing circuit CPU ₁ of the slave station 1 is the code receiving circuit R ₁ receives the time correction data D (TAJ), reads the time of the atomic clock LC _1, this adds time correction data (code included) and , And sets the time of the child time LC ₁ to that time.

As a result, the time of the child clock LC ₁ is synchronized with the time of the parent clock MC.

The time synchronization can be performed for the child clocks LC ₂ ... Under the slave station 2 by exactly the same operation. The time correction data is transmitted to the slave station 1 by the arithmetic processing circuit CPU ₀ of the master station 0 in the opposite manner to the above.
The transmission delay time td at the time T _S1 of the child clock LC ₁ that has arrived
+ Time ta from reading the time on the child clock to sending the code ta + sign 1
Child clock estimated time T _R10, which is the sum of frame length tc
It is also possible to obtain it as a difference T _R10 −T _{R0 from} the time T _R0 of the master clock 0 at the time when the reception of the code frame arrived by multiplying the time by the child clock time T _S1 .

Since the time synchronization method according to the present invention can be applied to a data transmission system that constantly sends a code, the method is also mentioned in the embodiment, but other coding methods, for example, a constant code is not sent. Polling from the master station (Polli
It is needless to say that the present invention can be applied to a system in which each slave station transmits a code according to (ng).

Also in the configuration of the embodiment, for example, the register RG of the master station 0
_{If 01} , RG ₀₂ , ... Are individually provided as in the embodiment, the time adjustment operation of the child clock of each child station can be performed in parallel, but if one station is sequentially performed, one shared register is provided. It goes without saying that various configurations can be made such that the above can be sequentially used.

It should be noted that the transmission delay time td between the master station and each slave station is the folding test of the modulation / demodulation circuit when the data transmission system is installed, for example, the modulation circuit M ₀₁ , the demodulation circuit D ₀₁ of the master station 0 in FIG. The modulation circuit M ₁ and the demodulation circuit D ₁ of the slave station 1 are separated from the internal circuit, the output of the demodulation circuit D ₁ in the slave station ₁ is connected to the modulation circuit M ₁ , and the input code of the modulation circuit M ₀₁ of the master station 0 is input. It suffices to measure the time delay until a change appears in the output of the demodulation circuit D ₀₁ , measure it by dividing it by 2, etc., and store it as data in the storage device of the arithmetic processing circuit CPU ₀ of the master station 0.

In addition, the time adjustment operation is performed every time all digits (hour, minute, second,
There is no need to do this in milliseconds),
At the time of device startup or at long-term cycle, up to seconds are corrected (or absolute time is transmitted to set the time of the child clock), and the millisecond correction is made once an hour. It is possible to reduce the bit length of.

〔The invention's effect〕

As described above, according to the first and second inventions of this application, the time data of the child clock is collected in accordance with the code transmission / reception operation of the data transmission system, and the correction operation is performed based on the time with the master clock regardless of the absolute time. Since the correction is made based on the difference data, the operation processing circuit of the data transmission system is not interrupted in operation and does not impose a heavy burden, and the time can be corrected while maintaining the flow even in the case of constant cyclic transmission.
Even if there is a difference in delay time between the upper and lower transmission lines, there is an effect that time synchronization can be reliably established.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a time synchronization method of a data transmission system according to the present invention in a SCADA system, and FIG. 2 is a diagram showing codes transmitted and received between a master station 0 and a slave station 1 in FIG. It is explanatory drawing which shows an example. 0 is a master station, 1, 2, ... are slave stations, CPU ₀ is an arithmetic processing circuit, MC is a master clock, RG ₀₁ , RG ₀₂ , ... are registers,
S ₀₁ , S ₀₂ , ... Are code transmitting circuits, R ₀₁ , R ₀₂ , .. are code receiving circuits, CPU ₁ , CPU ₂ , ... Are arithmetic processing circuits, LC ₁ , LC ₂ ,. , RG ₁ , RG ₂ ,
... is a register, R ₁ , R ₂ , ... is a code receiving circuit, S
₁ , S ₂ , ... Are code transmission circuits, L _1D , L _1U , L _2D , L
_2U , ... is a transmission line connecting the master station 0 and the slave stations 1, 2 ,.

Continuation of front page (56) Reference JP-A-60-109347 (JP, A) JP-A-60-2220915 (JP, A) JP-A-60-214291 (JP, A)

Claims (2)

[Claims] 1. A method in a data transmission system for bidirectionally transmitting data between a master station and a slave station, comprising: a slave clock installed in the slave station and a master clock installed in the master station. In the time synchronization method of the data transmission system for synchronously synchronizing, the slave station is, in advance, from the break point of the frame of the code transmitted toward the master station in response to the slave clock time check command from the master station. The time (T _S1 ) of the child clock before the defined fixed time (ta) is transmitted as data in the frame following the delimiter, and the master station starts from the time (T _R0 ) of the reception completion time of the frame. 1 frame length (tc) + the fixed time (t
a) + Subordinate clock estimated time (T _S10 ) is calculated by subtracting the sum of transmission delay time (td), and the estimated sub clock time (T _S10 ) and the _sub clock time (T _S1 ) received from the slave station. Difference time (T _S10 −T _S1 ) is transmitted as time correction data to the slave station, and when the slave station receives the time correction data, the difference time (T _S10 −T _S1 ) is received at the time. A time synchronization method for a data transmission system, characterized in that the child clock is synchronized with the parent clock by adding and correcting. 2. A method in a data transmission system for bidirectionally transmitting data between a master station and a slave station, comprising a slave clock installed in the slave station and a master clock installed in the master station. In the time synchronization method of the data transmission system for synchronously synchronizing, the slave station is, in advance, from the break point of the frame of the code transmitted toward the master station in response to the slave clock time check command from the master station. The time (T _S1 ) of the child clock before the predetermined fixed time (ta) is transmitted as data in the frame following the break, and the master station receives the time (T _S1 ) of the child clock received from the slave station. ), The transmission delay time (td) + the fixed time (ta) +1
Estimated time of child clock (T plus total of frame length (tc))
_R10 ), and the time (T _R10 ) at which the slave clock is estimated and the time (T _S1 ) when the slave clock is received from the slave station (T _S1 ) is completed.
_R0 ) and the time difference (T _R0 −T _R10 ) is transmitted as time correction data to the slave station, and when the slave station receives the time correction data, the time difference (TR ₀ −T _R0 − T _R10 ) is added and corrected to synchronize the child clock with the master clock.