JPH06187193A - Program debugging device and microcomputer - Google Patents

Abstract

PURPOSE:To provide a debugging device in which only trace information necessary on debugging is stored in a trace memory. CONSTITUTION:A program debugging device in which the debugging of a program executed by a microcomputer 11 is performed is equipped with a branching execution address storage memory 17 which discriminates whether or not an instruction executed by the microcomputer 11 is the branching instruction, and outputs a branching instruction execution signal 29 when it is the branching instruction, and an address control circuit 18 which inputs the branching instruction execution signal 29, and allows a trace memory 12 to store only the branching instruction and the instruction of a prescribed steps before and after the branching instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program debugging device for debugging a program executed by a microcomputer, and a microcomputer suitable for debugging the program.

[0002]

2. Description of the Related Art As a conventional debug device, for example,
Information indicating the execution status such as execution address, status information, and read / write data (hereinafter referred to as “trace information”) is sequentially stored in the trace memory, and the stored trace information is displayed on the display to display the microcomputer. There is known a format in which debugging work is performed by checking the execution status.

FIG. 6 is a block diagram schematically showing a configuration example of a trace circuit 60 in a conventional debug device.

In FIG. 1, a microcomputer 11
Outputs the bus information 21. This bus information 21
Is composed of an address, data, and status information (read, write, etc.).

The comparator circuit 13 includes an external logic signal 22 and bus information 21 output from an external target circuit.
Enter. Then, these signal values are compared with the preset values stored in advance, and when they match, the trace memory 1
The control signal 26 for instructing to start or stop the storage of the trace information in 2 is output.

The write strobe generation circuit 14 inputs the status information 23 of the bus information 21, and the write strobe signal 24 which is a signal for giving a write timing of the bus information 21 to the trace memory 12 is triggered by this status. To generate. This write strobe signal 2
4 is sent to the write strobe control circuit 15.

The write strobe control circuit 15 inputs the above-mentioned control signal 26 from the comparison circuit 13 together with the write strobe signal 24, enables the write strobe signal 24 during the trace execution, and outputs it as the trace write strobe signal 25. On the other hand, while the trace is stopped, the write strobe control circuit 15 disables the input write strobe signal 24.

The address control circuit 16 generates and outputs an address signal 27 for designating an address when writing bus information in the trace memory 12. An address incrementer (not shown) is provided inside the address control circuit 16, and the write strobe control circuit 1 is provided.
Every time the trace write strobe signal 25 is input from 5, the address value indicated by the address signal 27 is incremented by "1". Further, control such as clearing is performed by a control signal input from the comparison circuit 13.

The trace memory 12 has a data input terminal 2
The bus information 21 input from a is transferred to the write signal input terminal 12
According to the timing of the trace write strobe signal 25 input from b, the trace write strobe signal 25 is stored in the address designated by the address signal 27 input from the address input terminal 12c.

The bus information (trace information) 21 stored in the trace memory 12 is displayed by a display device (not shown) during debugging.

In such a debug device, the comparison circuit 1
All the bus information (trace information) 21 output from the microcomputer 11 is stored in the trace memory 12 from the start to the stop of the trace by the control signal output from the microcomputer 3. That is, all the processing contents executed by the microcomputer 11 from the start to the end of the trace are stored in the trace memory 12.

[0012]

When a user performs a program debugging operation of the microcomputer 11 by using such a debugging device, the microcomputer 1
All the processing executed by 1 (that is, trace memory 1
It is rare to check all of the contents stored in 2), and normally an operation involving branching of an execution address, such as a jump instruction, a call instruction, a return instruction or an interrupt instruction (hereinafter simply referred to as “branch operation”) It is enough to check only before and after the instruction related to As described above, when it is desired to check only the branching operation, conventionally, the check is performed while searching for the corresponding portion from the trace information displayed on the display.

Therefore, in the conventional debug device, most of the trace information stored in the trace memory 12 is information that is not used during debugging.
The utilization efficiency of 2 was very poor.

Further, since the amount of information that is not checked is much larger than the amount of information that is checked, it is difficult for the user to find the check location, and thus the efficiency of the debugging work is poor. In addition, since the user can easily overlook the check point as described above, there is a high possibility that the user will overlook the check point even if the program has a bug.

On the other hand, by appropriately selecting the set value of the comparison circuit 13, it is possible to store only before and after the branch operation in the trace memory 12. However, when specifying a part such as a jump instruction in this way, only a few parts or tens of parts can be specified for the reason of cost, etc. It is virtually impossible to specify.

The present invention has been made in view of such drawbacks of the prior art, and is used in a debug device capable of storing only trace information necessary for debugging in a trace memory and such a debug device. It is an object of the present invention to provide a microcomputer.

[0017]

[Means for Solving the Problems]

(1) A program debug device according to the first invention is a program debug device for debugging a program executed by a microcomputer, and determines whether or not the execution of the microcomputer is a branch operation. In the case of a branch operation, a determination means for outputting a branch execution signal and a storage means for storing only this instruction and an instruction of a predetermined step before and after the instruction when the branch execution signal is input are provided. It is characterized by (2) A program debug device according to a second aspect of the invention is a program debug device for debugging a program executed by a microcomputer, and when a branch execution signal is input, this instruction and before and after this instruction. It is characterized in that it is provided with a storage means for storing only an instruction of a predetermined step. (3) A microcomputer according to a third aspect of the invention is the microcomputer used in the program debug device according to the second aspect of the invention, wherein it is determined whether the execution is a branch operation, and if it is a branch operation. Is equipped with a discrimination means for outputting a branch execution signal.

[0018]

According to the present invention, the discriminating means discriminates whether or not the execution of the microcomputer is a branching operation, and when it is the branching operation, the branching execution signal is outputted and the storing means inputs the branching execution signal. In this case, by storing only the instruction relating to this operation and the instruction at a predetermined step before and after this instruction, it becomes possible to trace only the instruction relating to the branch operation and the instruction at a predetermined step before and after this instruction.

[0019]

【Example】

(Embodiment 1) An embodiment of the debug device according to the first invention will be described.

FIG. 1 is a block diagram schematically showing a configuration example of the trace circuit 10 in the debug device according to the present embodiment. In the figure, the components denoted by the same reference numerals as those in FIG. 6 are the same as those in FIG.

The branch execution address storage memory 17 has an address corresponding to the address of the execution instruction of the microcomputer 11, and can store 1-bit data for each address. Then, in association with each execution instruction of the microcomputer 11, information on whether or not this instruction is accompanied by a branch operation (jump instruction, call instruction, return instruction, interrupt instruction, etc.) is stored. Here, it is assumed that "1" is stored when the instruction at the address is accompanied by a branch operation, and "0" is stored when the instruction at the address is not accompanied by the branch operation.

The program development language execution circuit 32 determines whether or not each instruction executed by the microcomputer 11 is accompanied by a branch operation, and if there is an instruction accompanied by a branch operation, outputs the address of the instruction. To do. For example, by using, as the circuit 32, a circuit using a program development language that can also judge whether or not the instruction is accompanied by a branch operation when the program is assembled, Can make decisions.

The branch information writing circuit 19 stores data in the branch execution address storage memory 17 according to the address information input from the program development language execution circuit 32. That is, the branch information writing circuit 19 stores "1" in the address corresponding to the address information input from the program development language execution circuit 32 in the branch execution address storage memory 17, and stores "1" in other addresses. 0 ”is stored. The storage of data in the branch execution address storage memory 17 by the branch information writing circuit 19 as described above is carried out in advance before tracing.

It should be noted that instead of using the program development language execution circuit 32, the user himself / herself determines whether or not each instruction is an instruction related to a branch operation from the program list and sets the branch execution address storage memory 17. The branch information writing circuit 19 may be configured.

When the address information 28 is input from the microcomputer 11, the branch execution address storage memory 17 described above checks the value of the bit corresponding to this address. If this bit is "1", the branch execution signal 29 is output from the output circuit (not shown) to the address control circuit 18.

The address control circuit 18 generates an address signal 27 for designating a write address of the trace memory 12. The address value indicated by the address signal 27 is incremented by "1" each time the trace write strobe signal 25 is input from the write strobe control circuit 15, but from the initial address to a predetermined address (here, 2).
n), this initial address (ie 2
Return to n previous address). Then, when the branch execution signal 29 is input from the branch execution address storage memory 17, after sequentially outputting n address signals 27 added by “1” according to the trace write strobe signal 25,
A value indicating the {initial address + (2n + 1)} th address is output. The same operation is repeated using this address as the initial address. The point that control such as clearing is performed by the control signal 26 input from the comparison circuit 13 is the same as the address control circuit 16 of the above-described conventional debug device (see FIG. 6).

Next, the procedure of the storing operation in the trace memory 12 when the debug device of this embodiment is used will be described. FIG. 2 is a conceptual diagram for explaining such an operation.

As shown in FIG. 2A, in this embodiment, the storage area of the trace memory 12 is divided into a plurality of blocks A, B, C ,. Here, each block has 2n + 1 addresses.

The bus information when the microcomputer 11 first executes the instruction is stored in the address 1 (block A). Further, the bus information about the instructions executed after the second time is also sequentially stored at the second address and thereafter.

Next, all the addresses (1
When the storage of the bus information in the addresses 2n + 1) is completed,
The next bus information will be stored again at address 1 (
The bus information previously stored at address 1 is deleted). Then, the bus information after that is also stored sequentially from the second address. Such an operation is repeated until the microcomputer 11 executes the instruction related to the branch operation.

Here, if the instruction executed by the microcomputer 11 involves a branching operation, the subsequent n
Similar to the case described above, the individual pieces of bus information are sequentially stored at the addresses in the block A. Even when the bus information is stored in the address 2n + 1 after the branch operation is executed and before the n pieces of bus information are stored, the remaining bus information is restored from the address 1 as in the case described above. I do.

When the storage of n pieces of bus information after the branch operation is completed, each address (2
The data is sequentially stored in the addresses (n + 2 to 4n + 2).

For example, as shown in FIG. 2B, the number of address areas in one block is 17 (that is, n = 8).
Assuming that the bus information to be stored in the 12th address is for the instruction related to the branch operation, after storing the bus information related to this instruction in the 12th address, the subsequent 8 bus information are the 13th address to the 17th address. And the first to third addresses are sequentially stored, and the ninth and subsequent bus information are sequentially stored at the 18th to 34th addresses.

Then, the storage in each address of the block B is repeated until the microcomputer 11 next executes the instruction relating to the branch operation. When the instruction related to the branch operation is executed, as in the case described above, after storing n pieces of bus information, the storage in each address of the block C is continued.

Similarly, the bus information is sequentially stored in each block until the trace is stopped.

As described above, according to the debug device of the present embodiment, only the instruction relating to the branch operation and the trace information (bus information 21) of n bits before and after this are trace memory 1.
2 can be stored.

(Embodiment 2) Next, an embodiment of the debug device according to the second invention and the microcomputer according to the third invention will be described.

FIG. 3 is a block diagram schematically showing a configuration example of the trace circuit 30 in the debug device according to the present embodiment. In the figure, the components denoted by the same reference numerals as those in FIGS. 1 and 6 are the same as those in these figures.

In this embodiment, the microcomputer 31
Outputs a branch execution signal 29 which is a signal indicating that there is an instruction related to the branch operation.

FIG. 4 is a block diagram schematically showing a configuration example of the microcomputer 31. The microcomputer 31 outputs an instruction decoder 41 which outputs a branch operation decode signal 43 when an instruction relating to a branch operation is stored, and an interrupt acceptance signal 44 which outputs an interrupt acceptance signal 44 when an interrupt request is made in an interrupt enabled state. Included acceptance circuit 4
2 and. Then, the branch operation decode signal 43
And the interrupt acceptance signal 44 is input to the OR circuit 45. The OR circuit 45 outputs the branch execution signal 29 when the branch operation decode signal 43 or the interrupt acceptance signal 44 is on.

The branch execution signal 29 is transmitted to the address control circuit 18 via the comparison circuit 13.

The address control circuit 18 is the same as the first embodiment.
Similarly to the address control circuit in, the address signal 27 for designating the write address of the trace memory 12 is generated. The address value indicated by the address signal 27 is incremented by "1" each time the trace write strobe signal 25 is input from the write strobe control circuit 15, but from the initial address to a predetermined address (here, 2n
When it increases, it returns to the initial address. When the branch execution signal 29 is input, n address signals 27 are sequentially output according to the trace write strobe signal 25, and then a value indicating the {initial address + (2n + 1)} th address is output. The same operation is repeated for the initial address.

By using the trace circuit 30 and the microcomputer 31 having such a configuration, as in the above-described first embodiment (see FIG. 2), only the instruction relating to the branch operation and the trace information before and after this are traced. It can be stored in the memory 12.

Here, the structure of the microcomputer 31 is not limited to that shown in FIG. 4, and the structure may be such that the branch execution signal 29 is output when there is an instruction related to the branch operation. Can be used if

FIG. 5 shows another configuration example of the microcomputer 31. The microcomputer 31 employs a pipeline processing method, and internally outputs an instruction buffer 51 and a cue flash signal 53 which is a signal for clearing an instruction stored in the instruction buffer when executing a branch operation. And an instruction decoder 52 for Then, the cue flash signal 53 is converted into the branch execution signal 29.
As an external output. This branch execution signal 29 can be traced using the debug device of this embodiment by being taken into the address control circuit 18 via the comparison circuit 13 (see FIG. 3).

In the first and second embodiments described above, the number of instructions stored in the trace memory 12 may be different before and after the instruction relating to the branch operation. Is of course.

[0047]

As described in detail above, according to the present invention, a debug device capable of storing only trace information necessary for debugging in a trace memory and a microcomputer used in such a debug device are provided. Can be provided.

Therefore, the storage capacity of the memory of the debugging device can be reduced, so that the cost can be reduced and the efficiency of the debugging work can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing a configuration example of a trace circuit in a debug device according to an embodiment of the first invention.

2A and 2B are conceptual diagrams for explaining a storage operation in a trace memory when the debug device shown in FIG. 1 is used.

FIG. 3 is a block diagram schematically showing a configuration example of a trace circuit in a debug device according to an embodiment of the second invention.

FIG. 4 is a block diagram schematically showing a configuration example of a microcomputer according to a third invention.

FIG. 5 is a block diagram schematically showing another configuration example of the microcomputer according to the third invention.

FIG. 6 is a block diagram schematically showing a configuration example of a trace circuit in a conventional debug device.

[Explanation of symbols]

 10, 30, 60 Trace circuit 11, 31 Microcomputer 12 Trace memory 13 Comparison circuit 14 Write strobe generation circuit 15 Write strobe control circuit 16, 18 Address control circuit 17 Branch execution address storage memory 19 Branch information writing circuit 21 Bus information 22 External logic signal 23 Status information 24 Write strobe signal 25 Trace write strobe signal 26 Control signal 27 Address signal 28 Address information 29 Branch execution signal 41, 52 Instruction decoder 42 Interrupt acceptance circuit 43 Branch operation decode signal 44 Interrupt acceptance signal 45 OR Circuit 51 Instruction buffer

Claims (8)

[Claims] 1. A program debug device for debugging a program executed by a microcomputer, wherein execution of the microcomputer involves branching of an execution address (hereinafter, "branch operation"). And a determining means for outputting a branch execution signal in the case of a branch operation, and a storage means for storing only this instruction and an instruction of a predetermined step before and after this instruction when the branch execution signal is input. A program debugging device comprising: 2. A branch execution address storage memory for storing whether or not each instruction executed by the microcomputer is an instruction relating to a branch operation, and a content stored in the branch execution address storage memory. 2. The program debug device according to claim 1, further comprising: an output unit that outputs the branch execution signal when the instruction corresponding to the input address information is related to a branch operation. 3. A program for determining whether or not each instruction executed by the microcomputer is an instruction relating to a branch operation and, if the instruction is an instruction relating to a branch operation, outputting the address of the instruction. 3. The program debug device according to claim 2, further comprising: a development language executing means; and branch information writing means for writing a judgment result in the branch execution address storage memory. 4. When the memory means does not input the branch execution signal, the storage area is repeatedly and sequentially stored in a storage area of a predetermined step in the memory, and when the branch execution signal is input, subsequent predetermined steps are performed. 4. An address control means for designating a storage address of the memory is provided so as to store the instruction of the above in another storage area after storing the instruction. Program debug device. 5. A program debug device for debugging a program executed by a microcomputer, which stores only this instruction and instructions at predetermined steps before and after this instruction when a branch execution signal is input. A program debug device comprising means. 6. When the storage means does not input the branch execution signal, the storage area is repeatedly and sequentially stored in a storage area of a predetermined step in the memory, and when the branch execution signal is input, subsequent predetermined steps are performed. 6. The program debug device according to claim 5, further comprising address control means for designating a storage address of the memory so that the instruction is stored in another storage area after storing the instruction. 7. A microcomputer used in the program debug device according to claim 4, wherein it is determined whether or not an instruction to be executed is accompanied by a branch operation, and if it is a branch operation, branch execution is performed. A microcomputer provided with a discrimination means for outputting a signal. 8. The microcomputer according to claim 7, wherein said discriminating means outputs a queue flash signal for clearing the instruction stored in the instruction buffer at the time of branch as the branch execution signal.