JPH0618976U - Waveform storage - Google Patents

Abstract

(57) [Summary] [Purpose] Writing a complicated waveform acquisition memory dedicated to roll mode to a circuit of a normal sampling structure in a method of sequentially acquiring and displaying waveform data by low-speed sampling such as roll mode in a waveform storage device. It is an object to realize low-speed sampling such as roll mode without adding a read circuit. [Configuration] A memory for AD-converting an input signal with a high-speed clock and a circuit for dividing the high-speed clock and a circuit for dividing the high-speed clock and stopping the memory operation at the timing of the divided clock to read one data of the memory and display system And a circuit for starting the memory storage operation.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to improvement of low-speed sampling in a waveform storage device such as a digital oscilloscope.

[0002]

[Prior art]

 Conventionally, low-speed sampling such as roll mode has been performed with a hardware configuration as shown in Fig. 3, for example. This operation will be described with reference to the time chart of FIG. A sampling clock A is output from the clock frequency dividing circuit 4, the input signal is digitized by the AD converter 1, and stored in the serial memory 2. The write clock K at this time is the same signal as the sampling clock A. The waveform in the second row of FIG. 4 shows the write address of the serial memory 2, and the data is written at the address n at the rising edge of the sampling clock A. At the rising edge of the sampling clock A, an interrupt signal is input from the output B of the flip-flop 7 to the CPU 3. The CPU 3 transfers the data at address n (data sampled this time) to the read / display block 5 at the timing of the read signal M as shown in the fourth and fifth rows of FIG. Then, the signal C resets the flip-flop 7, and waits for the next sample. As described above, the data is transferred to the display block for each sampling and the roll-like waveform is displayed. At the start of sampling, the internal address (write address, read address) of the serial memory 2 must be initialized, but the read reset and write reset are simultaneously performed by the address reset signal J by the memory reset circuit 10 and initialized. Another conventional example is to use a RAM instead of the serial memory 2 in FIG. 3 (not shown), but manages the address when writing and the address when reading as in the above. I have to go. The operation is similar because the address counter is built-in or externally configured.

[0003]

In the above-described conventional technique, the control circuit is complicated because the write address and the read address of the memory must be the same address to perform the write operation and the read operation. In addition, switching between the normal sampling control other than the roll mode and the above control also complicates the circuit. The purpose of the present invention is to eliminate these drawbacks and realize a low-speed sampling method such as roll mode with a simpler circuit configuration.

[0004]

[Means for Solving the Problems]

 In order to achieve the above object, the present invention shifts the memory by setting the clock of the AD converter and the write clock of the memory higher than the originally required sampling frequency, and commonizing the write clock and read clock of the memory. It is used as a register and interrupts the CPU at the sampling clock cycle to stop the write clock of the AD converter and memory.

[0005]

[Action]

 As a result, since the waveform data immediately before the sampling clock is packed in the memory that stopped the storage operation at each sampling clock, when the CPU reads 1 data, even if there is a certain address interval, the sampling clock You can get the data synchronized with.

[0006]

【Example】

 An embodiment of the present invention will be described below with reference to FIG. 1 (block diagram) and FIG. 2 (time chart). 1 is an AD converter, 2 is a serial memory, 3 is a CPU, 4 is a clock generation circuit, 5 is a display block, 6 is a CRT, 7 is a flip-flop, and 8 is a clock switching circuit. A high-speed clock G and a sampling clock A (low-speed clock) are output from the clock generation circuit 4. The input signal is digitized by the AD converter 1 by the high-speed clock G and stored in the serial memory 2. The flip-flop 7 is set by the sampling clock A, and the interrupt signal B is output to the CPU 3. The CPU 3 switches the switching signal E of the clock switching circuit 8 by this interrupt signal B 1 to switch the write and read clock D of the serial memory from the high speed clock G side to the read signal F side. In response to the read signal F, the CPU 3 reads one data in the serial memory 2 through the data bus H and transfers it to the display block 5 as display data. Next, the CPU 3 switches the switching signal E to switch the read / write clock D of the serial memory to the high speed clock G side. The CPU 3 outputs the flip-flop reset signal C, resets the flip-flop, and waits for an interrupt. In the same way, the data synchronized with the sampling clock is sequentially obtained.

[0007]

[Effect of device]

 According to the present invention, a complicated control circuit (write clock, read clock control, etc.) for special write address and read address of the memory is not required, and the roll mode is not added to the normal sampling circuit. Slow sampling such as can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart of FIG.

FIG. 3 is a block diagram showing an example of a conventional technique.

FIG. 4 is a time chart of FIG.

[Explanation of symbols]

 1 AD converter 2 Serial memory 3 CPU 4 Clock generation circuit 5 Display block 6 CRT 7 Flip-flop 8 Clock switching circuit

Claims (1)

[Scope of utility model registration request] 1. A memory having a clock generation circuit and a circuit for dividing the frequency of the clock, the memory storing an input signal with a clock having a frequency faster than the frequency division clock, and a storage clock of the memory at the timing of the frequency division clock. A waveform storage device having means for stopping and reading.