JPH0619633A - Signal processing system in duplex system - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] C
1 command transmission and data transfer from PU to each channel
The system bus occupancy rate will be reduced to improve overall performance. [Structure] A CPU 10 is provided with a DMA means 101, is connected via a system bus 2, and is a dual channel 3.
Means 301, 4 for setting active / standby mode to 0, 40
01 and channel identifier setting means 302 and 402 are provided,
Address setting means 303 and 403 are provided for each channel. When writing from the CPU, set the same address on channels 30 and 40, and set different addresses when reading. Only the working channel performs the confirmation response to the bus 2 after writing the command or data, and the confirmation response to the CPU 10 at the completion of reception of the command or data is performed by both the working and standby channels using their own identifiers. The configuration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing system in a dual system in which, for example, a CPU and a channel are connected by a system bus, and the channel is duplicated to improve reliability of an electronic computer.

[0002]

2. Description of the Related Art One of the means for improving the reliability of electronic computers
One is the duplication system. In this method, for example, a file channel is duplicated with respect to the CPU, and normally one file channel is used, and when the file channel is abnormal, the other file channel is used.

FIG. 7 shows a specific example of the prior art in which the file channels are duplicated. This figure shows an example in which a file channel and a hard disk are duplicated in an electronic computer system. 1 is a CPU, 2 is a system bus, 3 and 4 are file channels, and 5 and 6 are hard disks.

In the CPU 1, 11 is a processor, 12 is an internal bus, 13 is a main memory, and 14 is a system bus interface. Further, the file channels 3 and 4 have the same configuration, and the file channel 3 includes a processor 31, an internal bus 32, a buffer memory 33,
System bus interface 34, DMA (Direct Mem
ory Access) controller 35, ROM 36 for storing operation program of processor 31, SCSI (Small Comp
I / O interface 3 such as computer system interface)
Similarly, the file channel 4 is also composed of a processor 41, an internal bus 42, a buffer memory 43, a system bus interface 44, a DMA controller 45, and an R.
It is composed of an OM 46 and an I / O interface 47.

In such a configuration, when the data in the main memory 13 is written to the hard disks 5 and 6, both the hard disks 5 and 6 are written, and the contents written to these hard disks 5 and 6 are Always match. On the other hand, when the contents written in the hard disks 5 and 6 are read out to the main storage unit 13 of the CPU 1, one of the hard disks 5 and 6 is set as the active side and the other is set as the standby side. The data is read from the hard disk on the standby side when there is an abnormality on the active side. Since the probability that the two hard disks 5, 6 will become abnormal at the same time is extremely small, the reliability can be improved by adopting such a method.

The operation of writing the contents of the main memory 13 into the hard disks 5 and 6 is specifically performed as follows. First, the CPU 1 commands the file channels 3 and 4 to write from the main storage unit 13 to the hard disks 5 and 6. Specifically, the processor 11 sends a command, and this command is sent from the system bus interface 14 to the file channels 3 and 4 via the system bus 2, and on the file channel 3 side,
The above command is written in the buffer memory 33 via the system bus interface 34. On the file channel 4 side, the data is written in the buffer memory 43 via the system bus interface 44.

As a result, the processor 31 on the file channel 3 side decodes the command written in the buffer memory 33, and when it knows that the command is a write command from the main memory 13 to the hard disk 5, it activates the DMA controller 35. Then, the data in the main memory 13 is transferred to the buffer memory 33. Then, the processor 31 activates the DMA of the I / O interface 37 to transfer the data from the buffer memory 33 to the hard disk 5.

Upon completion of this data transfer, the processor 31 stores the command end information in the buffer memory 33, activates the DMA controller 35, and transfers the command end information to the main memory unit 13.

On the other hand, also on the side of the file channel 4,
Similar to the file channel 3 side, the processor 41
After the data is transferred from the main memory 13 to the buffer memory 43, the data is transferred from the buffer memory 43 to the hard disk 6. After the data transfer is completed, the processor 41 stores the command end information in the buffer memory 43, activates the DMA controller 45, and transfers the command end information to the main storage unit 13.

The CPU 1 judges that the data writing from the main memory 13 to the hard disks 5, 6 is completed only after receiving the completion information from both the file channels 3, 4.

The above is the procedure for writing data from the main storage unit 13 of the CPU 1 to the hard disks 5, 6.
The procedure for reading data from the hard disks 5, 6 to the main storage unit 13 is performed as follows.

Here, assuming that the file channel 3 and the hard disk 5 are on the active side and the file channel 4 and the hard disk 6 are on the standby side, the CPU 1 sends a command only to the active side and does not send to the standby side. However, if the termination information from the working side is abnormally terminated, or if the termination information of the working side cannot be received, a similar read command is immediately issued to the standby side, and the standby side replaces the working side. To substitute the reading process.

[0013]

Although such a duplex system has an advantage that reliability can be improved, the signal processing method in the above-mentioned conventional duplex system has the following problems.

That is, in the conventional method, the command transmission from the CPU 1 to the file channels 3 and 4 and the data transfer from the main storage unit 13 of the CPU 1 to the buffer memories 33 and 43 of the file channels 3 and 4 are performed twice respectively. Since the disk access performance is reduced and the occupancy rate of the system bus 2 is increased as compared with the case where the redundancy is not provided, there is a problem that the performance of the entire computer system is reduced.

In the present invention, even when duplexing is performed,
Command transmission from the CPU to each channel and data transfer from the main memory in the CPU to the buffer memory of each channel only have to be done once, and the system bus occupancy rate is reduced to improve overall system performance. It is an object of the present invention to realize a signal processing method in a duplex system capable of achieving the above.

[0016]

FIG. 1 is a block diagram for explaining the principle of the present invention.
40 is connected by the system bus 2, and channels 30 and 40 are duplicated with respect to the CPU 10.

The CPU 10 has the DMA means 101, the channels 30 and 40 are mode setting means 301 and 401 for setting the active mode and the standby mode, and an identifier (IDentifir) for identifying each channel.
e, hereinafter referred to as ID), ID setting means 302 for setting
402, and address setting means 303, 403 for setting two different addresses for writing and reading to a buffer memory (not shown) provided in the channels 30, 40.

Then, the channels 30 and 40 are set by the mode setting means 301 and 401 to determine whether they are the active side or the standby side. Here, the channel 30 is the active side and the channel 40 is the standby side. . In addition, the channels 30 and 40 set IDs for channel identification by the ID setting means 302 and 402, respectively, and the address setting means 303 and 403 set the writing addresses so that the channels 30 and 40 have the same address. The address for reading is set to be different for the channels 30 and 40.

[0019]

After the above setting, the data stored in the main storage unit (not shown in FIG. 1) of the CPU 10 is connected to the channels 30 and 40 by the data storage means (see FIG. 1). The operation of writing to (not shown) is performed as follows.

A command is sent from the CPU 10 to the channel 30 via the system bus 2, and the command is written to the channel 30. The writing addresses are the same for both channels 30 and 40. Therefore, the above command is simultaneously written to the channel 40. At this time, the channel 40 is on the standby side, and the acknowledgment on the system bus 2 for writing by the CPU 10 is not output from this channel 40, and only the channel 30 on the active side acknowledges on the system bus 2. I do. Then, after receiving the command, the channels 30 and 40 notify the CPU 10 of the response that data reception is possible from the channels 30 and 40 by using their own IDs.

As a result, the CPU 10 causes the DMA means 10 to operate.
1 is used to send data from the main storage unit to the channel 30 and write it in the buffer memory of the channel 30. The data is also written in the buffer memory of the channel 40 in the same manner as the above command. Then channels 30, 40
Transfers the written data to the data storage means connected to each channel. And channel 30,
40 notifies the CPU 10 of the processing completion message using its own ID.

On the other hand, when the CPU 10 reads the above data, the read command from the CPU 10 is simultaneously written to both the channels 30 and 40. Then, the data in the data storage means connected to each of the channels 30 and 40 is transferred to the corresponding channel, but the data transfer from the channel to the CPU 10 is performed on the working channel 30.
Only do. If there is an abnormality in the active channel 30, the standby channel 40 is read.

Therefore, even in the case of duplexing, C
1 command transmission and data transfer from PU to each channel
It only needs to be turned.

[0024]

EXAMPLES Examples of the present invention will be described below. FIG. 2 is a block diagram showing a first embodiment of the present invention, and the same parts as those in FIG. 1 are designated by the same reference numerals. Also in this example,
An example in which a file channel is used as a channel is shown. The basic configuration is the same as that in FIG. 7 in which the conventional method is described, but the difference from FIG.
DMA controller 15 (corresponding to CPU 1 in FIG. 7)
And the system bus interface 3 of channels (which will be described as file channels in the embodiment) 30 and 40 (corresponding to the file channels 3 and 4 in FIG. 7).
4 and 44 are configured as shown in FIG. 3, and the other components are the same as those in FIG. 7, and therefore, the same parts are denoted by the same reference numerals, and the description of the functions and the like is omitted. The system bus interfaces of the file channels 30 and 40 in FIG. 2 will be described below as system bus interfaces 341 and 441.

The system bus interface 341,
As shown in FIG. 3, 441 is a receiver 51, 52, 53 of the system bus 2, a driver (nand gate) 54 of the system bus 2, a mode / ID setting register 55, an inverter 56, an address comparator 57, a NAND gate 58, a selector 59. , Address setting devices 60 and 61. In such a configuration, the system bus interfaces 341, 441 are different from the conventional system bus interfaces 34, 44 in a portion surrounded by a dotted line in FIG. 3, that is, the mode / ID setting register 5
5, inverter 56, NAND gate 58, selector 5
9. The configuration is such that an address setter 60 is added.

In FIG. 3, S1 is a data signal of the system bus 2, S2 is an address signal of the system bus 2, S3 is a write signal of the system bus 2, S4 and S7 are response signals of the system bus 2, and S5 is an ID. A signal, S6, is a buffer memory selection signal.

In such a configuration, the processor 11 of the CPU 10 first sets the mode / ID setting register 55 of the file channels 30 and 40 in the initial processing.
Set. Here, the mode / ID setting register 55 is specifically configured as shown in FIG. That is, the 8 bits from the 0th bit to the 7th bit are
As the ID setting bit that constitutes the ID, the 1st of the 15th bit
The bit is the mode setting bit M.

The mode setting bit M sets whether the file channel is the active file channel or the standby file channel. The mode setting bit M is "1".
When it is "0", it is the active side, and when it is "0", it is the standby side.

Here, since the file channel 30 is on the active side, the system bus interface 341 is used.
The mode setting bit M of the mode / ID setting register 55 on the (file channel 30 side) is set to "1", and the mode setting bit M of the mode / ID setting register 55 on the bus interface 441 (file channel 40 side) is set to "0". deep. This mode / ID setting is CPU
This is done by setting 10 in the program.

In addition to the above mode / ID setting, the addresses of the address setters 60 and 61 of the system bus interfaces 341 and 441 are also set in advance. In Figure 3,
The address setters 60 and 61 are supposed to be manually switched, but this may be a register on the system bus like the mode / ID setting register 55. If it is a register on this system bus,
Similar to the mode / ID setting register 55, the CPU 10 sets it by a program. This address setter 6
0 and 61 are for determining the system bus address for the buffer memories 33 and 43 of the file channels 30 and 40, respectively.
The reason why two addresses are provided for each of 0 and 40 is that the address is changed when writing the command or data in the buffer memories 33 and 43 and when reading the commands or data from the buffer memories 33 and 43. Now address setter 6
Address setter for writing 0, address setter 61
Is an address setter for reading, the set address by the address setter 60 is set to the same address in the file channel 30 and the file channel 40, and the set address by the address setter 61 is set in the file channel 30 and the file channel 30. 40 and different addresses are set.

As described above, the mode / ID setting register 5
5 and the address setters 60 and 61 are set, the operation of writing the data in the main storage unit 13 of the CPU 10 to the hard disks 5 and 6 will be described next.

The processor 11 of the CPU 10 writes a command in the buffer memory 33 of the file channel 30 on the active side. At this time, the address at the time of writing is set to the same for the file channels 30 and 40 by the address setter 60 as described above.
The selector 59 causes the address setter 6 to operate in response to the write signal S3.
It is designed to select 0. Therefore, the above command is simultaneously written in the buffer memory 43 of the file channel 40. However, at this time, since the mode setting bit M of the mode / ID setting register 55 of the file channel 40 is set to "0" (standby side),
The NAND gate 58 prevents the acknowledgment signal on the system bus 2 from being output to the system bus 2. Therefore, the confirmation response to the system bus 2 is performed only by the file channel 30 on the active side. 2
Simultaneous writing to one buffer memory 33, 43 can be easily realized if the system bus 2 is a synchronous bus.
The response to the system bus 2 with respect to the writing to the buffer memory 33 needs to be performed at a timing considering the case where the buffer memory 43 is being accessed by the processor 41. In order to shorten the transfer time to the system bus 2, it is necessary to give priority to the access to the buffer memories 33 and 34 of the system bus interfaces 341 and 441 over the access of the processors 31 and 41 to the buffer memories 33 and 43.

By the way, the file channel 30 is
When the above command is received, the CPU 10 notifies the CPU 10 of the response deletion indicating that the data can be received by a message. The file channel 40 on the standby side similarly makes a response to the CPU 10 indicating that data can be received. At this time, the file channel 3 received by the CPU 10
The ID is used to distinguish which file channel each message from 0, 40 is from. As described above, this ID is a channel identification code composed of 8 bits of ID setting bits in the mode / ID setting register 55, and the file channels 30, 4
It is set in advance corresponding to 0.

The CPU 10 uses the file channels 30, 40
When the message is received from both of the above, the DMA controller 15 is activated to write the data from the main storage unit 13 to the buffer memory 33. In this case as well, as in the case of the command transmission, the standby side file channel Four
The same data is written in the buffer memory 43 of 0.

As a result, the file channels 30, 40
After that, disk transfer is performed from the respective buffer memories 33 and 43 to the hard disks 5 and 6, and a command processing completion message is notified to the CPU 10, respectively. CPU 10 has file channels 30, 4
By receiving both command processing completion messages of 0, it is considered that the writing of data to the hard disks 5 and 6 is completed.

On the other hand, when reading the data in the hard disks 5 and 6 to the main memory 13, the data read command is written in both the file channels 30 and 40. Data is read from the hard disks 5, 6 to the buffer memories 33, 43 by both the file channels 30, 40, but data is transferred from the buffer memories to the main memory 13 by the file channel 3 on the active side.
0 only, not the file channel 40 on the standby side.

If a failure occurs in the file channel 30 on the active side, the CPU 10 changes the setting of the file channel 40 on the standby side to the active side, and the file channel 4
A command to continue processing is sent to 0. This active / standby mode setting is performed by rewriting the mode setting bit M from "1" to "0" or "0" to "1" in the mode / ID setting register 55 as described above.

As described above, according to this embodiment, the CPU
10 when a command is sent to the file channels 30 and 40, or from the main storage unit 13 to each file channel 3
When writing data to the buffer memories 33 and 43 of 0 and 40, a command or data is written to the two file channels 30 and 40 at the same time, and the confirmation response on the system bus at this time is the file channel 3 of the active side.
0, and a confirmation response by a message to the CPU 10 at the time when the reception of the command or data is completed, the respective file channels 30 and 40 perform their own I / O.
I am trying to use D. Therefore, even if the file channels are duplicated, the command issuance and the data transfer only have to be performed once.

FIG. 5 shows a second embodiment of the present invention. The difference between FIG. 5 and FIG.
0, 40 internal buses 32, 42 to transceivers 38, 4
Another buffer memory 3 on the bus separated in 8.
That is, 9,49 are provided. In this second embodiment,
The buffer memories 39 and 49 of the file channels 30 and 40 have the same address at the time of writing. In addition, the buffer memories 39 and 49
Is dedicated to the data buffer, and the processors 31 and 41 do not access the data buffers 39 and 49 during the data transfer with the system bus 2.

According to the second embodiment, the timing at which the file channel 30 returns the acknowledgment signal to the system bus 2 varies depending on the access times of the buffer memories 39 and 49 of the two file channels 30 and 40, respectively. Only the above need be considered, and the transfer to the system bus 2 can be speeded up.

FIG. 6 shows a third embodiment of the present invention, in which the DMA controllers 35 and 45 of the file channels 30 and 40 are removed from the second embodiment (FIG. 5). In the first embodiment, when the reception of the command or data is completed, the file channels 30 and 40 are DMed.
CP message using A controller 35, 45
Although the U10 is notified, in the third embodiment, the file channels 30 and 40 only display the status on the buffer memory, and the CPU 10 detects the status from the system bus 2.

In the third embodiment, when data is read from the hard disks 5, 6 to the main memory 13, the transfer from the buffer memory to the main memory 13 is CP.
The DMA controller 15 on U10 performs this.

By doing so, the DMA controllers 35 and 45 can be removed from the file channels 30 and 40, thereby reducing the cost. Also, when there is a failure on the active side, the buffer memory on the standby side can be read immediately without sending a new command to the standby side, so the standby side can be read at high speed when the active side fails. be able to.

In each of the above embodiments, the side using the file channel as the channel has been described, but the present invention is not limited to the file channel, and is applied to, for example, a communication control channel or an image processing channel. it can. Further, even when the CPU is duplicated, the present invention can be applied to data transfer.

[0045]

According to the present invention, for example, in a dual computer system in which a CPU and a channel are connected to the system bus and the above channel is duplicated, the command issuance and the data transfer from the CPU to each channel via the system bus are performed once. Since it is possible to reduce the system bus occupancy rate, the system bus occupancy rate can be reduced, and the processing performance of the entire system can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a first embodiment of the present invention.

FIG. 3 is a system bus interface 34 in FIG.
It is a block diagram of 1,441.

4 is a diagram showing a specific example of a mode / ID setting register in FIG.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a block diagram showing a third embodiment of the present invention.

FIG. 7 is a block diagram illustrating a signal processing method in a conventional duplex system.

[Explanation of symbols]

 10 CPU 30, 40 channel 101 DMA means 301, 401 Mode setting means 302, 402 ID setting means 303, 403 Address setting means

Claims (2)

[Claims] 1. A CPU (10) and a dual channel (30, 40) for the CPU are connected by a system bus (2), one channel being a working side and the other channel being a standby side. In a signal processing method in a duplex system, a DMA (Direct Memory Access) is provided to the CPU (10).
Means (101) are provided and each of the channels (3
0, 40) is provided with mode setting means (301, 401) for setting the active mode and the standby mode and identifier setting means (302, 402) for channel identification, and further, the CPU for each channel (30, 40) Address setting means (303, 403) for setting respective addresses at the time of writing and reading a command or data from (10) is provided for each channel, and from the CPU (10) to each channel (30, 40). Of the command writing time and when the CPU (10) uses the DMA means (101) to write data to each buffer memory in each channel (30, 40), the write address is set to the same address for each channel. , Read address when reading data from each channel is After the command and data from the CPU (10) are written to each channel (30, 40) at the same time, the confirmation response from the channel side to the CPU on the system bus (2) is The channel set on the active side performs the message (CPU (1
The signal processing method in the duplex system is characterized in that both channels perform the confirmation response to 0) together with the channel identifier. 2. Each channel (30, 40) confirms the reception completion of the command or data by displaying a status on a buffer memory in these channels, and the CPU
2. The signal processing method according to claim 1, wherein the step (10) is performed by detecting the status of the system bus (2).