JPH06196644A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] [Purpose] Heat treatment of a P-type diffusion layer for forming a shallow junction
Even if heat treatment is performed at low temperature or for a short time according to the conditions,
Bonding of As-added N-type diffusion layer without increasing
A method for manufacturing a semiconductor device capable of sufficiently reducing a leak current is provided.
provide. [Structure] In the region where the N-type diffusion layer is formed, is the Si substrate surface
Et As⁺ Ion and Si ₂ F⁺ Ion implantation at the same time,
As⁺ Ion and Si₂ F⁺ Ion-implanted Si group
Heat treat the plate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having an N-type diffusion layer to which As is added, for example, a CMOS structure having a P-type diffusion layer and an N-type diffusion layer on the same substrate. The present invention relates to a semiconductor device manufacturing method suitable for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art A field effect transistor having a MOS (metal-oxide film-semiconductor) structure is known. This M
A field effect transistor having an OS structure is configured to include a source, a drain, and a gate. By changing a gate voltage applied to the gate, a drain current flowing between the source and the drain is controlled, and an amplifying action and a switching action are performed. Has been created. As a method of forming the source and drain, ion implantation for introducing impurities into the Si substrate and recovery of the crystal damaged by the ion implantation after the ion implantation to electrically activate the implanted ions are performed. A method combined with heat treatment is generally used. This MOS structure field effect transistor has P
There are a type manufactured using a mold substrate and a type manufactured using an N-type substrate.

For example, a process of forming an N type diffusion layer (for example, a region to be a source and a drain) on a P type Si substrate is shown in FIG.
Will be described with reference to. First, as shown in FIG.
On the surface of the P-type Si substrate 10, SiO ₂ having a thickness of about 200Å
The film 11 is formed. Next, as shown in FIG. 3B, the wafer surface is patterned with the photoresist 12, and As ⁺ ions are implanted into the patterned portion. Next, as shown in FIG. 3C, the photoresist is peeled off, and heat treatment is performed at a predetermined temperature for a predetermined time, so that the N-type diffusion layer 1 is formed.
3 is formed.

A semiconductor device having a CMOS structure having an N-type diffusion layer and a P-type diffusion layer formed by the above ion implantation and subsequent heat treatment on the same substrate is a low power consumption type semiconductor device. Widely used. This CMO
An example of the S structure will be described with reference to FIG. This CMO
A semiconductor device having an S structure includes an N well 21 which is a large N type region formed in a P type Si substrate 20, and
P type diffusion layers 22 and 23 formed in the N well 21
(P-type source, P-type drain) and N-type diffusion layers 24, 2
5 (N-type source, N-type drain) are provided,
In addition, selective oxidation (LOCOS) is performed to separate each element.
There is also provided a LOCOS film 26 formed in 1. and a gate electrode 27 for controlling the drain current flowing between the source and the drain.

In the process of forming the semiconductor device having the above structure, the P type diffusion layers 22 and 23 implanted with B ⁺ ions (or BF ₂ ⁺ ions) and the N type diffusion layers 24 and 25 implanted with As. A heat treatment for forming is simultaneously performed. Further, as the miniaturization of the MOS transistor progresses, in order to reduce the short channel effect of the transistor, it is necessary to form the junction depth 28 shallow especially in the P-type diffusion layers 22 and 23. In order to form this shallow junction, it is necessary to lower the heat treatment temperature after the ion implantation or shorten the heat treatment time to shorten the diffusion distance of the implanted B ⁺ ions. Here, since the B ⁺ ions implanted into the P-type diffusion layers 22 and 23 have a small atomic radius and are light, there is little crystal damage due to the implantation of the B ⁺ ions, and diffusion at a low temperature provides sufficient junction depth and recovery of crystal defects. Is obtained. On the other hand, the As ⁺ ions implanted in the N-type diffusion layers 24 and 25 have a large atomic radius and are heavy, so that crystal damage due to the implantation of As ⁺ ions is large, and sufficient recovery of crystal defects can be obtained by diffusion at low temperature. Can not. Therefore, under the heat treatment condition of making the junction depth 28 of the P-type diffusion layers 22 and 23 shallow, the N-type diffusion layers 24 and
The recovery of the crystal defects of No. 25 is insufficient, and the electric charge conducts the crystal defects which are not recovered, and the N-type diffusion layers 24 and 25 and the P-type Si
While a leak current is generated at the interface with the substrate 20 and the junction leak current increases, under the heat treatment conditions for sufficiently recovering the crystal defects of the N-type diffusion layers 24 and 25, the P-type diffusion layers 22 and 23.
Since the junction depth 28 of the MOS transistor becomes deep, miniaturization of the MOS transistor cannot be achieved.

As a method of As ⁺ ions to reduce the junction leakage current of the N-type diffusion layer injected, injecting F ⁺ ions immediately after implanting As ⁺ ions were the injected F ⁺
A method of reducing the junction leakage current by improving the interface characteristics between the LOCOS film around the junction and the Si substrate by means of ions is known. (1990, 37th Joint Lecture on Applied Physics, Proceedings, 30p-ZF-4, Volume 2, p648)

[0007]

However, the above-mentioned As ⁺
The method of implanting F ⁺ ions immediately after implanting ions has the problems that the number of ion implantation steps is increased and that the junction leakage current is not sufficiently reduced. In view of the above circumstances, the present invention provides an N-type doped with As ⁺ ions without increasing the number of steps even when a low-temperature or short-time heat treatment such as a heat treatment of a P-type diffusion layer for forming a shallow junction is performed. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of sufficiently reducing the junction leak current of a diffusion layer.

[0008]

The present inventor came to the present invention by paying attention to the fact that the mass number of As and the mass number of Si ₂ F are the same 75. According to a method of manufacturing a semiconductor device of the present invention for achieving the above object, ions of impurity atoms are implanted from a substrate surface into a region where an N-type diffusion layer is formed, and the substrate is heat-treated to form an N-type diffusion layer. In the method of manufacturing a semiconductor device according to the above, in the region where the N-type diffusion layer is formed,
The feature is that As ⁺ ions and Si ₂ F ⁺ ions are simultaneously implanted from the Si substrate surface.

[0009]

Function: The mass number of As for forming the N-type diffusion layer is 7
5 and the mass number of Si ₂ F is also 75. Therefore, using an ion implanter equipped with a mass spectrometer, A
The s ⁺ ions and Si ₂ F ⁺ ions can be implanted into the Si substrate at the same time, and the throughput is not reduced.
Further, As implanted into the Si substrate becomes an impurity for forming the N-type diffusion layer, while F is the N-type diffusion layer and the LO.
It serves to improve the characteristics of the junction interface between the COS film and the Si substrate and reduce the junction leakage current. In addition, the Si substrate is made amorphous by the implantation of Si. Therefore, even in the heat treatment at about 850 ° C., the crystal of the Si substrate damaged by the ion implantation is well recovered. In the present invention, since Si is implanted as described above, heat treatment at about 850 ° C. is sufficient for defects that do not disappear unless heat treatment is performed at 900 ° C. or higher in the conventional method in which Si is not implanted. Thereby, the junction leak current can be further reduced.

When the method for manufacturing a semiconductor device of the present invention is applied to a method for manufacturing a semiconductor device having a CMOS structure having a p-channel MOS and an n-channel MOS on the same substrate, the junction depth of the P-type diffusion layer is Even if the heat treatment process after ion implantation is performed at low temperature or for a short time to make the depth shallower, as described above, Si ₂ F ⁺ ions are implanted in the N-type diffusion layer, so that the crystal defects are well formed. It is possible to recover and sufficiently reduce the junction leak current.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method of manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. In this embodiment, FIG.
A semiconductor device having the CMOS structure shown in was manufactured. The steps other than the step of forming the N-type diffusion layer of the CMOS structure are known methods. First, FIG. 1 shows an ion implantation apparatus used for forming the N-type diffusion layer.

The ion implantation apparatus 30 includes an ion source 31 for ionizing a gas into plasma, an extraction electrode 33 for extracting ions in the plasma to form an ion beam 32, and an extracted ion beam 32. Are provided with a mass analyzer 34 that bends the flight trajectory of the ion beam 32 due to the difference in mass number, a slit 35 that allows only target ions to pass, and an acceleration tube 36 that accelerates the ions that have passed through the slit 35. There is.

In this embodiment, the ion source 31 simultaneously ionizes SiF ₄ gas and AsH ₃ gas (arsine gas), and the mass analyzer 34 and the slit 35 use As ⁺ ions (mass number 75) and Si ₂ F ⁺ ions (mass number 75). Only the mass number of 75) is sent to the accelerating tube 36, and As ⁺ ions and Si ₂
F ⁺ ions were simultaneously implanted. Here, the mass spectrometer 34
As described above, the flight trajectory of the ion beam 32 is bent by the difference in the mass number of ions.
^{Since both +} ions and Si ₂ F ⁺ ions have the same mass number of 75, they have the same flight trajectory and pass through the slit 35.

As when implanting ions into a Si substrate⁺ Io
Energy: 75 keV, dose: 5 × 10¹⁵c
m^-2And On the other hand, Si₂ F⁺ Ions have energy: 7
5 keV, dose SiF_Four Adjust the gas flow rate
By 1 × 10¹⁵cm^-2, 2 × 10¹⁵cm^-2, 5 × 1
0¹⁵cm^-2, 1 × 10¹⁶cm^-24 types were selected. Well
In addition, the regions 22 and 23 where the P-type diffusion layer is formed (see FIG. 4).
B) under well-known conditions ⁺ Ions were implanted. N type expansion
P-type regions 24 and 25 (see FIG. 4) in which scattered layers are formed
In the regions 22 and 23 where the diffusion layers are formed (see FIG. 4), the above
After implanting ions under each condition of
It was activated by gas and caused by ion implantation.
Heat treatment was applied to the Si substrate to recover the crystal defects.
It was The heat treatment condition of the Si substrate after the ion implantation is 85.
0 ° C, 30 minutes, N₂ I went in the atmosphere. In addition, As⁺ ion
And Si₂ F⁺ Aeon at the same time Faraday cup (target
Is counted as⁺ Ion and Si₂ F⁺ 
The number of ions was determined by experiment.

After manufacturing the semiconductor device having the CMOS structure as described above, the junction leakage current of the junction diode (with a gate) between the P-type Si substrate and the N-type diffusion layer formed on the P-type Si substrate is measured. It was measured. This measurement result is N
Junction leakage current of a conventional semiconductor device in which Si ₂ F ⁺ ions are not implanted into the type diffusion layer, and F ions are implanted into the N type diffusion layer immediately after the above-described As ⁺ ions are implanted into the N type diffusion layer. FIG. 2 shows a comparison with the junction leakage current of the semiconductor device having the N-type diffusion layer formed by the method. The vertical axis on the left side of FIG. 2 shows the leak current, and the vertical axis on the right side shows the surface leak current. Further, in FIG. 2, ○, ● are values of leak current, △, ▲ are values of surface leak current, and ○, △
Indicates the value obtained by the method of this embodiment, and ● and ▲ indicate the value obtained by the method of implanting F ions immediately after the implantation of As ⁺ ions. Further, the Si ₂ F implantation dose amount of zero means that only As ⁺ ions were implanted and Si ₂ F ⁺ ions were not implanted in the formation region of the N-type diffusion layer.

[0016] As shown in FIG. 2, when the region for forming the N-type diffusion layer by the method of this example was implanted As ⁺ ions and Si ₂ F ⁺ ions at the same time, subsequent heat treatment conditions are 85
Even at 0 ° C. for 30 minutes, the junction leak current could be reduced compared to the conventional case. Therefore, the junction depth of the P-type diffusion layer is made shallow and M
Under heat treatment conditions that can respond to the miniaturization of OS transistors,
The heat treatment of the N-type diffusion layer can be sufficiently performed. Moreover, since As ⁺ ions and Si ₂ F ⁺ ions are implanted at the same time, the throughput is improved as compared with the method of implanting F ions immediately after implanting As ⁺ ions.

[0017]

As described above, according to the method for manufacturing a semiconductor device of the present invention, As ⁺ ions having a mass number of 75 and Si ₂ F ⁺ ions having a mass number of 75 are simultaneously implanted into a Si substrate, and the characteristics of the bonding interface are improved. Therefore, the junction leakage current can be reduced by the low temperature heat treatment without lowering the throughput.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing an ion implantation apparatus used in an embodiment of the present invention.

FIG. 2 is a graph showing the junction leakage current of a semiconductor device manufactured by the method for manufacturing a semiconductor device of this embodiment in comparison with the junction leakage current of a conventional semiconductor device.

FIG. 3 is a cross-sectional view showing a step of forming an N type diffusion layer on a P type Si substrate.

FIG. 4 is a cross-sectional view showing a semiconductor device having a CMOS structure.

[Explanation of symbols]

 20 P-type Si substrate 21 N-well 22,23 P-type diffusion layer 24,25 N-type diffusion layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 29/784 9054-4M H01L 29/78 301 P

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, wherein ions of impurity atoms are implanted from a substrate surface into a region where an N-type diffusion layer is formed, and the substrate is heat-treated to form an N-type diffusion layer. In the area where the layer is to be formed,
A method of manufacturing a semiconductor device, comprising simultaneously implanting s ⁺ ions and Si ₂ F ⁺ ions.