JPH0443649A - Semiconductor device and its preparation - Google Patents

Abstract

PURPOSE:To protect a semiconductor device element from being deteriorated by providing a conductive side wall at the side of the gate electrode via an insulating film and by electrically connecting a conductive side wall to a conductive part at the potential side of the source electrode relative to a potential of the drain electrode. CONSTITUTION:A gate electrode 22 is prepared on a silicon wafer 15, and the gate electrode 22 is masked to diffuse impurities, thereby preparing low density area 23S and 23D. Next, after an insulating film is prepared on the surface of the wafer, a conductive film 25a is formed, followed by preparing conductive side walls 25S and 25D leaving a conductive film 25 resident only in the side of the gate electrode 22. Next, the conductive side wall is masked to diffuse impurities to prepare hole density areas 26S and 26D. Next, after preparing an insulating film 27 on the gate electrode 22, opening 281 and 282 are prepared, and when preparing a source electrode 29S and a drain electrode 29D in the openings, the conductive side wall 25D at the drain side is electrically connected to a conductive part situated at the potential side of the source electrode 29S relative to the potential of the source electrode 29S or drain electrode 29D. With this, a semiconductor element can be protected from being deteriorated.

Description

[Detailed description of the invention] (Summary) L D D (IigMIy doped drain
) structure and its manufacturing method, with the aim of further preventing device deterioration due to hot electrons when miniaturizing the device and obtaining a highly reliable semiconductor device. A conductive sidewall part is provided on the substrate via an insulating film, and the sidewall part on the drain side is electrically connected to a conductive part on the potential side of the source electrode with respect to the potential of the drain electrode. A step of forming a gate electrode on and forming a low concentration region using this as a mask, a step of forming an insulating film on the surface, and then forming a conductive film on the surface,
- A process of forming a conductive sidewall on the side of the electrode, a process of forming a high concentration region using the conductive sidewall as a mask, and an opening is formed after forming an insulating film on the surface, and a source electrode is formed here. and a step of electrically connecting a side wall portion on the drain side to the source electrode or a conductive portion on the potential side of the source electrode with respect to the potential of the drain electrode when forming the drain electrode.

[Industrial Application Field] The present invention relates to an MO3 type semiconductor device having an LDD structure and a method for manufacturing the same.

In recent years, the development of integrated circuit technology has been remarkable, and the degree of integration has increased approximately four times every three years. As the degree of integration increases, J-transistors are also becoming smaller, but the voltage used cannot be lowered due to social demands for standardization. For this reason, miniaturized transistors have regions to which a high electric field is locally applied, and as a result, deterioration of elements due to hot electrons has become a serious problem in MO3 field effect transistors, for example. To deal with these problems, field effect transistors with an LDD structure are often used, in which a lightly doped diffusion layer (part of the drain) alleviates the electric field concentration generated near the gate electrode. In many cases, the effects are not sufficient, and improvements are strongly desired.

[Conventional technology]

Figure 6 shows the conventional LDD structure MO3 type field effect!・Structure diagram of an example of Runstar is shown. In the figure, a source high concentration diffusion region 1s and a drain high concentration diffusion region 18. Source low concentration diffusion region 211 and drain high concentration diffusion region 2
．． Is the ion using the gate electrode 3 and the sidewall insulating film 4 provided on the sidewall thereof? f - formed by people, especially
The concentration of the electric field generated near the drain is alleviated in the drain low concentration diffusion region 21) to prevent element deterioration due to hot electrons. In the figure, 5 is a source electrode, 6 is a drain interval, 7 is an insulating film, 8 is a GaI oxide film, and 9 is a semiconductor substrate.

[Problem to be solved by invention]

As shown in FIG. 7, during operation of the MO3 type transistor, a current path called a channel (inversion layer 10) is formed directly below the electrode 1 to the electrode 3, and the source diffusion region 1. ．． 2. A current begins to flow between the drain diffusion regions IO and 2o.

Second, for a certain source-drain voltage, as the source-drain distance narrows due to miniaturization, the electric field strength increases, and a large electric field becomes concentrated particularly near the drain. For this reason, the carrier (source F.
When the rain layer is made of an N-type semiconductor (therefore, when the semiconductor substrate is P-type), the electrons (-) are greatly accelerated, and eventually become 1
/2KT (K is Holtzmann constant, T is absolute temperature) (electron) has a kinetic energy exceeding 2KT (K is Holtzmann's constant, T is absolute temperature), and such electrons collide with semiconductor elements near the drain. Change of course and game 1-
Due to the Coulomb force from tffi 3, it is injected into the sidewall insulating film 4 on the drain side, as shown by O in FIG. 7, and becomes trapped there.

In conventional LDI structure transistors, such hot electrons are alleviated to some extent in the drain low concentration diffusion layer 2°, but as miniaturization progresses further, electric field concentration becomes even stronger. No countermeasures have been taken.

For this reason, especially when the miniaturization progresses further, the amount of charge injected and trapped inside the sidewall insulating film 4D will further increase, causing the problem that the semiconductor interface will be reversed and current flow will be inhibited. .

An object of the present invention is to provide a highly reliable semiconductor device that further prevents deterioration of the device due to hot electrons when the device is miniaturized.

[Means to solve the problem]

The above problem is solved by providing a conductive sidewall part on the side of the gate electrode via an insulating film, and connecting the conductive sidewall part on the drain side to the conductive part on the source electrode potential side with respect to the drain electrode potential. The problem is solved by a semiconductor device characterized in that it has a configuration in which the semiconductor devices are connected to each other. In addition, a gate electrode is formed on a semiconductor substrate of one conductivity type, and ions are implanted using the gate electrode as a mask to form a low concentration region. After forming an insulating film on the surface, a conductive film is formed on the surface. a step of forming a conductive sidewall by leaving the conductive film only on the sides of the gate electrode; a step of forming a high concentration region by implanting ions using the conductive sidewall as a mask; After forming an insulating film, an opening is formed in a predetermined portion, and when forming a source electrode and a drain electrode in the opening, the conductive side wall on the drain side is connected to the source electrode or the source electrode with respect to the potential of the drain electrode. The present invention is solved by a method for manufacturing a semiconductor device, which includes a step of electrically connecting to a conductive portion on the potential side of the semiconductor device.

[Effect]

For example, in the case of an N-type semiconductor substrate, electrons (negative charges) move from the source low concentration region to the drain low concentration region and tend to be injected into the conductive sidewall on the drain side. However, in the present invention, the conductive sidewall on the drain side is connected to the source electrode (
Since the structure is electrically connected to the drain electrode (lower potential than the drain electrode), electrons (negative charges) are repelled by the drain side wall (connected to the source electrode, so the potential is lower than the drain electrode) and the drain It is no longer injected into the side wall of the side. Therefore, even if the electric field concentration near the drain becomes stronger as the miniaturization progresses further, the current flow will not be inhibited as in the conventional example, and deterioration of the device due to hot electrons can be prevented.

〔Example〕

FIG. 1 shows a manufacturing process diagram of an embodiment of the present invention.

In the same figure (A), a silicon oxide film 16 is grown on the entire surface of the solicon substrate 15 to a thickness of about 200 wafers, and a silicon nitride film 17 is grown on the entire surface by CVD to a thickness of about 1,500 wafers. Subsequently, the silicon nitride film 17 is removed from the rest of the silicon nitride film 17, leaving only the active element portion. Next, as shown in FIG. 5B, approximately 5,000 field oxide films 18 are formed, and then the nitride film 17 in the active element area is removed using phosphoric acid boiling, and then oxidized by controlled etching using hydrofluoric acid. Remove silicon M16. In this way, the normal LOCOS process is completed. Next, the same figure (C)
In the step, the gate oxide film 19 is formed by about 50 to about 300 people.

Next, in the same figure (D), after about 3,000 phosphorus-doped polycrystalline silicon films 20 are grown, a silicon oxide film 21 is grown on that person Lo by CVD, and resist buttering is performed to remove these by etching. form a shaped gate electrode structure. Next, using this gate electrode 22 as a mask, for example, arsenic ions (concentration is about 1X
Source low concentration regions 23..1' rain low concentration regions 23. are formed by ion implantation of 1013 ions/cr+f to about 1X10'' ions/co?) at 60 keV and T-4 RG.

Next, in the same figure (E), a phosphorous oxide film 2'la is grown by CVD on the entire surface by about 100 to about +000 layers, and then a phosphorus doped film is grown by about 1,500 to about 3,000 layers to obtain anisotropic properties. Etching is performed to form an insulating film 24 (silicon oxide film) and a conductive side wall portion 25 (polycrystalline silicon film) on the side walls of the gate electrode 22.
remain. During this anisotropic etching, the polycrystalline silicon film 25a and the silicon oxide film 24a as well as the low concentration region 23. , 23. Since the upper oxide film I9 is also removed and the silicon substrate 15 is exposed, an oxide film 19', which is needed in this area during the next ion implantation, is formed by about 200 people. Next, using the gate electrode 22 and the side wall portions 25 as masks, for example, arsenic ions (concentration approximately 5×10'6/cffl) are implanted at an energy of 60 keV in the self-aligned source high concentration region 26. .

Drain high concentration region 26. form.

Next, in FIG. 2F, a silicon oxide film 27 is formed by CVD over the entire surface by approximately 2,000 to 3,000 layers.

Subsequently, annealing is performed at a temperature of 900°C for 30 minutes to form the low concentration region 23. ．． 23. , high concentration area 26g,
26o is activated.

Next, in FIG. 2G, an opening 281 is formed in the silicon oxide film 27 and the oxide film 19' from the source high concentration region 268 to the gate electrode 22, and the drain high concentration region 26. Upper silicon oxide film 27 and oxide film 1
A 28° opening is formed at 9'. Next, the opening 281
an aluminum source electrode 29. Along with forming the
An aluminum drain electrode 29D is formed in the opening 282.

As is clear from the figure (G), the source electrode 29 is connected to the source-side conductive side wall 25 by the opening 28+. As shown in the plan view of the main part in FIG. As a result, the side wall portion 25o on the drain side is electrically connected to the source electrode 29. As shown in the equivalent structure diagram in FIG. When the source and drain are made of N-type semiconductors, as explained in FIG. However, in the present invention, the side wall 25o on the drain side is injected into the drain side wall 25o.
5D is electrically connected to the source electrode 29Il, which has a lower potential than the drain electrode 29D.
5D is on the more negative potential side than the drain electrode 29o, and as a result, the side wall portion 25.5D on the drain side. The electrons (having a negative charge) that were about to be injected into the side wall 25o
(which is on the more negative potential side than the drain electrode 29.) is repelled by the side wall portion 250, and no more tl- particles are generated inside the side wall portion 250. As a result, even if the electric field concentration near the l-rain becomes stronger due to further miniaturization, the current flow will not be inhibited as explained in Fig. 7, and the pot Deterioration of the element due to electrons can be prevented.

Note that when the source, l, and rain are made of P-type semiconductors (
Therefore, the case where the substrate is of N type also depends on the same thinking as in the above embodiment. Holes (having a positive charge) move from the source low concentration region to the drain low concentration region and try to be injected into the drain side side wall. Since the sidewall is electrically connected to the source electrode, which has a higher potential than the drain electrode, the sidewall is at a more positive potential than the )・rain electrode, which causes the l・rain side Holes (having a positive charge) that try to be injected into the sidewall are repelled by the sidewall (which is at a more positive potential than the drain electrode) and are no longer injected into the sidewall.

Further, the drain electrode 29 shown in FIG. 1(G). is the source high concentration region 26. 1-7 [
The opening 28 .is formed over the pole 22 , for example as shown in FIG. 4 . The drain electrode 29S° may be extended to the side wall 25 on the drain side by forming a large opening 2 as shown in FIG.
81" to a small source electrode 298".
are formed, and an opening 283 is newly formed on the side wall portion 25D on the goo l-electrode 22 and the side wall 25D on the side of the helein 1, an electrode 30 is formed therein, and the electrode 30 is connected to the source electrode 29. Alternatively, the electrode 30 may be connected to an appropriate portion on the lower potential side than the drain electrode 29.The embodiment shown in FIG. 5 has a margin for alignment. Used when there is.

〔Effect of the invention〕

As explained above, according to the present invention, since the conductive side wall portion on the drain side is connected to the conductive portion having the potential on the source electrode side with respect to the drain electrode, electrons or holes are hardly injected into the side wall portion on the drain side. This makes it possible to prevent element deterioration due to pot electrons even when miniaturization is further advanced, and it is possible to obtain a highly reliable integrated circuit.

[Brief explanation of drawings]

Fig. 1 is a manufacturing process diagram of one embodiment of the present invention, Fig. 2 is a plan view explaining the gate side wall portion, Fig. 3 is an isolateral structure diagram of the present invention, and Fig. 4 is another embodiment of the present invention. FIG. 5 is a structural diagram of yet another embodiment of the present invention, FIG. 6 is a structural diagram of a conventional example, and FIG. 7 is a diagram explaining the state of pot electron generation. In the figure, 15 is a silicon substrate (semiconductor substrate of one conductivity type), 19 is a gate oxide film, 19゛ is an oxide film, 22 is a gate electrode, 23s is a source low concentration region, 23 is a drain low concentration region, and 24 is an insulation film. 25a is a polycrystalline silicon film (conductive film), 253 is a conductive sidewall on the source side, 25o is a conductive sidewall on the drain side, 26 is a source high concentration region, 26o is a drain high concentration region, 27 is a silicon oxide film (insulating film), 28+, 28+, 28+, 282, 28s opening, 29Il, 29. ', 29. " indicates a source electrode, 29o a drain electrode, and 30 an electrode. Manufacturing process diagram of an embodiment of the present invention FIG. 1 (Part 2) Plan view illustrating the gate side wall portion FIG. 2 Equivalent structure diagram of the present invention Fig. 5 Structural diagram of another embodiment of the present invention Fig. 4

Claims (2)

[Claims] (1) In a semiconductor device having an LDD structure, conductive sidewall portions (25_S, 25_D) are provided on the sides of the gate electrode (22) via an insulating film (24), and the conductive sidewall portion (25_D) is provided on the drain side. ) is electrically connected to a conductive portion (29_S) located on the potential side of the source electrode (29_S) with respect to the potential of the drain electrode (29_D). (2) Gate electrode (2) on one conductivity type semiconductor substrate (15)
2), and using the gate electrode (22) as a mask, impurity diffusion is performed to form low concentration regions (23_S, 23_D), and after forming an insulating film (24) on the surface, a conductive film is formed on the surface. film(
forming a conductive film (25a) only on the sides of the gate electrode (22);
) to form conductive sidewall portions (25_S, 25_D); and a step of diffusing impurities using the conductive sidewall portions (25_S, 25_D) as a mask to form high concentration regions (26_S, 26_D). After forming an insulating film (27) on the surface, an opening (27) is formed in a predetermined portion.
8_1, 28_2), and the openings (28_1, 28_2) are provided.
Source electrode (29_S) and drain electrode (2)
9_D), the conductive side wall portion (25_D) on the drain side is placed on the potential side of the source electrode (29_S) with respect to the potential of the source electrode (29_S) or the drain electrode (29_D). A method for manufacturing a semiconductor device, comprising the step of electrically connecting to a certain conductive portion.