JPH06196668A - Master slice type semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a master slice type semiconductor integrated circuit, and aims to improve the degree of integration by adopting a basic cell structure in which the degree of freedom of wiring is increased as compared with the conventional one. [Structure] The basic cell 90 includes a P-channel transistor group 7
0 and N channel transistor group 80, one contact each at the upper end of the first and second gate electrodes 71, 72 of the P channel transistor group 70, and two contacts each at the lower end. 2 can be formed on the upper ends of the third and fourth gate electrodes 81 and 82 of the N-channel transistor group 80.
One contact can be formed at each of the two contacts and the lower end portion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice type semiconductor integrated circuit having an improved degree of integration.

[0002]

2. Description of the Related Art Conventionally, master slice type semiconductor integrated circuits have been widely used. The master slice method is a method in which a large number of basic cells having a predetermined structure are formed in advance on an LSI chip and wirings between the basic cells are added to complete an integrated circuit that performs a desired operation. In this master slice method, various integrated circuits can be completed simply by creating a mask pattern for wiring, which is suitable for small-quantity, high-mix production.

FIG. 3 is a diagram showing the structure of a general master slice type basic cell. First in the vertical direction of the figure
And the second gate electrodes 11 and 12 extend, and the first and second gate electrodes 11 and 12 cause the first, second and third P-channel source / drain regions 13, 14 and 15 to extend.
Are formed so as to be separated from each other on the left and right sides, whereby a P-channel transistor group 10 including two P-channel transistors is formed.

The P-channel transistor group 10
The N-channel transistor group 20 including two N-channel transistors is formed adjacent to the lower part of the figure. This N-channel transistor group 20 also has a structure similar to that of the P-channel transistor group 10, and third and fourth gate electrodes 21 and 22 extend in the vertical direction of the drawing, and these third and fourth gate electrodes 21 and 22 are formed. The first, second, and third N-channel source / drain regions 23, 2
4, 25 are formed so as to be separated from each other on the left and right.

Further, contact formation regions (contact formation regions) in which contacts of the gate electrodes are formed are formed at upper and lower ends of the first, second, third and fourth gate electrodes 11, 12, 21, 22. The central part of the black circle 11a,
11b, 12a, 12b, 21a, 21b, 22a, 2
2b. ) Has been placed. Here, not only the gate electrode but also each region where one contact can be formed will be referred to as a contact formation region. The P-channel transistor group 10 and the N-channel transistor group 20 described above form a basic cell, and a large number of the basic cells are arranged on the wafer.

A case where a D flip-flop is constructed by using the basic cell constructed as described above will be described.
FIG. 4 is an actual wiring diagram when a D flip-flop is formed using the basic cell shown in FIG. In the figure, the black circles and marks represent the central part of the contact formation area, and the ○ marks are the first layer that connects the base on which the basic cell is formed and the first wiring layer formed on this base via an insulating layer. The formed contact, □, represents the contact formed in the second layer connecting the first wiring layer and the second wiring layer formed on the first wiring layer via the insulating layer.

Seven basic cells 31, 32,
33, 34, 35, 36, 37 are arranged, and a power supply line 38 and a ground line 39 are formed at the top and bottom of the drawing, respectively. For example, the contacts 41, 42 formed on the first layer,
43 and 44 are connected by a wiring 45, and contacts 51 and 52 formed in the second layer are connected by a wiring 53, thus forming a complicated wiring structure.

[0008]

As described above, when the basic cell becomes a complicated cell such as a flip-flop, contacts and wirings are crowded in this cell, so that the gate is formed in the region 30 in which the basic cell is formed. It becomes difficult to form the electrode contact. In the conventional example shown in FIG. 4, contacts 61, 62, and 61 are also provided in regions outside the region 30 in which the basic cells 31, 32, 33, 34, 35, 36, 37 are arranged.
63, 64 and wirings 65, 66 are formed. As described above, in the conventional basic cell, the area outside the area 30 in which the basic cells are arranged may be used as a wiring area, which causes an increase in the area of the wiring area, which results in an increase in the area of the circuit formed by the basic cell. There is a problem that the degree of integration may decrease.

In view of the above circumstances, it is an object of the present invention to provide a master slice type semiconductor integrated circuit having an improved degree of integration.

[0010]

A master slice type semiconductor integrated circuit according to the present invention for achieving the above object comprises:
(1) First and second gate electrodes that extend in the vertical direction in parallel with each other and that have at least one contact formation region in which one of the upper end portion and the lower end portion has at least one contact formed in the other; A P-channel transistor group consisting of first, second and third P-channel source / drain regions separated from each other by these first and second gate electrodes, and (2) above and below the P-channel transistor group. Third and fourth gate electrodes, which are arranged adjacent to each other in the direction, extend in the vertical direction in parallel with each other, and have at least one contact formation region in at least one of the upper end and the lower end, and at the other end,
An N-channel transistor group including first, second and third N-channel source / drain regions separated from each other by the third and fourth gate electrodes on the left and right sides,
(3) The contact forming regions of the first gate electrode, the first P-channel source / drain region, the third gate electrode, and the first N-channel source / drain region extend vertically. (4) the second P-channel source / drain region and the contact formation regions of the second N-channel source / drain region are arranged on a second straight line extending in the vertical direction. (5) Contact formation of each of the second gate electrode, the third P-channel source / drain region, the fourth gate electrode, and the third N-channel source / drain region. It is characterized in that a large number of basic cells are arranged adjacent to each other on a third straight line whose region extends in the vertical direction.

[0011]

In the master slice type semiconductor integrated circuit of the present invention, a large number of basic cells having a P-channel transistor group and an N-channel transistor group are arranged, similar to the P-channel transistor group 10 and the N-channel transistor group 20 shown in FIG. However, the gate electrode of the present invention has at least one contact formation region in one of the upper end and the lower end and at least two contact formation regions in the other, and (3), Because of the positional relationships shown in (4) and (5), the degree of freedom of wiring is large and wiring can be performed without waste, so that it is possible to form a circuit with a higher degree of integration than in the past.

Here, in the present invention, when the D flip-flop is constructed, at least one of the upper end and the lower end of the gate electrode has at least one contact formation region and the other has at least two contact formation regions. It seems that the area increases and the degree of integration of the circuit formed by arranging the basic cells decreases, but this part can be used as a wiring area and the degree of freedom of wiring becomes large, so that a wasteful area. Does not mean Therefore, as a whole,
The degree of integration of the circuit configured by arranging the basic cells can be improved.

[0013]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a diagram showing a structure of a basic cell according to an embodiment of the present invention. The black circles in the figure indicate the central portions of the contact formation regions where contacts can be formed.

The basic cell 90 includes a P-channel transistor group 70 and the P-channel transistor group 70.
Of adjacent N-channel transistor group 80 in the lower part of the figure
It consists of In the P-channel transistor group 70, the first and second gate electrodes 71, 7 are arranged in the vertical direction in the figure.
2 extends and these first and second gate electrodes 71, 72
Thus, the first, second, and third P-channel source / drain regions 73, 74, and 75 are formed so as to be separated from each other on the left and right, whereby two P-channel transistors are formed. First and second gate electrodes 71,
One contact can be formed on each of the upper ends of 72, while two contacts can be formed on each of the lower ends.

In the N-channel transistor group 80,
Third and fourth gate electrodes 81 and 82 extend in the vertical direction of the figure, and the first and second N-channel source / drain regions 83 and 84 are formed by the third and fourth gate electrodes 81 and 82. , 85 are formed so as to be separated from each other on the left and right sides, whereby two N-channel transistors are formed. Third and fourth gate electrodes 81, 82
Two contacts can each be formed on the upper end of the, while one contact can be formed on each lower end.

Here, as shown in FIG. 1, the first gate electrode 71, the first P-channel source / drain region 73,
The contact formation regions of the third gate electrode 81 and the first N-channel source / drain region 83 are arranged adjacent to each other on a first straight line 91 extending in the up-down direction shown by a dashed line in the drawing. . Further, the contact forming regions of the second P-channel source / drain region 74 and the second N-channel source / drain region 84 are adjacent to each other on the second straight line 92 extending in the vertical direction indicated by the alternate long and short dash line in the figure. Are arranged. Furthermore, the second gate electrode 7
2, the gate electrodes 82 of the third P-channel source / drain regions 75 and 4, and the contact formation regions of the third N-channel source / drain region 85 each have a third straight line extending in the vertical direction indicated by a dashed line in the figure. 93 are arranged adjacent to each other.

FIG. 2 is an actual wiring diagram when a D flip-flop is constructed using the basic cell shown in FIG. 1, and this D flip-flop has the same function as the flip-flop shown in FIG. In the figure, the black circles and marks represent the central part of the contact formation area, and the ○ marks are the first layer that connects the base on which the basic cell is formed and the first wiring layer formed on this base via an insulating layer. Contact formed, □ is the above first
The contact formed in the second layer connecting the first wiring layer and the second wiring layer formed via the insulating layer to the first wiring layer.

Seven basic cells 101, 10 are arranged in the horizontal direction of the figure.
2, 103, 104, 105, 106, 107 are arranged, and a power supply line 108 and a ground line 10 are respectively provided at the top and bottom of the drawing.
9 is formed. For example, the contacts 111, 112, 113, 114 formed on the first layer are connected by the wiring 115, and the contacts 121, 122 formed on the second layer are connected.
Are connected by wiring 123, and have a complicated wiring structure. However, since two contact formation regions are provided at the lower ends of the first and second electrodes 71 and 72, and two contact formation regions are provided at the upper ends of the third and fourth electrodes 81 and 82, the D flip-flop is formed. The degree of freedom of wiring within the circuit is large, and as in the case shown in FIG. 4, the area outside the area 100 in which the basic cells are arranged is not used as a wiring area.

Here, when the dimensions of the basic cell according to the embodiment of the present invention and the conventional basic cell shown in FIG. 3 are compared, both have 12 grids in the vertical direction and 3 grids in the horizontal direction, and have the same size. Has become. However, in the basic cell according to the embodiment of the present invention, as described above, there are two contact formation regions at the lower ends of the first and second electrodes 71 and 72,
Since two contact forming regions are provided at the upper end portions of the third and fourth electrodes 81 and 82, the degree of freedom of wiring is increased, and therefore the basic cell according to the embodiment of the present invention is used. Comparing the dimensions of the D flip-flop shown in FIG. 2 configured by using the same with the dimensions of the D flip-flop shown in FIG. 4 configured by using the basic cell shown in FIG. The size of the D flip-flop configured using the basic cell according to the embodiment is smaller. This point will be described.

The D flip-flop shown in FIG. 2 can be composed of 13 grids in the vertical direction and 21 grids in the horizontal direction. On the other hand, the D flip-flop shown in FIG. 4 is composed of 14 grids in the vertical direction and 21 grids in the horizontal direction. Therefore, (area in the conventional type (FIG. 4)) / (area in the present invention (FIG. 2)) = (14 × 21) / (13 × 21) ≈1.
077 ... (A), which is a D flip-flop having a higher degree of integration as compared with the basic cell shown in FIG.

[0021]

As described above, the master slice type semiconductor integrated circuit of the present invention has at least one of the upper end portion and the lower end portion in order to increase the degree of freedom of wiring.
On the other hand, a large number of basic cells each having a gate electrode having at least two contact formation regions are arranged, and the degree of freedom of wiring is large. Therefore, the degree of integration is improved as compared with the conventional master slice type semiconductor integrated circuit. Can be planned.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of a basic cell according to an embodiment of the present invention.

FIG. 2 is an actual wiring diagram when a D flip-flop is configured using the basic cell shown in FIG.

FIG. 3 is a diagram showing a structure of a general master slice type basic cell.

FIG. 4 is a substantial wiring diagram when a D flip-flop is configured using the basic cell shown in FIG.

[Explanation of symbols]

70 P-Channel Transistor Group 71 First Gate Electrode 72 Second Gate Electrode 73, 74, 75 P-Channel Source / Drain Region 80 N-Channel Transistor Group 81 Third Gate Electrode 82 Fourth Gate Electrode 83, 84, 85 N Channel source / drain regions 101, 102, 103, 104, 105, 106, 1
07 Basic cell

Claims (1)

[Claims] 1. A first gate electrode and a second gate electrode which extend vertically in parallel with each other and have at least one contact formation region in one of the upper end and the lower end and in which the contact is formed in the other. And a P-channel transistor group consisting of first, second and third P-channel source / drain regions separated from each other by these first and second gate electrodes, and a vertical direction of the P-channel transistor group. Third and fourth gate electrodes, which are arranged adjacent to each other, extend in the vertical direction in parallel with each other, and have at least one contact formation region in at least one of the upper end and the lower end, and at the other end;
An N-channel transistor group composed of first, second and third N-channel source / drain regions separated from each other by the third and fourth gate electrodes on the left and right sides is provided, and the first gate electrode and the first N-channel transistor group are provided. One P-channel source / drain region, the third gate electrode, and each contact formation region of the first N-channel source / drain region are arranged adjacent to each other on a first straight line extending in the vertical direction, The contact forming regions of the second P-channel source / drain region and the second N-channel source / drain region are arranged adjacent to each other on a second straight line extending in the vertical direction, and further, the second gate electrode Contact points of the third P-channel source / drain region, the fourth gate electrode, and the third N-channel source / drain region. Master slice type semiconductor integrated circuit formation region third straight line basic cells arranged adjacent to the vertically extending is characterized by comprising a large number sequence.