JPH06196670A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [Purpose] A RAM in which a plurality of basic cell rows in which basic cells are arranged in a row are arranged in parallel in the periphery of an array area,
A large-scale hard macro cell such as a ROM and the logic area arranged in the central portion can be easily connected. A U-shaped P-type MOS transistor 6a is arranged in a line on the right side of a straight line Y1-Y2 which is perpendicular to the arrangement direction of the basic cell line in a line above the basic cell line. An inverted U-shaped P-type MOS transistor 6c on the left side
Are arranged in a line. In one row below the basic cell row,
The U-shaped N-type MOS transistors 6b are arranged side by side on the right side of a straight line Y1-Y2 perpendicular to the arrangement direction of the basic cell columns. The inverted U-shaped N-type MOS transistors 6d are arranged in a line on the left side. [Effect] It is possible to arrange the terminals of the hard macrocells of the same configuration arranged on the left and right of the straight line Y1-Y2 toward the center.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate array type semiconductor integrated circuit device, and more particularly to an arrangement of basic cells spread in an array region.

[0002]

2. Description of the Related Art FIG. 6 is a plan view of a gate array type semiconductor integrated circuit device. In FIG. 6, 1 is a semiconductor chip having a semiconductor integrated circuit formed on its surface, 2 is an input / output pad for inputting / outputting signals and a power source to / from the outside, 3 is an array region in which basic cells are spread, and 4 is a basic Represents a basic cell sequence in which cells are arranged in a line. A large number of input / output pads 2 are arranged on the periphery of the semiconductor chip 1, and an array region 3 in which basic cells are spread is provided in a region surrounded by the input / output pads 2 on the semiconductor chip 1. Further, the array region 3 is formed by arranging a plurality of basic cell rows 4 formed by arranging the basic cells in one row in parallel.

FIG. 7 is an enlarged plan view of the basic cell row 4 shown in FIG. Here, a gate separation type is shown as one row of the basic cell row. In FIG. 7, 5 is a basic cell, 6a is a gate electrode of a P-type MOS transistor, 6b is a gate electrode of an N-type MOS transistor, 7 is a P-type diffusion region and is a source electrode or drain electrode of a P-type MOS transistor, and 8 is The N-type diffusion region corresponds to the source electrode or the drain electrode of the N-type MOS transistor. The basic cell 5 is composed of a pair of P-type MOS transistor and N-type MOS transistor. As described above, since the shape of the gate electrodes 6a and 6b forming the basic cell 5 is not rectangular, X1-X2 perpendicular to the basic cell row 4 is formed.
It has the characteristic that the shape of the basic cell is not symmetrical with respect to the axis.

FIG. 8 is an equivalent circuit diagram of the basic cell array 4 shown in FIG. 8, the same reference numerals as those in FIG. 7 indicate the parts corresponding to those in FIG. The P-type diffusion region 7 forming the source or drain electrode of the P-type MOS transistor and the N-type diffusion region 8 forming the source or drain electrode of the N-type MOS transistor are connected in series. In the gate separation type basic cell array 4, a transistor at a position to be isolated is turned off to divide the series connected transistor array to form a desired circuit.

FIG. 9 is a plan view showing the structure of a conventional array region 3. In FIG. 9, reference numerals 4a to 4d denote basic cell columns of the first to fourth stages, respectively. By showing only the gate electrodes 6a and 6b, a plurality of basic cell columns 4 of FIG. It represents the situation that is configured. Each of the basic cell rows 4a to 4d is configured by arranging a plurality of basic cells 5 in one row in the same direction. The arrangement directions of all the basic cell rows 4a to 4d are the same.

[0006]

Since the conventional semiconductor integrated circuit device is constructed as described above, the following problems exist. This problem will be described with reference to FIG. FIG. 10 is a plan view showing a state in which hard macro cells are arranged on the semiconductor chip forming the array region shown in FIG. In FIG. 10, 9a to 9d are hard macro cells, 10 is a logic region, 11 is a terminal of the hard macro cell, and the same reference numerals as those in FIG. 6 indicate the corresponding portions of FIG.

An R normally arranged in a semiconductor integrated circuit device
Large-scale hard macro cells 9a to 9d such as AM and ROM
Are arranged in the peripheral portion of the array area 3 of the semiconductor chip 1, and the logic area 10 composed of macro cells such as NAND circuits and NOR circuits is arranged in the central portion of the array area 3 so that the use efficiency of the chip area is improved. Get better. Then, in order to make the hard macro cells 9a to 9d and the logic region 10 easily accessible, the hard macro cells 9a to 9d
It is desirable to arrange the hard macro cells 9a to 9d so that the terminal of 9d is on the center side of the array region 3.

However, in the semiconductor chip 1 in which the array area 3 is formed as in the conventional case, the basic cell row 4 of the array area 3 is formed.
Since all the basic cells are arranged in the same direction, the hard macro cells 9a to 9d using the basic cells are arranged only in the same direction because the terminals 11 are located in the same direction. I can't. As shown in FIG. 10, if the hard macro cells 9a to 9d are arranged on the peripheral portion of the array region 3, for example, on the left and right of the logic region 10 arranged at the center, one of the hard macro cells 9a arranged on the right side or the left side, 9b terminal 11
Will be arranged toward the side opposite to the center of the array region 3. Therefore, in order to connect the logic region 10 arranged in the central portion of the array region 3 and the terminals 11 of the hard macro cells 9a and 9b, it is necessary to secure an extra wiring region, which reduces the efficiency of use of the chip area. There was a problem that it would end up. Further, there is a problem that the wiring length becomes long and the delay time also increases.

On the other hand, when the terminals 11 of the hard macro cells 9a and 9b arranged at the left and right ends in the array area 3 are both arranged on the center side, the hard macro cells 9a to 9d are inverted on the right side and the left side in the array area 3. Therefore, even if the hard macro cells 9c and 9d and the hard macro cells 9a and 9b are hard macro cells having the same circuit configuration, the hard macro cells 9c and 9d and the hard macro cell 9a can be arranged on the right and left sides. , 9b
It was necessary to design and separately.

The present invention has been made to solve the above-mentioned problems, and includes terminals of hard macro cells arranged in a peripheral portion of an array area of a semiconductor chip and a logic area arranged in a central portion of the array area. It is an object of the present invention to provide a gate array type semiconductor integrated circuit device capable of easily connecting to each other.

[0011]

A semiconductor integrated circuit device according to a first aspect of the present invention is a gate array type semiconductor integrated device having an array region in which a plurality of basic cell rows in which a plurality of basic cells are arranged in a row are arranged in parallel. In the circuit device, at least a part of the array region includes a plurality of basic cell rows in which the basic cells are arranged in a direction opposite to an axis perpendicular to the arrangement direction.

A semiconductor integrated circuit device according to the second invention is
A gate array type semiconductor integrated circuit device having an array area in which a plurality of basic cell rows in which a plurality of basic cells are arranged in a row are arranged in parallel, wherein the array area is the basic cells in a mutual relation of the basic cell rows. The arrangement direction of includes a portion in which the predetermined direction is reversed for every predetermined number of basic cell columns.

[0013]

The array region in the first aspect of the invention uses, for example, a hard macro cell by using a partial region including a plurality of basic cell rows in which the basic cells are arranged in the direction opposite to the axis perpendicular to the arrangement direction. When arranging in the peripheral part of the array region, even if the hard macro cell arranged on one side so as to be line symmetric with respect to the axis perpendicular to the arrangement direction is inverted, the terminal position of the hard macro cell is It can be easily arranged toward the center of the array region where the logic region is formed.

The array region in the second aspect of the present invention uses, for example, a part of the region in which the arrangement direction of the basic cells in the mutual relation of the basic cell columns is opposite in every predetermined number of basic cell columns. When arranging the hard macro cells in the peripheral portion of the array region, the hard macro cells on the other side are arranged 180 degrees so as to be point-symmetric with the hard macro cells arranged on the one side.
By arranging the terminals by rotating them once, the terminal position of the hard macro cell can be easily arranged, for example, toward the central portion side of the array area in which the logic area is formed.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of an array region of a semiconductor chip in a semiconductor integrated circuit device according to an embodiment of the present invention. In FIG. 1, 6a is a gate electrode of a U-shaped P-type MOS transistor, 6b is a gate electrode of a U-shaped N-type MOS transistor, 6c is a gate electrode of an inverted U-shaped P-type MOS transistor, 6d
Is a gate electrode of an inverted U-shaped N-type MOS transistor, 13 is an array region of a semiconductor chip, and 14a to 14d.
Indicates a basic cell row forming the array region 13.

In each of the basic cell rows 14a to 14d, a U-shaped P-type MOS transistor is provided on the right side of the basic cell row on the right side of a straight line Y1-Y2 perpendicular to the arrangement direction of the basic cell rows. The transistors 6a are arranged in a line, and the inverted U-shaped P-type MOS transistor 6c is arranged in a line on the left side. In a row below the basic cell row, with a straight line Y1-Y2 perpendicular to the arrangement direction of the basic cell row as a boundary,
The U-shaped N-type MOS transistors 6b are arranged side by side on the right side, and the inverted U-shaped N-type MOS transistors 6d are arranged side by side on the left side. Array area 13
Is a configuration in which the above-mentioned basic cell rows 14a to 14d are arranged in parallel in four stages.

In contrast to the basic cell row forming the array area shown in FIG. 1, the basic cell row forming the array area shown in FIG. A Z-Z2 line that is perpendicular to the direction of arrangement of the basic cell columns is used as a boundary, and a U-shaped P-type MOS transistor 6a is arranged side by side on the left side and an inverted U-shaped P-type MOS transistor 6c is arranged on the right side. Are arranged side by side. In addition, in the lower row of the basic cell row, Z1-Z perpendicular to the arrangement direction of the basic cell row is provided.
On the right side of the line 2, the U-shaped N-type MOS transistors 6b are arranged side by side in a line, and on the left side are the inverted U-shaped N-type M transistors.
The OS transistors 6d are arranged in a line. The array region 23 has four basic cell columns 24a to 24d.
It is configured by arranging in parallel.

FIG. 3 is a plan view showing the structure of a semiconductor integrated circuit device in which hard macro cells are arranged on the semiconductor chip forming the array region shown in FIGS.
In FIG. 3, 31 is a semiconductor chip having a semiconductor integrated circuit formed on its surface, 32 is an input / output pad for inputting / outputting signals and a power source to / from the outside, 33 is an array area in which basic cells are spread, and 34 is a basic Represents a basic cell sequence in which cells are arranged in a line. A large number of input / output pads 32 are arranged on the periphery of the semiconductor chip 31, and an array region 33 in which basic cells are spread is provided in a region surrounded by the input / output pads 32 on the semiconductor chip 31. Further, the array region 33 is configured by arranging a plurality of basic cell rows 34, which are configured by arranging basic cells in one row, in parallel. Also,
Reference numerals 39a to 39d denote hard macro cells, 30 denotes a logic area, and 41 denotes terminals of the hard macro cells. In the semiconductor integrated circuit device shown in FIG. 3, the logic region 40 is arranged in the center of the semiconductor chip 1.

In the semiconductor integrated circuit device of FIG. 3, since the arrangement directions of the gate electrodes of the basic cells are symmetrical with respect to the central axis, the hard macro cells 49a and 49b arranged on the right side of the logic region 40 and the left side thereof are arranged on the left side. The hard macro cells 49c and 49d thus arranged are arranged in directions opposite to each other by moving in line symmetry with respect to the central axis and inverting the arrangement. Therefore, the terminal positions 41 of the hard macro cells 49a to 49d arranged in the peripheral portion are arranged on the central side of the array region 43 where the logic region 41 is located.

Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a plan view showing a structure of an array region of a semiconductor chip according to another embodiment of the present invention. Figure 4
6a is a gate electrode of a U-shaped P-type MOS transistor, 6b is a gate electrode of a U-shaped N-type MOS transistor, and 6c is an inverted U-shaped P-type M transistor.
A gate electrode of the OS transistor, 6d is a gate electrode of an inverted U-shaped N-type MOS transistor, 43 is an array region of a semiconductor chip, and 44a to 44d are array regions 43.
The basic cell sequence which comprises is shown.

In the basic cell rows 44a and 44c, U-shaped P-type MOS transistors 6a are arranged in a row in the upper row, and in the lower row, a U-shaped N-type MOS transistor is arranged in the right row.
The transistors 6b are arranged in a line. Also,
In the basic cell rows 44b and 44d, the inverted U-shaped P-type MOS transistors 6c are arranged in a row on the upper side,
In the lower row, an inverted U-shaped N-type MOS transistor 6
d are arranged in a line. And array area 4
3 is the basic cell rows 44a, 44c and 4 having different array directions.
4b and 44d are alternately arranged in each row. In this case, the hard macro cells arranged in the array region 43 are
By arranging it by rotating 180 degrees, the terminal position can be arranged on the central axis side.

FIG. 5 is a diagram showing another mode of the array region shown in FIG. In FIG. 5, 6a is a gate electrode of a P-type MOS transistor having a U-shape, 6b is a gate electrode of an N-type MOS transistor having a U-shape, 6c is a gate electrode of a P-type MOS transistor having an inverted U-shape, 6d is a gate electrode of an inverted U-shaped N-type MOS transistor, 53 is an array region of a semiconductor chip, 54a
Reference numerals 54d to 54d denote basic cell columns forming the array region 53.

In the basic cell rows 54a and 54b, U-shaped P-type MOS transistors 6a are arranged in a row in the upper row, and in a lower row, the U-shaped N-type MO transistor is arranged in the right row.
The S transistors 6b are arranged side by side in a line. Also,
In the basic cell rows 54c and 54d, the inverted U-shaped P-type MOS transistors 6c are arranged side by side in one row on the upper side, and the inverted U-shaped N-type MOS transistors 6d are arranged in one row on the lower side. They are arranged side by side. The array region 53 has the basic cell columns 54a and 54b arranged in different directions.
And 54c and 54d are arranged in two columns. in this case,
180 hard macro cells placed in the array area 53
The terminal position can be arranged on the opposite side by rotating the base cell by one degree or by reversing it in line symmetry with respect to the axis perpendicular to the arrangement direction of the basic cell rows and moving in parallel up and down by two basic cell rows.

Although the gate array type semiconductor integrated circuit device using the CMOS transistor as a basic cell has been described in the above embodiment, the basic cell is an N-type MOS.
It may be composed of only a transistor or a P-type MOS transistor, and has the same effect as that of each of the above-described embodiments.

Further, although the case where the entire array region is line-symmetrical or point-symmetrical has been described in the above-mentioned embodiments, it is sufficient if a part of the array region is symmetrical as described above. Has the same effect as.

In another embodiment, the basic cells are arranged such that the basic cells are arranged in the opposite direction in every one row or in every two rows. However, it is not limited to how many rows are arranged in the opposite direction. The better effect can be obtained by selecting according to the target to be used.

Further, in each of the above embodiments, the semiconductor integrated circuit device of the gate separation type has been described, but the semiconductor integrated circuit device of the gate array type of another type may be used, in which non-rectangular gate electrodes are arranged. In that case, the same effect as that of the above embodiment is obtained.

[0028]

As described above, according to the semiconductor integrated circuit device of the first aspect of the present invention, at least a part of the array region is arranged in the direction opposite to the axis perpendicular to the arrangement direction of the basic cells. Since it is configured to include a plurality of basic cell columns arranged toward each other, for example, in the logic region formed in the region including the vertical axis and the hard macro cells formed on both sides thereof, the logic region and the hard macro cell are This has the effect of reducing the length of wiring to be connected and reducing the delay time. Further, there is an effect that the wiring region connecting the logic region and the hard macro cell can be reduced, and the efficiency of use of the gate can be improved. Also, the restrictions when arranging hard macro cells on a semiconductor chip are eased,
In designing a hard macro cell, it is sufficient to design one cell for the same circuit configuration, and it is not necessary to consider the terminal position of the cell, which has the effect of facilitating the design.

According to the semiconductor integrated circuit device according to the second aspect of the present invention, in the array region, the arrangement direction of the basic cells in the mutual relation of the basic cell rows is a reverse direction for every predetermined number of basic cell rows. Is configured to include
For example, in the logic region formed in the region including the vertical axis and the hard macro cells formed on both sides thereof, the wiring length connecting the logic region and the hard macro cell is shortened, and the delay time can be reduced. Further, there is an effect that the wiring area connecting the logic area and the hard macro cell can be made small, and the use efficiency of the gate can be improved. Further, the restrictions when arranging the hard macro cells on the semiconductor chip are relaxed, and in designing the hard macro cells, it is sufficient to design one cell for the same circuit configuration, and it is not necessary to consider the terminal positions of the cells. It has the effect of making it easier.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an array region according to an embodiment of the present invention.

FIG. 2 is a diagram showing another aspect of the array region according to the embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a semiconductor chip in which hard macro cells and the like are arranged in a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of an array region which is another embodiment of the present invention.

FIG. 5 is a diagram showing another aspect of an array region according to another embodiment of the present invention.

FIG. 6 is a plan view showing a configuration of a conventional semiconductor chip.

FIG. 7 is a plan view showing a configuration of a conventional basic cell row.

8 is a diagram showing an equivalent circuit of the basic cell row shown in FIG. 7. FIG.

FIG. 9 is a diagram showing a configuration of a conventional array area.

FIG. 10 is a diagram showing a configuration of a semiconductor chip in which a hard macro cell and the like are arranged in a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 semiconductor chip 2 input / output pad 3 array area 4 basic cell row 5 basic cells 6a, 6c P-type MOS transistor gate electrode 6b, 6d N-type MOS transistor gate electrode 7 P-type diffusion region 8 N-type diffusion region 9 hard macrocell 10 Logic area 11 Terminal

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[Procedure amendment]

[Submission date] April 28, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction content]

FIG. 3 is a plan view showing the structure of a semiconductor integrated circuit device in which hard macro cells are arranged on the semiconductor chip forming the array region shown in FIGS.
In FIG. 3, 31 is a semiconductor chip having a semiconductor integrated circuit formed on its surface, 32 is an input / output pad for inputting / outputting signals and a power source to / from the outside, 33 is an array area in which basic cells are spread, and 34 is a basic Represents a basic cell sequence in which cells are arranged in a line. A large number of input / output pads 32 are arranged on the periphery of the semiconductor chip 31, and an array region 33 in which basic cells are spread is provided in a region surrounded by the input / output pads 32 on the semiconductor chip 31. Further, the array region 33 is configured by arranging a plurality of basic cell rows 34, which are configured by arranging basic cells in one row, in parallel. Also,
39a to 39d are hard macro cells, 40 is a logic area
Area 41 indicates a terminal of the hard macro cell. In the semiconductor integrated circuit device shown in FIG. 3, the logic region 40 is arranged in the center of the semiconductor chip 1.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

In the semiconductor integrated circuit device of FIG. 3, since the arrangement directions of the gate electrodes of the basic cells are symmetrical with respect to the central axis, they are arranged on the left side of the hard macro cells 39a and 39b arranged on the right side of the logic region 40. The hard macro cells 39c and 39d thus arranged are arranged in directions opposite to each other by moving in line symmetry with respect to the central axis and inverting the arrangement. Therefore, the terminal location 41 of the hard macro cell 39a~39d arranged in the peripheral portion, the logic region
The array region 33 having 40 is arranged on the central side.

Claims (2)

[Claims] 1. A gate array type semiconductor integrated circuit device having an array area in which a plurality of basic cell rows in which a plurality of basic cells are arranged in a row are arranged in parallel, wherein the array area is provided in at least a part thereof. A semiconductor integrated circuit device comprising a plurality of basic cell rows in which basic cells are arranged in a direction opposite to an axis perpendicular to the arrangement direction. 2. A gate array type semiconductor integrated circuit device having an array region in which a plurality of basic cell columns in which a plurality of basic cells are arranged in a line are arranged in parallel, wherein the array regions are related to each other in the basic cell columns. 2. The semiconductor integrated circuit device according to claim 1, wherein the arrangement direction of the basic cells includes a portion having a reverse direction for every predetermined number of basic cell rows.