JPH0619702A - Microcomputer computing element - Google Patents

Abstract

PURPOSE:To shorten processing time and to simplify software so as to efficiently use hardware resource by sharing registers by means of an arithmetic and logic computing element and an address computing element. CONSTITUTION:At least two independent address computing elements 12 and 13, at least one arithmetic and logic computing element 10 and a register file 11 which is connected to them are provided. The register file 11 is provided with at least two pairs of registers or register pairs which can be used as at least two one-word length registers and which have bit length more than two word length. The arithmetic and logic computing element 10 and the address registers 12 and 13 synchronously operate and execute writing at a clock cycle next to that when input data is read. One arithmetic and logic computing element 10 and two address computing elements 12 and 13 can independently fetch data from the regisiter file 11 and independently write data and therefore the transfer of data is not required.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer having a plurality of calculators for calculating a plurality of word lengths.

[0002]

2. Description of the Related Art Conventional microcomputers of this type are
It has an arithmetic and logic unit for data calculation and an address unit for address calculation. In particular, the attress arithmetic unit is equipped with an address arithmetic unit capable of generating at least two addresses in order to transfer the two input data of the arithmetic logic unit from the memory.

A conventional example is shown in FIG. In this example, it has one arithmetic logic operation unit 10, a register file 11, two independent address operation units 12 and 13, and an address operation register file 14. The address operation register file 14 has eight registers of one word length dp0, dp1, dp2, dp3 for two address operators and dn0, dn1, dn2, dn3. Further, the register file 11 has eight registers each having a word length for arithmetic and logic operation units. The registers are r0H and r0L, r1H and r1L, r2H and r2.
L, r3H, and r3L have a 2-word length register pair configuration, and the word length can be selectively determined depending on the type of operation of the arithmetic operation unit.

The arithmetic logic unit 10 and the register file 11 are connected to each other by buses 7-9. The address arithmetic units 12 and 13 and the address arithmetic register file 14 are connected to each other by buses 1 to 6. Further, the register files 11 and 14 are connected to each other by a register transfer bus 15.

According to this structure, the output result of the arithmetic and logic unit 10 is stored in the register file 11. Input / output of the address calculators 12 and 13 is the register file 1
Limited to 4. So two register files 1
The register transfer bus 15 is used for transferring the data of 1 and 14 so that the operation result of the arithmetic logic unit can be used for the address operation, or vice versa. The register transfer bus 15 has a bit width of one word length, and transfer is possible between all the registers in the register files 11 and 14. Therefore, the operation result of the arithmetic logic operation unit 10 is calculated by the address operation units 12, 1
In order to use it for the address calculation in 3, the output result of the arithmetic and logic unit 10 is once output to the register file 11 and then data is transferred from the register file 11 to the register file 14 by an instruction, and then the address calculator 1
Address calculation is performed at 2 and 13.

[0006]

In the above-mentioned conventional configuration, the register 11 used by the arithmetic logic operation unit 10 and the register 14 used by the address operation units 12 and 13 are different in type, and the arithmetic logic operation unit is used. When the calculation result in 10 is used as an address, the data must be transferred through the register transfer bus 15, which causes an increase in processing time and complexity of the program, and it is necessary to temporarily hold the same data. Therefore, there is a problem that extra registers are needed and resources on the hardware are wasted. An object of the present invention is to provide a microcomputer arithmetic unit capable of shortening processing time and reducing registers.

[0007]

According to the present invention, at least two independent address arithmetic units that mainly perform address arithmetic, at least one arithmetic logic arithmetic unit, and an address arithmetic unit and an arithmetic logic arithmetic unit are respectively connected. And a registered register file. This register file has a register or a register pair having a bit length of 2 words or more, which can also be used as at least two sets of at least two 1 word length registers, and has at least 2 as an input to an arithmetic logic unit. One or more registers can be selectively selected and set in word length, and at least one or more registers can be selectively selected and set as output, while at least two or more registers can be set as input to the address calculator. Registers can be selectively selected and set in word length, and at least one or more registers can be selectively selected and set as outputs.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention. 1
Arithmetic logic operation unit 10 that can selectively set word length or 2-word length data to each input / output independently, and two independent address operation units 12 and 13 that operate 1-word length data
And four 1-word-length register files 11 each of which can be used as a 2-word-length register pair. Then, with respect to the register file 11, the address arithmetic units 12 and 13 are interconnected using the buses 1 to 6 and the arithmetic logic arithmetic unit 10 is interconnected to each other using the buses 7 to 9.

The first address calculator 12 has a word length of 2
It has one input and one output, also one word long,
The 1-word-length bus 1 is connected to the first input of the first address calculator, and the 1-word-length bus 2 is connected to the second input of the first address calculator. The output of the first address calculator 12 is connected to the bus 5 having a length of one word. In addition, the second address calculator 13 has a word length of 2
It has one input and one output, also one word long,
The 1-word-length bus 3 is connected to the first input of the second address calculator, and the 1-word-length bus 4 is connected to the second input of the second address calculator. The output of the second address calculator is connected to the 1-word-long bus 6.

The arithmetic logic operation unit 10 selectively outputs two inputs which can selectively input 1-word length or 2-word length data and 1-word length or 2-word length data. It has a single input which can be connected to a bus 7 having a length of 2 words and a first input of an arithmetic unit.
A bus 8 which is also two words long and is connected to the second input of the arithmetic operation unit. The output of this arithmetic operation unit is connected to a bus 9 having a length of 2 words.

The register file 11 comprises four 1-word length registers r0H, r0L, r1H, and r1L. The r0H register and r0L register, and the r1H register and r1L register are operated as a 2-word length register pair r0 and r1. You can r0H and r1L or r0H
It does not matter whether or not other combinations such as r1H and r1H can be operated as a register pair, but it is impossible in the present embodiment.

R0H or r1H can be selectively output to the bus 1 of 1 word length, and r0L or r1L can be selectively output to the bus 2 of 1 word length. Further, r0H or r1H can be selectively output to the one-word-length bus 3, and r0L or r1L can be selectively output to the one-word-length bus 4. R0H or r1H can be selectively output to the upper one word length and r0L or r1L can be selectively output to the lower one word length to the bus 7 having a two word length. For bus 9 of 2 word length, r0H from the upper 1 word length
Alternatively, it can be selectively input to r1H, and the lower 1
The word length can be selectively input to r0L or r1L.

From the bus 5 of one word length, r0H or r1H
Can be selectively input to r0 from the 1-word bus 6
H or r1H can be selectively input. However, 2
It is not always necessary to output 2-word length data to the word-length bus, and similarly, it is not necessary to input 2-word length data from the 2-word length bus. You may write only. Further, here, the description has been given on the assumption that the buses 5 and 6 can selectively input to r0H or r1H, but it is also possible to selectively input to r0L and r1L.

According to this structure, one arithmetic and logic unit 10 and two address and arithmetic units 12 and 13 operate synchronously, and writing is performed in the next clock cycle after reading the input data. One arithmetic logic operation unit 10 and two address operation units 12 and 13 can independently take in data from the register file 11 and write the data independently. The arithmetic logic operation unit 10 and the first address operation unit 1
2, the output result of the second address arithmetic unit 13 in the next cycle arithmetic logic unit 10, the first address arithmetic unit 12,
It is possible to perform an operation as an input of the second address operation unit 13, and it is possible to combine many data operations without having to transfer data.

FIG. 2 is a block diagram of a second embodiment of the present invention, in which parts equivalent to those of the first embodiment are designated by the same reference numerals. In the first embodiment, the register file 11 has one word length and two words.
While only the combination of word lengths can be performed, in this second embodiment, a 1/2 word length register is added to the register file 11 so that 0.5 / 1 / 1.5 / 2 / 2.5 word length data can be handled respectively. It is the one. In the present embodiment, the added register has a 1/2 word length, but it can have an arbitrary bit length. In addition, the number of registers has been increased to a maximum of four 2.5 word length register pairs. With this, bus 7,
8 and 9 are 2.5 word length buses, and the upper 0.5 word length is r0e,
Input / output to / from r1e, r2e, and r3e.

From the results of various benchmarks, the number of registers required for this type of microcomputer is at least four for three arithmetic units, and at least 8 if the performance is taken into consideration. Books are considered necessary, so increasing the number of books and setting the optimal bit length
It should be decided depending on the type and number of arithmetic units.

[0017]

As described above, according to the present invention, since the register is shared by the arithmetic logic unit and the address arithmetic unit, when the arithmetic result of the arithmetic logic unit is used as an address, the internal bus is used. There is an effect that it is not necessary to transfer data, processing time is shortened, software is simplified, and hardware resources can be efficiently used.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of a microcomputer arithmetic unit of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of a conventional microcomputer arithmetic unit.

[Explanation of Codes] 1-6 Address arithmetic unit bus 7-9 Arithmetic logic arithmetic unit bus 10 Arithmetic logic arithmetic unit 11 register file 12, 13 Address arithmetic unit 14 Address arithmetic register file

Claims (1)

[Claims] 1. At least 2 which mainly perform address calculation.
There are two independent address arithmetic units, at least one arithmetic logic unit, and register files respectively connected to the address arithmetic unit and the arithmetic logic unit, and the register file includes at least two sets of at least two. It has a register or a register pair having a bit length of 2 words or more that can also be used as one 1 word length register, and at least 2 or more registers are selectively selected as an input to the arithmetic and logic unit. , And at least one or more registers can be selectively selected and set as outputs, while at least two or more registers can be selectively selected and set as inputs to the address calculator. , And at least one or more registers can be set as outputs by selectively selecting the word length. Computer arithmetic unit.