JPH06197048A - Automatic adaptive equalizer - Google Patents

Abstract

PURPOSE:To attain equalization even when a frequency spectrum is deviated from an ideal spectrum distribution by using a demodulated base band signal to control an amplitude distortion equalizer or a delay distortion equalizer in an adaptive equalization means. CONSTITUTION:A control signal generating means 41 extracts an in-phase control signal Re and an orthogonal control signal Im relating to a transversal equalizer from demodulation signals DP, DQ and error signals YP, YQ from a demodulation means 42. An adder subtractor and averaging means 40 is provided with adder subtractor means 23-26 and averaging means 19-22 receiving the signals Re, Im and outputting a control signal required to equalizers 15-18 for amplitude distortion or delay distortion and adds or subtracts the signals Re, Im and averages them and outputs the result to an adaptive equalization means 39 as a control signal. Thus, even when a frequency spectrum is deviated from an ideal frequency spectrum distribution, accurate equalization is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic adaptive equalizer, and more particularly to an automatic adaptive equalizer for improving transmission distortion equalization characteristics in a digital radio transmission system.

[0002]

2. Description of the Related Art A conventional automatic adaptive equalizer has a secondary amplitude distortion equalizer 1 and a primary amplitude distortion equalizer 2 as adaptive equalizing means, as shown in FIG. And the intermediate frequency signal input from the terminal 101 is equalized in the secondary amplitude distortion equalizer 1 and the primary amplitude equalizer 2 with the secondary amplitude distortion and the primary amplitude distortion, respectively. It is output from the terminal 102. FIG. 4 shows an example of the amplitude frequency characteristic of the intermediate frequency signal input from the terminal 101. In this example, the first-order amplitude distortion corresponding to the difference in amplitude level at the frequencies f ₋ and f ₊ , There is a second-order amplitude distortion corresponding to a decrease in the amplitude level at the center frequency f ₀ .
The selection filters 3, 4 and 5 in FIG. 3 have their respective selection frequencies set to f ₋ , f ₊ and f ₀ , and outputs S (f ₋ ) and S (f ₊ ) of the selection filters 3 and 4 are set. Control signal | S to the first-order amplitude distortion equalizer 2 via the subtracting amplifier 6 via the resistors R ₁ and R _2.
(F ₋ ) −S (f ₊ ) |
_- )-S (f _<+> ) | is controlled so that the first-order amplitude distortion equalizer 2 is minimized. Further, the outputs S (f ₋ ), S (f ₊ ) and S (f ₀ ) of the selection filters 3, 4 and 5 are supplied to the control signal | {S
(F ₋ ) + S (f ₊ )} / 2−S (f ₀ ) |, and this | {S (f ₋ ) + S (f ₊ )} / 2−S (f
₀ ) | controls the second-order amplitude distortion equalizer 1 so as to minimize.

As described above, the intermediate frequency signal input from the terminal 101 through the control action on the first-order amplitude distortion equalizer 2 and the second-order amplitude distortion equalizer 1 is the first-order and second-order signals. Is equalized and output from the terminal 102. A specific example of the first-order amplitude distortion equalizer 2 and the second-order amplitude distortion equalizer 1 is shown in FIG. 5 as a block diagram showing a main part thereof. In FIG. 5, the intermediate frequency signal input from the terminal 103 is split into two at a predetermined level in the branch circuit 8, one is input to the branch circuit 10 via the delay circuit 9, and the other is input to the combining circuit 12. To be done. In the synthesizing circuit 12, the signal that is bifurcated to a predetermined level in the branch circuit 10 and is input via the delay circuit 11 and the signal that is input from the branch circuit 8 as described above are combined, and the control circuit 14 Send to. In the control circuit 14, the terminal 1
The level of the signal input from the synthesizing circuit 12 is controlled by the control signal input from 05 and sent to the synthesizing circuit 13. In the synthesizing circuit 13, the other signal branched in the branching circuit 10 and the level-controlled signal output from the control circuit 14 are input and synthesized, and the terminal 10
Output via 4. A hybrid circuit or the like in the intermediate frequency band is usually used for the branch circuit and the combining circuit in FIG.

Since the specific examples of the first-order and second-order amplitude distortion equalizers are used as elements constituting the adaptive equalizing means also in the embodiments of the present invention described later, the essential points of the operation principle thereof will be described. explain.

Assuming that the delay time of the delay circuits 9 and 11 in FIG. 5 is T (sec), the angular frequency of the signal of interest is ω (Ras / sec), and the control coefficient of the control circuit 14 is α, then from the terminal 103. Input signal exp
The output signal S ₀ from the terminal 104 corresponding to (jωt)
(T) is shown by Formula (1).

[0006]

As is clear from the equation (1), the transfer function for the signal exp (jω (t−T)) of the circuit shown in FIG. 5 is (1 + 2αcosωT), and since the imaginary component is not included, α is changed. However, only the amplitude component changes trigonometrically, and the phase and delay time are constant on the frequency axis. That is, the amplitude distortion equalization characteristic is defined by the following equation (2).

Amplitude Distortion Characteristic → 1 + 2α cos ωT (2) Referring to the above equation (2), when the equalizer shown in FIG. 5 is used as a first-order amplitude distortion equalizer, the delay circuit in FIG. The delay time T of 9 and 11 is ω ₀ T = (2m−
1) Set to be π / 2 (m is a positive integer). Here, ω ₀ is the angular frequency corresponding to the center frequency f ₀ in FIG. By setting the value of T in this way,
In the vicinity of the center frequency f ₀ , a sine function is used,
A first-order amplitude distortion equalizer characteristic having an approximately linear gradient is obtained. Next, when it is used as a secondary amplitude distortion equalizer, the delay time T is set so that ω ₀ T = 2mπ (m is a positive integer). Accordingly, the above formula (2)
As is clear from the above, in the vicinity of the center frequency f ₀ , the second-order amplitude distortion is equalized by approximation using a cosine function.

An example of the conventional automatic adaptive equalizer including the first-order amplitude distortion equalizer and the second-order amplitude distortion equalizer has been described above. However, at least one of the amplitude distortion equalizers is provided. If you have.

[0010]

However, such a conventional automatic adaptive equalizer, in the equalization of the amplitude distortion, has a part of the frequencies (f ₀ , f ₊ ,
Only the 3 points of f ₋ ) are observed and only the spectrum at that frequency is equalized so as to have an ideal value. Therefore, at other frequencies, there is a deviation from the ideal value, resulting in a demodulated baseband signal at the sampling time. Even if the amplitude distortion occurs, there is a drawback that further equalization is not performed.
When considering the combined use of this automatic adaptive equalizer and a transversal equalizer as a countermeasure against intersymbol interference, of course, mutual synergistic effects can be expected. Since it requires a control circuit for controlling, there is a disadvantage that the circuit configuration is unnecessarily duplicated. Further, since the control signal for equalization is extracted from the frequency spectrum of the signal, the target of distortion equalization is limited to amplitude distortion only, and there is a drawback that it cannot be applied to group delay distortion at all.

[0011]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, and to demodulate a in-phase control signal and a quadrature control signal corresponding to a transversal equalizer from a predetermined demodulation means. Control signal generating means for extracting from the error signal, and addition and subtraction and averaging means for inputting the in-phase control signal and the quadrature control signal and outputting a control signal corresponding to each distortion equalizer of amplitude distortion or delay distortion. By including the transmission distortion to be equalized can be detected based on the demodulated signal at the sample time, and the circuit configuration can be efficiently formed when used in combination with the transversal equalizer. Another object of the present invention is to provide an automatic adaptive equalizer that can be applied to both amplitude distortion and delay distortion.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a main part of a first embodiment of the present invention. As shown in FIG. 1, the automatic adaptive equalizer of the present invention comprises an adaptive equalizer 39, an addition / subtraction / averaging means 40, a control signal generator 41, and a demodulator 42. The adaptive equalizer 39 is a second-order delay distortion equalizer 15, a first-order delay distortion equalizer 16, and a first-order amplitude distortion equalizer 17.
And quadratic amplitude distortion equalizer 18, addition / subtraction and averaging means 40 includes averaging circuits 19, 20, 21 and 22, subtraction circuits 23 and 25, and adding circuits 24 and 26, and control signal generating means 41. Is an exclusive OR circuit 27, 2
8, 29, 31, 32 and 33 and exclusive NOR circuit 3
0 and 34 and shift registers 35, 36, 37 and 38.

In the figure, a configuration for achieving all the objects of the present invention is shown for the sake of simplification of description.
In order to achieve the individual objects of the present invention, the adaptive equalizing means 39 may be provided with at least one equalizer,
Further, the addition / subtraction and averaging means 40 and the control signal generating means 41 need only have internal circuits for controlling the equalizer.

In FIG. 1, the intermediate frequency signal input from the terminal 106 is input to the adaptive equalizing means 39, and four types of control are input from the adding / subtracting and averaging means 40 to the adaptive equalizing means 39. Amplitude distortion and phase distortion are equalized by the signal and sent to the demodulation means 42. Demodulation means 42
Is generally provided with a phase detector, a level discriminator, an error signal generator, a clock synchronization circuit, etc., and a predetermined demodulation output signal in a state where the adaptive equalizer 39 is operating normally. Is output via terminals 107-110. The demodulation means 42 produces the control signal for equalizing the first-order and second-order amplitude distortions and the first-order and second-order delay distortions in the adaptive equalization means 39 with the demodulation output signal. At the same time, demodulated signals D _P and D _Q and error signal Y
Control signal generating means 4 for _P and Y _Q and a clock signal
Send to 1.

In a transversal type equalizer using a transversal filter, the error signal Y is obtained by a so-called ZF (zero forcing) algorithm.
By taking the correlation between _P and Y _Q and the demodulated signals D _P and D _Q , the tap coefficient that minimizes the waveform distortion is obtained. The ZF algorithm and the method of obtaining the correlation are described in Japanese Patent Application No. Sho 56-21527 (Japanese Patent Laid-Open No.
The details are described in "Automatic Equalizer", and detailed description thereof will be omitted. The correlation circuit for obtaining the above-mentioned correlation is realized by using an exclusive OR circuit.

[0017] In the control signal generating means 41, the shift register 37 and 38, wherein the demodulated signal D _P and D _Q, respectively, the clock signal and to input, 1 bit each demodulated signal D _P and D _Q The delayed demodulated signals D _{P (-1)} and D _{Q (-1)} are output, and the exclusive OR circuits 31 and 33 and the exclusive OR circuit 3 are output, respectively.
2 and the exclusive NOR circuit 34. On the other hand, in the shift registers 35 and 36, the error signals Y _P and Y _Q and the clock signal are input, and the error signals Y _P and Y _Q are delayed by 1 bit, respectively, and the error signal Y _{P (+ 1)} and Y _{Q (+1)} are output, and the exclusive OR circuit 27 and the exclusive NOR circuit 30 are output, respectively.
To the exclusive OR circuits 28 and 29. In addition, the demodulated signals D _P and D _Q and the error signal Y _P
1 and Y _Q are directly connected to the exclusive OR circuits 27 and 29, the exclusive OR circuit 28 and the exclusive NOR circuit 30 without passing through the shift registers 35 to 38, as shown in FIG. , Exclusive OR circuit 31 and exclusive NOR circuit 34, and exclusive OR circuits 32 and 33
Entered in and.

The outputs of the exclusive OR circuits 27 and 28 are added via the resistors R ₃ and R ₄ , and the exclusive OR circuit 2 is added.
9 and the outputs of the exclusive NOR circuit 30 are added via resistors R ₅ and R ₆ , and the exclusive OR circuits 31 and 32 are added.
The output of the adder via a resistor R ₇ and R _8, the output of the exclusive OR circuit 33 and exclusive NOR circuit 34 are summed via a resistor R ₉ and R _10, the aforementioned Japanese Patent Application No. Sho 56
Respectively, as is described in -215,271 given by the following formula (3) in-phase control signal R _e (-1), the orthogonal control signal I _m (-1), in-phase control signal R _e (+1) and quadrature control signals I _m (+1) is generated.

[0019] _{R e (-1) = D P} · Y P (+1) + D Q · Y Q (+1) I m (-1) = D P · Y Q (+1) -D Q · Y P _{(+1) Re} (+1) = D _{P (-1)}・ Y _P + D _{Q (-1)}・ Y _{Q Im} (+1) = D _{P (-1)}・ Y _Q −D _{Q (-1)} - Y _P ... (3) where, in the formula (3), "-" represents an exclusive OR.

The above formula (3) R _e (-1) in and I _m (-1), the tap corresponding to the (-1) tap (1 bit advanced tap the main tap) in transversal filter represents a real part of the coefficient and an imaginary part, R _e (+1) and I _m (+1), like (+1) taps real tap coefficients corresponding to (1-bit delay taps to the main tap) Represents a part and an imaginary part.

The above-mentioned in-phase control signals R _e (-1) and R _e
e (+1) and the orthogonal control signals I _m (-1) and I
_{The m} (+1) is output from the control signal generating means 41 and input to the adding / subtracting and averaging means 40, and the R _e (−)
1) and R _e (+1) are applied to the subtraction circuit 23 and the I _m (−)
1) and I _m (+1) are added to the adder circuit 24, and I _m (−)
1) and I _m (+1) are supplied to the subtraction circuit 25, and the _Re (-)
1) and R _e (+1) are input to the adder circuit 26, respectively, and R _e (−1) −R _e (+1) and I _m (−), respectively.
1) + I _m (+1), I _m (−1) −I _m (+1) and R _e (−1) + R _e (+1) are generated and input to the averaging circuits 19 to 22 to calculate the time average. The second-order delay distortion equalizer 1 is smoothed by taking
5, the signals are input to the first-order delay distortion equalizer 16, the first-order amplitude distortion equalizer 17, and the second-order amplitude distortion equalizer 18 as respective control signals for distortion equalization. 1 in adaptive equalizer 39
Specific examples of the second-order amplitude distortion equalizer 17 and the second-order amplitude distortion equalizer 18 are the same as those of the equalizer shown in FIG. As will be described later, the control coefficient α of the equation (2) is the orthogonal control signal I _m (−
1) -I _m (+1) time-averaged {I _m (-1) -I
The average value of _m (+1)} is used, and in the case of the second-order amplitude distortion equalizer, the in-phase control signals _Re (-1) + _Re (+1) are time-averaged { _Re (-1) + _Re. The average value of (+1)} is used. Further, specific examples of the first-order delay distortion equalizer 16 and the second-order delay distortion equalizer 15 are shown in FIGS. 6 and 7, respectively. Since specific examples of the first-order amplitude distortion equalizer 17 and the second-order amplitude distortion equalizer 18 have already been described, the description thereof is omitted here, and the first-order delay distortion equalizer 16 and the second-order amplitude distortion equalizer 18 are omitted. Specific examples of the delay distortion equalizer 15 will be described.

FIG. 6 is a block diagram showing a main part of a concrete example of the first-order delay distortion equalizer. The intermediate frequency signal inputted from the terminal 115 is subtracted from the delay circuit 48 having a delay time T ″ (sec). It is input to the circuit 52. The output of the delay circuit 48 is input to the delay circuit 49 having a delay time T (sec), and
It is input to the subtraction circuit 54. The output of the delay circuit 49 is input to the delay circuit 50 having a delay time T (sec.) And the combining circuit 56, and the output of the delay circuit 50 has a delay time T ″.
It is input to the subtraction circuit 52 via the delay circuit 51 of (sec.). In the subtraction circuit 52, the difference between the signal input from the terminal 115 and the signal input from the delay circuit 51 is calculated, and the difference output is input to the synthesis circuit 53. In the subtraction circuit 54, the output signal of the delay circuit 48 and the output signal of the delay circuit 50 are input, and the difference signal thereof is output and input to the synthesis circuit 53. In the combining circuit 53, the difference output signal from the subtracting circuit 52 and the subtracting circuit 54
The difference output signal from is input and synthesized, and the control circuit 5
In 5, the combined signal input from the combining circuit 53 is changed by the predetermined control signal input from the terminal 116.
The level is controlled, output, and sent to the synthesis circuit 56. In the combining circuit 56, the output signal from the control circuit 55 and the output signal from the delay circuit 49 are input, combined, and output via the terminal 117. Now, assuming that the control coefficient in the control circuit 55 is α, the transfer function H (jω) from the terminal 115 to the terminal 117 is expressed by the following equation (4).
Given by.

H (jω) = 1 + j2α (sinωT + sinωT ′) (4) (T ′ = T + T ″ in the above equation) The phase characteristic θ (ω) is obtained from the above equation (4), and the delay time characteristic τ (ω) is calculated. Equation (5) is obtained by calculation.

[0024]

An example of delay time characteristics of this first-order delay distortion equalizer is shown in FIG. 8 with the control signal level as a parameter.
As the control coefficient α, the orthogonal control signal I _m (−1) + I _m (+1) is time-averaged {I _m (−) as described later.
The average value of 1) + I _m (+1)} is used.

Next, FIG. 7 is a block diagram showing a main part of one concrete example of the second-order delay distortion equalizer. In FIG. 7, terminal 1
The intermediate frequency signal input from 18 has a delay time T (se
c. ) Are input to the delay circuit 57 and the subtraction circuit 59. The output of the delay circuit 57 is input to the delay circuit 58 and the synthesizing circuit 61 having the same delay time T (sec.). Delay circuit 58
Is output to the subtraction circuit 59, the difference between the output signal and the intermediate frequency signal input from the terminal 118 is calculated, and the difference output signal is input to the control circuit 60. In the control circuit 60, the level of the difference signal input from the subtraction circuit 59 is controlled by a predetermined control signal input from the terminal 119, and the difference signal is output to the combining circuit 61. In the combining circuit 61, the output signal from the control circuit 60 and the output signal from the delay circuit 57 are input, combined, and output via the terminal 120. When the control coefficient in the control circuit 60 is α, the delay time characteristic τ (ω) between the terminals 118 and 120 is given by the equation (6).

[0027]

FIG. 9 shows an example of the delay time characteristic of this second-order delay distortion equalizer with the control signal level as a parameter.
Incidentally, as a control factor alpha, as described below, phase control signal _{R e (-1) -R e (} +1) obtained by averaging the time {R _e (-
The average value of 1) -R _e (+1)} is used.

The in-phase control signals R _e (-1) and R described above are used.
_e (+1) is the real part of the tap coefficients C ₋₁ and C ₊₁ corresponding to tap (−1) and tap (+1), respectively, and also the orthogonal control signals I _m (−1) and I
_m (+1) is the imaginary part of the tap coefficients C _-1 and C ₊₁ corresponding to tap (-1) and tap (+1), respectively. That is, C ₋₁ = R _e (−1) + jI _m (−1) C ₊₁ = R _e (+1) + jI _m (+1). Therefore, from taps (-1) and (+1),
The transfer functions corresponding to the transversal equalizers, which are added via the multiplier having the tap coefficients C _-1 and C ₊₁ as multipliers, are given by the equations (7) and (8).

[0030]

[0031]

The relationship between the transversal equalizer and the amplitude distortion / delay distortion equalizer is well known.
"DATA TRAN" issued in year 0 (1965)
SMISSION "(WILLIAM R. BENNE
TT, JAMES R. DAVEY, MCGRAW-
HILL) pp. 269-273,
The details will be described below with reference to the drawings.

FIG. 10 shows the real part and the imaginary part on the horizontal axis and the vertical axis, respectively, of S ₀ , S _-1 and S ₊₁ for explaining the relationship between the amplitude or group delay and the transversal equalizer. It is a vector diagram.

FIG. 10A shows the case where the multipliers of S _-1 and S ₊₁ are equal (each component pair is even symmetric), and the component of S ₊₁ gradually increases with S as the input signal increases. _The phase is later than ₀ , while the component of S _-1 is ahead of S ₀ , but the sum of the three S ₀₁
It can be seen that in the same phase as S ₀ , only the amplitude changes.
Therefore, the real part (horizontal axis) represents the change in amplitude.

On the other hand, FIG. 10B shows the case where the polarities of the component pairs are opposite (odd symmetry), and it can be seen that the amplitude change is small and the phase (θ) is changed. Therefore, the imaginary part represents the change in phase. Since the group delay is the frequency derivative of the phase, the imaginary part obtained by frequency differentiating H _(W) represents the group delay.

It is apparent that the first-order distortion can be approximated by a sine wave and the second-order distortion can be approximated by a cosine wave for each of the amplitude and the group delay. As described above, the coefficient R _e (−1) + R of cos ωT in the real number part of the above equation (7)
Coefficient I _m (−1) −I _{m of e} (+1) and sin ωT
From (+1), equalization control signals for the second-order amplitude distortion and the first-order amplitude distortion are obtained, respectively, and the above equation (8) is obtained.
CosωT coefficient R _e (−1) −R in the imaginary part
Coefficient I _m (−1) + I _{m of e} (+1) and sin ωT
It is clear that the equalization control signals for the second-order delay distortion and the first-order delay distortion are obtained from (+1), respectively.

Therefore, as the control coefficient α, when the amplitude distortion equalizer having the amplitude distortion equalization characteristic of the equation (2) is used as the primary amplitude distortion equalizer, α = {I _m (− 1) -I _m
The average value of (+1)} may be used, and when used as a second-order amplitude distortion equalizer, α = {R _e (−1) + R
The average value of _e (+1)} may be used. Also, equation (5)
In the case of the first-order delay distortion equalizer of, α = {I _m (−1) +
The average value of I _m (+1)} may be used, and 2 in the formula (6) is used.
In the case of the next delay distortion equalizer, α = {R _e (−1) −R _e
The average value of (+1)} may be used.

These control signals are transmitted as shown in FIG.
6 and 7, corresponding control circuits of the first-order amplitude distortion equalizer, the second-order amplitude distortion equalizer, the first-order delay distortion equalizer, and the second-order delay distortion equalizer are shown. Is input to the first and second order amplitude distortions and the first and second order delay distortions are equalized. Moreover, since the control signal is obtained by the control information from the demodulated baseband signal waveform,
Distortion due to internal factors of the device itself can be properly equalized.

FIG. 2 is a block diagram showing a main part when the automatic adaptive equalizer of FIG. 1 and the transversal equalizer are used together. As shown in FIG. 2, the automatic adaptive equalizer of the present invention comprises an adaptive equalizer 43, an adder / subtractor and averaging unit 44, a transversal filter 45, a control signal generator 46, and a demodulator. And 47. The adaptive equalization means 43 and the addition / subtraction and averaging means 44 are formed similarly to the adaptive equalization means 39 and the addition / subtraction and averaging means 41 in the first embodiment, respectively.
Further, regarding matters related to the operation contents of the transversal filter 45, the control signal generating means 46 and the demodulating means 47, for example, the above-mentioned Japanese Patent Application No. 56-215271 (Japanese Patent Application Laid-Open No. 58-111519) "Automatic etc." Since it has been described in detail in the description of "Chemicalizer", detailed description regarding the operation contents of each of these means will be omitted. In FIG. 2, a predetermined demodulation signal is output from the demodulation means 47 to the terminal 11
1, 112, 113 and 114, and at the same time, demodulated signals D _P and D _Q and a main tap control error signal Y _P1 corresponding to the transversal filter.
And Y _Q1 , the above-mentioned error signals (abbreviation of other tap control error signals) Y _P and Y _Q, and the clock signal are output and input to the control signal generating means 46. In the control signal generating means 46, the demodulated signal, the error signal and the clock signal are input, and the in-phase control signal _Re (-1),
R _e (0) and R _e (+1) and the orthogonal control signal I
_m (−1) and I _m (+1) are generated and output, and to the addition / subtraction and averaging means 44, the in-phase control signals R _e (−1) and R _e (+1) and the quadrature are output. Sends out control signals I _m (−1) and I _m (+1), and
For the transversal filter 45, the in-phase control signals _Re (-1), _Re (0) and _Re (+1).
And the orthogonal control signals I _m (−1) and I _m (+1)
And. Here, the orthogonal control signal R _e (0) is the demodulation signals D _P and D _Q and the main tap control error signal Y _P1.
A control signal corresponding to the main tap of the transversal filter 45 obtained from the exclusive OR circuit and the addition circuit from Y _Q1 and Y _Q1 and given by the following equation (9).

[0040] In _{R e (0) = D P} · Y P1 + D Q · Y Q1 ... (9) adding and subtracting and averaging means 44 inputs the in-phase control signal and the quadrature control signals, the adaptive equalization means Four
Equalization control signal {R _e (-1) + R _e (+
1)} average value, {I _m (−1) −I _m (+1)} average value, {R _e (−1) −R _e (+1)} average value and {I _m (−1) The average value of + I _m (+1)} is output.
The operations of the addition / subtraction and averaging means 44 and the adaptive equalization means 43 have already been described. On the other hand, the in-phase control signal _Re (-) for the transversal filter output from the control signal generating means 46.
1), R _e (0) and R _e (+1), and the quadrature control signals I _m (−1) and I _m (+1) are input to the transversal filter 45 and each tap weighting control action is performed. The inter-symbol interference of the signal input to the transversal filter 45 via the adaptive equalization means 43 is removed. The details of this operation are described in detail, for example, in Japanese Patent Application No. 56-215271.
In this embodiment, control signal generating means for equalizing the first-order and second-order amplitude distortion and the first-order and second-order delay distortion,
Since the control signal generating means for the transversal filter for removing the intersymbol interference is shared, the circuit configuration is simplified as a whole.

Further, in the embodiment shown in FIGS. 1 and 2, the adaptive equalizer has first-order and second-order amplitude distortion equalizers and first-order and second-order delay distortion equalizers. However, in response to the purpose of the present invention or the actual state of transmission distortion,
It is not necessary to have all these equalizers. Therefore,
A specific one of these equalizers or a specific plurality of equalizers is used to form the adaptive equalization means,
It is possible to configure the automatic adaptive equalizer of the present invention.

For example, when only the first-order amplitude distortion equalizer 17 is required as the adaptive equalizing means, the adding / subtracting and averaging means includes the averaging circuit 21 and the subtracting circuit 25, and the control signal generating means is exclusive. Exclusive N with OR circuits 29 and 33
OR circuits 30 and 34 and shift registers 35 and 3
6, 37, 38 may be provided. When the first-order delay distortion equalizer 16 is added to this adaptive equalizing means, the averaging circuit 20 and the adding circuit 24 may be added to the adding / subtracting and averaging means.

When both the adaptive equalizer having only the first-order amplitude distortion equalizer 17 and the transversal equalizer are used together, the control signal generator has all the circuits shown in FIG. The averaging means include I _m (+1) and I
Only _m (−1) is supplied and supplied to the first-order amplitude distortion equalizer 17 via the subtraction circuit 25 and the averaging circuit 21.

[0044]

As described above, according to the present invention, the transmission distortion to be equalized is detected not based on the frequency spectrum but on the demodulated baseband signal waveform at the sampling time. Therefore, the amplitude distortion is detected from the frequency spectrum. As compared with the conventional automatic adaptive equalizer, the present invention has an effect that it can perform very accurate equalization and can also equalize internal distortion caused by the device itself. Further, when it is necessary to use a combination with a transversal type equalizer as a countermeasure against intersymbol interference, the control signal generation means can be shared for both equalization functions, and the circuit configuration is It has the effect of being simplified. Further, the present invention applies the other tap control signal corresponding to the transversal equalizer as an equalization control signal for the amplitude distortion and the delay distortion, thereby equalizing not only the amplitude distortion but also the delay distortion. There is an effect that it becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a first embodiment of the present invention.

FIG. 2 is a block diagram showing a main part of a second embodiment of the present invention.

FIG. 3 is a block diagram showing a main part of a conventional automatic adaptive equalizer.

FIG. 4 is a block diagram showing a main part of an example of an amplitude distortion equalizer.

FIG. 5 is an amplitude frequency characteristic diagram of an intermediate frequency signal.

FIG. 6 is a block diagram showing a main part of an example of a first-order delay distortion equalizer.

FIG. 7 is a block diagram showing a main part of an example of a second-order delay distortion equalizer.

FIG. 8 is a delay time characteristic diagram of a first-order delay distortion equalizer.

FIG. 9 is a delay time characteristic diagram of a second-order delay distortion equalizer.

FIG. 10 is a diagram for explaining the relationship between in-phase and quadrature components of a transversal equalizer and amplitude distortion and group delay distortion.

[Explanation of symbols]

 8, 10 Branch circuit 9, 11, 48, 49, 51, 57, 58 Delay circuit 12, 13, 53, 56, 61 Combined circuit 14, 55, 60 Control circuit 15 Second-order delay distortion equalizer 16 First-order delay Distortion equalizer 17 1st-order amplitude distortion equalizer 18 2nd-order amplitude distortion equalizer 19-22 Averaging circuit 23, 25, 52, 54, 59 Subtraction circuit 24, 26 Addition circuit 27-29, 31-33 Exclusive OR circuit 30,34 Exclusive NOR circuit 35-38 Shift register 39,43 Adaptive equalization means 40,44 Addition / subtraction and averaging means 41,46 Control signal generation means 42,47 Demodulation means 45 Transversal filter

Claims (8)

[Claims] 1. An automatic adaptive equalizer used in a digital radio transmission system, comprising a first-order amplitude distortion equalizer for inputting a modulated wave signal and equalizing first-order amplitude distortion according to a control signal. An adaptive equalizer, a demodulated signal defined as an identification output of a baseband signal obtained by synchronously detecting the equalized output signal of the adaptive equalizer, and a predetermined reference level of the demodulated signal. Demodulation means for outputting an error signal defined as the level deviation of the signal and a predetermined clock signal, in-phase component D _P and quadrature component D _Q of the demodulated signal, and in-phase component D _P and quadrature of the demodulated signal Demodulated signals D _P (−1) and D _{Q obtained} by delaying the component D _Q by 1 bit, respectively.
(−1), the in-phase component Y _P and the quadrature component Y _Q of the error signal, and the in-phase component Y _P and the quadrature component Y _Q of the error signal, which are delayed by 1 bit, respectively, and the error signal Y _P (+
1) and Y _Q (+1), the control signal generating means for outputting a control signal represented by the following formulas A and B as a quadrature control signal by calculating the correlation between the corresponding components, and I _{m (-1) = D P ·} Y Q (+1) -D Q · Y P (+1) ... A I m (+1) = D P (-1) · Y Q -D Q (-1) · Y P B (however, “•” indicates that correlation is taken) With respect to the inputs of the orthogonal control signals I _m (−1) and I _m (+1),
As the control signal for controlling the first-order amplitude distortion equalizer,
Addition / subtraction and averaging means including a subtraction circuit for generating I _m (−1) −I _m (+1) and an averaging circuit for taking a time average of the output signal of the subtraction circuit to generate a smoothed control signal output. An automatic adaptive equalizer characterized by comprising. 2. An automatic adaptive equalizer used in a digital radio transmission system, comprising a primary amplitude distortion equalizer for inputting a modulated wave signal and equalizing primary amplitude distortion according to a control signal. An adaptive equalizer and a transformer for inputting the first equalized output signal, the quadrature control signal and the in-phase control signal of the adaptive equalizer to remove intersymbol interference from the first equalized output signal. Versal equalization means, a demodulation signal defined as an identification output of a baseband signal obtained by synchronously detecting the second equalization output signal of the transversal equalization means, and a predetermined reference of the demodulation signal. A demodulation means for outputting an error signal defined as a level deviation from the level and a predetermined clock signal, an in-phase component D _P and a quadrature component D _Q of the demodulated signal, and an in-phase component D _{P of the} demodulated signal. and交成min D _Q demodulating respectively by one bit delayed signal D _P (-1) and D _Q
(−1), the in-phase component Y _P and the quadrature component Y _Q of the error signal, and the in-phase component Y _P and the quadrature component Y _Q of the error signal, which are delayed by 1 bit, respectively, and the error signal Y _P (+
1) and Y _Q (+1) by correlating the corresponding components, respectively, to output control signals represented by the following formulas A to D as the in-phase control signal and the quadrature control signal, respectively. Signal generation means, and R _e (−1) = D _P · Y _P (+1) + D _Q · Y _Q (+1) ... A R _e (+1) = D _P (−1) · Y _P + D _Q (+1) _{· Y Q ... B I m (} -1) = D P · Y Q (+1) -D Q · Y P (+1) ... C I m (+1) = D P (-1) · Y Q -D Q ( −1) · Y _P ... D (where “·” indicates that correlation is taken), with respect to the inputs of the orthogonal control signals I _m (−1) and I _m (+1),
As the control signal for controlling the first-order amplitude distortion equalizer,
Addition / subtraction and averaging means including an arithmetic circuit for generating I _m (−1) −I _m (+1) and an averaging circuit for taking a time average of the output signals of the subtraction circuit to generate a smoothed control signal output. An automatic adaptive equalizer characterized by comprising. 3. An automatic adaptive equalizer used in a digital radio transmission system, wherein a modulated wave signal is input and cascaded in an arbitrary order, and first-order amplitude distortion is equalized according to a first control signal. An adaptive equalizer having a first-order amplitude distortion equalizer for equalizing and a second-order amplitude equalizer for equalizing second-order amplitude distortion according to a second control signal; and the adaptive equalizer. A demodulated signal defined as an identification output of a baseband signal obtained by synchronously detecting the equalized output signal of, an error signal defined as a level deviation of the demodulated signal from a predetermined reference level, and a predetermined Of the demodulated signal, an in-phase component D _P and a quadrature component D _Q of the demodulated signal, and a demodulated signal D obtained by delaying the in-phase component D _P and the quadrature component D _Q of the demodulated signal by 1 bit. _P (-1) and D _Q
(−1), the in-phase component Y _P and the quadrature component Y _Q of the error signal, and the in-phase component Y _P and the quadrature component Y _Q of the error signal, which are delayed by 1 bit, respectively, and the error signal Y _P (+
1) and Y _Q (+1) are respectively correlated between the corresponding components to generate a control signal that outputs a control signal represented by the following formulas A to D as an in-phase control signal and a quadrature control signal. Means and R _e (−1) = D _P · Y _P (+1) + D _Q · Y _Q (+1) ... A R _e (+1) = D _P (−1) · Y _P + D _Q (−1) · _{Y Q ... B I m (-1} ) = D P · Y Q (+1) -D Q · Y P (+1) ... C I m (+1) = D P (-1) · Y Q -D Q (- 1) · Y _P ... D (where “·” indicates that correlation is taken), with respect to the inputs of the orthogonal control signals I _m (−1) and I _m (+1),
A subtraction circuit for generating I _m (−1) −I _m (+1) as the first control signal for controlling the first-order amplitude distortion equalizer, and a time average of the output signal of the subtraction circuit to smooth the signal. A first averaging circuit for producing a controlled control signal output;
An adder circuit for generating the in-phase control signal _Re (-1) + _Re (+1), and a second averaging circuit for taking a time average of the output signals of the adder circuit to generate a smoothed control signal output; An automatic adaptive equalizer characterized by including addition / subtraction and averaging means including. 4. An automatic adaptive equalizer used in a digital radio transmission system, wherein a modulated wave signal is input and cascaded in an arbitrary order,
A first-order amplitude distortion equalizer that equalizes first-order amplitude distortion in accordance with the control signal, and a second-order amplitude distortion equalizer that equalizes second-order amplitude distortion in accordance with the second control signal. An adaptive equalizer and a transformer for inputting the first equalized output signal, the quadrature control signal and the in-phase control signal of the adaptive equalizer to remove intersymbol interference from the first equalized output signal. Versal equalization means, a demodulation signal defined as an identification output of a baseband signal obtained by synchronously detecting the second equalization output signal of the transversal equalization means, and a predetermined reference of the demodulation signal. A demodulation means for outputting an error signal defined as a level deviation from the level and a predetermined clock signal, an in-phase component D _P and a quadrature component D _Q of the demodulated signal, and an in-phase component D _{P of the} demodulated signal. and a 1-bit delayed quadrature component D _Q It was demodulated signal D _P (-1) and D _Q
(−1), the in-phase component Y _P and the quadrature component Y _Q of the error signal, and the in-phase component Y _P and the quadrature component Y _Q of the error signal, which are delayed by 1 bit, respectively, and the error signal Y _P (+
1) and Y _Q (+1) by correlating the corresponding components, respectively, to output control signals represented by the following formulas A to D as the in-phase control signal and the quadrature control signal, respectively. Signal generation means, and R _e (−1) = D _P · Y _P (+1) + D _Q · Y _Q (+1) ... A R _e (+1) = D _P (−1) · Y _P + D _Q (−1) _{) · Y Q ... B I m} (-1) = D P · Y Q (+1) -D Q · Y P (+1) ... C I m (+1) = D P (-1) · Y Q -D Q (−1) · Y _P ... D (where “·” indicates that correlation is taken) With respect to the inputs of the orthogonal control signals I _m (−1) and I _m (+1),
As a first control signal for controlling the first-order amplitude distortion equalizer, an arithmetic circuit that generates I _m (−1) −I _m (+1) and a smoothing by taking the time average of the output signals of the subtraction circuit. A first averaging circuit for producing a controlled control signal output;
Corresponding to the inputs of the in-phase control signals R _e (−1) and R _e (+1), the second control signal for controlling the second-order amplitude distortion equalizer is R _e (−1) + R _e. And a second averaging circuit for generating a smoothed control signal output by time-averaging the output signal of the adding circuit and a second averaging circuit. Automatic adaptive equalizer. 5. An automatic adaptive equalizer used in a digital radio transmission system, wherein a modulated wave signal is input and cascaded in an arbitrary order to equalize first-order amplitude distortion according to a first control signal. An adaptive equalizer having a first-order amplitude distortion equalizer for equalizing and a first-order delay distortion equalizer for equalizing the first-order delay distortion according to a second control signal; A demodulated signal defined as an identification output of a baseband signal obtained by synchronously detecting the equalized output signal of the means, and an error signal defined as a level deviation from a predetermined reference level of the demodulated signal, A demodulation means for outputting a predetermined clock signal; a demodulated signal obtained by delaying the in-phase component D _P and the quadrature component D _Q of the demodulated signal and the in-phase component D _P and the quadrature component D _Q of the demodulated signal by 1 bit each. D _P (-1) and D _Q
(−1), the in-phase component Y _P and the quadrature component Y _Q of the error signal, and the in-phase component Y _P and the quadrature component Y _Q of the error signal, which are delayed by 1 bit, respectively, and the error signal Y _P (+
1) and Y _Q (+1), the control signal generating means for outputting a control signal represented by the following formulas A and B as a quadrature control signal by calculating the correlation between the corresponding components, and I _{m (-1) = D P ·} Y Q (+1) -D Q · Y P (+1) ... A I m (+1) = D P (-1) · Y Q -D Q (-1) · Y P B (however, “•” indicates that correlation is taken) With respect to the inputs of the orthogonal control signals I _m (−1) and I _m (+1),
A subtraction circuit for generating I _m (−1) −I _m (+1) as the first control signal for controlling the first-order amplitude distortion equalizer, and a time average of the output signal of the subtraction circuit to smooth the signal. A first averaging circuit for producing a controlled control signal output;
As the second control signal for controlling the first-order delay distortion equalizer, an adder circuit for generating I _m (−1) + I _m (+1) and a time average of the output signals of the adder circuit are smoothed. A second averaging circuit for producing a controlled control signal output,
An automatic adaptive equalizer characterized by including addition / subtraction and averaging means including. 6. An automatic adaptive equalizer used in a digital radio transmission system, wherein a modulated wave signal is input and cascaded in an arbitrary order,
A first-order amplitude distortion equalizer that equalizes the first-order amplitude distortion in accordance with the control signal, and a first-order delay distortion equalizer that equalizes the first-order amplitude distortion in accordance with the second control signal. An adaptive equalizer and a transformer for inputting the first equalized output signal, the quadrature control signal and the in-phase control signal of the adaptive equalizer to remove intersymbol interference from the first equalized output signal. Versal equalization means, a demodulated signal defined as an identification output of a baseband signal obtained by synchronously detecting the second equalized output signal of the transversal equalization means, and a predetermined reference of the demodulated signal. A demodulation means for outputting an error signal defined as a level deviation from the level and a predetermined clock signal, an in-phase component D _P and a quadrature component D _Q of the demodulated signal, and an in-phase component D _{P of the} demodulated signal. and a 1-bit delayed quadrature component D _Q It was demodulated signal D _P (-1) and D _Q
(−1), the in-phase component Y _P and the quadrature component Y _Q of the error signal, and the in-phase component Y _P and the quadrature component Y _Q of the error signal, which are delayed by 1 bit, respectively, and the error signal Y _P (+
1) and Y _Q (+1) by correlating the corresponding components, respectively, to output control signals represented by the following formulas A to D as the in-phase control signal and the quadrature control signal, respectively. Signal generation means, and R _e (−1) = D _P · Y _P (+1) + D _Q · Y _Q (+1) ... A R _e (+1) = D _P (−1) · Y _P + D _Q (−1) _{) · Y Q ... B I m} (-1) = D P · Y Q (+1) -D Q · Y P (+1) ... C I m (+1) = D P (-1) · Y Q -D Q (−1) · Y _P ... D (where “·” indicates that correlation is taken) With respect to the inputs of the orthogonal control signals I _m (−1) and I _m (+1),
As a first control signal for controlling the first-order amplitude distortion equalizer, a time average of the output signals of the arithmetic circuit and the subtraction circuit for generating I _m (−1) −I _m (+1) and the smoothing is performed. A first averaging circuit for producing a controlled control signal output;
As the second control signal for controlling the first-order delay distortion equalizer, an adder circuit for generating I _m (−1) + I _m (+1) and a time average of the output signals of the adder circuit are smoothed. A second averaging circuit for producing a controlled control signal output,
An automatic adaptive equalizer characterized by including addition / subtraction and averaging means including. 7. An automatic adaptive equalizer used in a digital radio transmission system, comprising a secondary amplitude distortion equalizer for inputting a modulated wave signal and equalizing secondary amplitude distortion according to a control signal. An adaptive equalizer, a demodulated signal defined as an identification output of a baseband signal obtained by synchronously detecting the equalized output signal of the adaptive equalizer, and a predetermined reference level of the demodulated signal. Demodulation means for outputting an error signal defined as the level deviation of the signal and a predetermined clock signal, in-phase component D _P and quadrature component D _Q of the demodulated signal, and in-phase component D _P and quadrature of the demodulated signal Demodulated signals D _P (−1) and D _{Q obtained} by delaying the component D _Q by 1 bit, respectively.
(−1), the in-phase component Y _P and the quadrature component Y _Q of the error signal, and the in-phase component Y _P and the quadrature component Y _Q of the error signal, which are delayed by 1 bit, respectively, and the error signal Y _P (+
1) and Y _Q (+1) are respectively correlated between the corresponding components, and control signal generating means for outputting control signals represented by the following formulas A and B, respectively, as in-phase control signals, _{R e (-1) = D P} · Y P (+1) + D Q · Y Q (+1) ... A R e (+1) = D P (-1) · Y P + D Q (-1) · Y Q ... B (however, “•” indicates that the correlation is taken) With respect to the inputs of the in-phase control signals R _e (−1) and R _e (+1),
As the control signal for controlling the second-order amplitude distortion equalizer,
_{R e (-1) -R e (} +1) adder-subtracter and the averaging means comprises an averaging circuit for generating a control signal output which is smoothed through time averaging of the output signal of the addition circuit and the adder circuit generates a An automatic adaptive equalizer, comprising: 8. An automatic adaptive equalizer used in a digital radio transmission system, which comprises a secondary amplitude distortion equalizer that inputs a modulated wave signal and equalizes secondary amplitude distortion according to a control signal. Type equalizer means and a first equalized output signal, a quadrature control signal and an in-phase control signal of the adaptive equalizer means, and a transversal for removing intersymbol interference from the first equalized output signal. Equalization means, a demodulation signal defined as an identification output of a baseband signal obtained by synchronously detecting the second equalization output signal of the transversal equalization means, and a predetermined reference level of the demodulation signal Demodulating means for outputting an error signal defined as a level deviation from the above and a predetermined clock signal, an in-phase component D _P and a quadrature component D _Q of the demodulated signal, and an in-phase component D _{P of the} demodulated signal straight Demodulated signal D _P of the component D _Q respectively by one bit delay (-1) and D _Q
(−1), the in-phase component Y _P and the quadrature component Y _Q of the error signal, and the in-phase component Y _P and the quadrature component Y _Q of the error signal, which are delayed by 1 bit, respectively, and the error signal Y _P (+
1) and Y _Q (+1) by correlating the corresponding components, respectively, to output control signals represented by the following formulas A to D as the in-phase control signal and the quadrature control signal, respectively. Signal generation means, and R _e (−1) = D _P · Y _P (+1) + D _Q · Y _Q (+1) ... A R _e (+1) = D _P (−1) · Y _P + D _Q (−1) _{) · Y Q ... B I m} (-1) = D P · Y Q (+1) -D Q · Y P (+1) ... C I m (+1) = D P (-1) · Y Q -D Q (−1) · Y _P ... D (“·” indicates that correlation is taken) Corresponding to the input of the in-phase control signals _Re (−1) and _Re (+1), the secondary amplitude as the control signal for controlling the distortion _{equalizer, R e (-1) + R} e (+1) time average is taken smoothing of the output signal of the addition circuit and the adder circuit generates a Automatic adaptive equalizer, characterized in that it comprises a subtraction and averaging means comprises an averaging circuit for generating a control signal output that.