JPH06197155A - Character string reception detection circuit - Google Patents

Abstract

(57) [Summary] [Purpose] The processing load on the microprocessor can be reduced,
(EN) Provided is a character string reception / detection circuit capable of supporting high-speed data communication with a simple structure, and capable of achieving high functionality. [Structure] Shift registers 3 to 5 for sequentially shifting and outputting received communication data transferred on a line, character data of a specific character string to be detected, and output data of registers 3 to 5, respectively. compare, match if they match signal S _EQ1 to S comparator _{E Q3} and respectively output 15-1
7 and an AND gate 18 that outputs a detection signal S _EQ indicating that a specific character string is detected based on the coincidence signals S _{EQ1 to} S _EQ3 output from the comparators 15 to 17, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a protocol analyzer or the like for detecting and analyzing a failure occurring in a digital communication network such as an integrated digital network (ISDN), and detects reception of a specific character string. The present invention relates to a character string reception detection circuit.

[0002]

2. Description of the Related Art A device for monitoring communication data, such as a protocol analyzer, has a trigger function for performing a special operation when a specific character string is received. In order to realize this trigger function, , It must be certain that it has received that particular string.

Therefore, in the prior art, first, a communication data transferred on a line in accordance with a predetermined communication protocol and received is used by a microprocessor according to a predetermined protocol by using an LSI (Large Scale Integrated Circuit) called a communication controller. It is converted into data that can be processed. Then, the converted data is compared with a preset specific character string to be detected by software processing by a microprocessor to detect the specific character string.

[0004]

By the way, in a protocol analyzer or the like, in order to reliably receive the communication data transferred on the line, the microprocessor uses software processing to make the communication data faster than the data transfer speed of the received communication data. It must process the communication data at high speed. In particular, the above-mentioned trigger function is a function that puts a heavy processing load on the microprocessor, and it is necessary to process communication data at a higher speed.

In order to process communication data at high speed by software processing with a microprocessor,
Usually, in addition to the main microprocessor that controls the entire device, recording control of communication data transferred over the line and front-end microprocessor that processes the recorded data, and operation control of the front-end microprocessor, An interface microprocessor or the like for interfacing the main microprocessor with the front-end microprocessor is required. For this reason, there is a problem that the configuration of the entire device becomes complicated and causes a cost increase.

The present invention has been made under such a background. By reducing the processing load of the microprocessor, it is possible to cope with high-speed data communication with a simple structure, and further to achieve high functionality. It is an object of the present invention to provide a character string reception detection circuit that can be used.

[0007]

In order to solve the above-mentioned problems, a character string reception detection circuit according to a first aspect of the present invention is a plurality of stages of shifts for sequentially shifting and outputting the received communication data transferred on the line. Means and each character data of a specific character string to be detected, which is provided corresponding to the number of stages of the shift means,
The output data of each stage of the shift means are respectively compared, and a plurality of comparison means that output a coincidence signal when they coincide with each other, and the specific character based on the coincidence signals respectively output from these comparison means, And a detection means for outputting a detection signal indicating that a column has been detected.

[0008]

According to the above structure, since the shift means of a plurality of stages are transferred on the line and the received communication data are sequentially shifted and output, the plurality of comparing means are provided with the respective characters of the specific character string to be detected. The data and the output data of each stage of the shift means are compared with each other, and if they match, a matching signal is output. As a result, the detection unit outputs the detection signal indicating that the specific character string is detected, based on the coincidence signals output from the plurality of comparison units.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a character string reception detection circuit according to an embodiment of the present invention. In this figure, reference numeral 1 is a data input terminal for receiving received 8-bit parallel communication data, and 2 is a data input terminal. Write signal input terminals to which the received data write signal is input, and 3 to 5 are 8-bit parallel input / output shift registers, respectively. Communication data input from the data input terminal 1 is input from the write signal input terminal 2 through the shift register. The data is sequentially shifted and output in synchronization with the received reception data write signal.

Further, 6 to 8 are data input terminals for inputting respective 8-bit parallel character data of a specific character string (for example, "ABC") to be detected, and 9 to 11 are character string write signals. Write signal input terminal for inputting 1
Reference numerals 2 to 14 are 8-bit parallel input / output shift registers, respectively, in which each character data input from the data input terminals 6 to 8 is a character string write signal input from the write signal input terminals 9 to 11, respectively. It is set in synchronization with.

Further, reference numeral 15 is a comparator which compares the output data of the shift register 5 with the output data of the shift register 12, and outputs a match signal S _EQ1 of "H" level when they match, and 16 is a shift register. 4 output data,
A comparator that compares the output data of the shift register 13 and outputs a match signal S _EQ2 of "H" level when they match, 17 compares the output data of the shift register 3 with the output data of the shift register 14. Then, when they match, the comparator outputs a match signal S _EQ3 of "H" level. _Reference numeral 18 denotes a three-input AND gate to which the coincidence signals S _EQ1 to S _EQ3 are respectively input. When all the coincidence signals S _{EQ1 to} S _EQ3 are at “H” level, the coincidence signal S _EQ of “H” level is output. Output. _{Reference numeral} 19 is an output terminal to which the coincidence signal S _EQ is output.

In such a configuration, first, a microprocessor (not shown) firstly sets 8-bit parallel character data ("") of a specific character string (for example, "ABC") to be detected.
A "," B "," C ") is input from the data input terminals 6 to 8 and the character string write signal is input from the write signal input terminals 9 to 11. As a result, the character string write signal is input. In sync,
8-bit parallel character data ("A", "B", "C") are preset in the shift registers 12 to 14, respectively.

Next, the 8-bit parallel communication data transferred and received on the line is input from the data input terminal 1 via the CPU data bus (not shown), and the received data is input from the write signal input terminal 2. When the write signal is input, the shift registers 3 to 5 sequentially shift the communication data input from the data input terminal 1 in synchronization with the received data write signal input from the write signal input terminal 2. Output.

Now, the communication data input from the data input terminal 1 is the first timing T1 of the received data write signal.
Character data "A" at the second timing T2 of the received data write signal and character data "B" at the second timing T2 of the received data write signal
If the character data is "C" at the timing T3 of
At the first timing T1, the output data of the shift register 3 is the character data "A" and the output data of the shift register 14 is the character data "C". Therefore, the comparator 17 outputs the "H" level match signal S. _EQ3 is not output. Therefore, the AND gate 18 outputs the "H" level match signal S.
_EQ is not output.

Next, at the second timing T2, the shift is performed.
The output data of register 3 is character data "B",
The output data of the register 14 is character data "C".
Then, the comparator 17 outputs the coincidence signal S of "H" level._EQ3Out
I can't help. Also, the output data of the shift register 4 is a sentence.
Character data "A", output data of the shift register 13
Is the character data "B", the comparator 16 outputs "H"
Bell coincidence signal S_EQ2Is not output. Therefore,
The match signal S of "H" level from the NAND gate 18 _EQOutput
Not done.

Next, at the third timing T3, the output data of the shift register 3 is character data "C" and the output data of the shift register 14 is character data "C". An H "level coincidence signal S _EQ3 is output. Further, since the output data of the shift register 4 is the character data "B" and the output data of the shift register 13 is the character data "B", the comparator 16 also outputs the "H" level coincidence signal S _EQ2. It Further, since the output data of the shift register 5 is character data "A" and the output data of the shift register 12 is character data "A",
The comparator 15 also outputs the "H" level coincidence signal S _EQ1 . Accordingly, the AND gate 18 outputs the "H" level coincidence signal S _{EQ, which} is supplied to the CPU (central processing unit) (not shown) via the output terminal 19. As a result, the CPU (not shown) detects that the specific character string ("ABC") is received by the "H" level match signal S _EQ , and executes, for example, a trigger function.

The embodiment of the present invention has been described in detail above with reference to the drawings. However, the specific structure is not limited to this embodiment, and there are design changes and the like within the scope not departing from the gist of the present invention. Also included in the present invention. For example, in the above-described embodiment, the specific character string to be detected has three characters ("
However, the number of specific character strings to be detected can be set arbitrarily. For example, character data consisting of 6 characters (for example, "A") can be set.
The detection accuracy can be further improved by detecting BCDEF "). However, it is necessary to increase the number of shift register stages and the number of comparators corresponding to the character string to be detected. In the above-described embodiment, the case of using the 8-bit parallel input / output shift register has been described, but if higher speed is required, a 16-bit input / output shift register may be used.

[0018]

As described above, the character string reception detection circuit of the present invention reduces the processing load on the microprocessor because the microprocessor performs the same processing as the algorithm for character string comparison by hardware. be able to. Therefore, it is possible to easily cope with high-speed data communication with a simple configuration. Further, since the processing load on the microprocessor is reduced, other processing can be added, so that high functionality can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a character string reception detection circuit according to an embodiment of the present invention.

[Explanation of symbols]

 1, 6 to 8 Data input terminal 2, 9 to 11 Write signal input terminal 3 to 5, 12 to 14 Shift register 15 to 17 Comparator 18 AND gate 19 Output terminal

Claims (1)

[Claims] 1. A plurality of stages of shift means for sequentially shifting and outputting received communication data transferred on a line, and a specific character string to be detected, which is provided corresponding to the number of stages of the shift means. The character data and the output data of each stage of the shift means are respectively compared, and a plurality of comparing means that outputs a match signal when they match, based on the match signals respectively output from these comparing means, A character string reception detection circuit comprising: a detection unit that outputs a detection signal indicating that the specific character string has been detected.