JPH0619782A - Memory control circuit - Google Patents

Abstract

PURPOSE:To reduce overhead at the time of continuous access to each memory bank. CONSTITUTION:When an access mode to each memory bank is set, a memory address control circuit IT controls address setting to plural memory banks to wich address bit lines excepting for both of the lowest-order bit lines of the memory address of each banks are shared-connected and control circuits 12 and 14 control the transfer of writing data to each memory band or reading data from it through buffers 21 and 23 in accordance with an asserted column address strobe signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for performing data processing via a memory having a bank formed by devices connected via a system bus, and particularly to a memory for controlling access to the memory made up of banks. It relates to a control circuit.

[0002]

2. Description of the Related Art Conventionally, in a device of this type, when a plurality of memory chips are formed into banks to perform memory access,
As represented by the 2-way memory bank interleave control, each memory bank is alternately accessed.

FIG. 8 is a block diagram for explaining the structure of a conventional memory control circuit, and the structure and operation will be described with reference to FIGS. 9 to 10.

In the figure, the DR is calculated from the cycle start signal / TS (/ indicates active low) from the system bus 1, the response signal / ACK and other controller signals 6 and information of the address bus 4 necessary for memory bank designation.
The state controller 7 generates a signal for controlling the entire AM controller. The address / data bus 2 is divided into the address bus 4 and the data bus 5 by the multiplexer 3 by the control signal 301 from the state controller 7, and stored in the address latch 16 by the address latch signal 302. When this address is a memory address, the control signal 303 of the row address strobe signal / RAS10 and the write enable signal (/ WE) 11, the column address strobe signal of A bank / CAS, the column address strobe signal group / CAS-Ax control Signal 305, MA-Ax which is the memory address of A bank
Control signal 306, M which is the memory address of B bank
The memory is accessed by the control signal 307 of A-Bx, the control signal 308 of DT-Ax which is the memory data of the A bank, and the control signal 309 of DT-Bx which is the memory data of the A bank.

First, from the latched address 310 to A
The bank address (MA-Ax) control circuit 311 outputs the A bank row address to the address line 312, and the B bank address (MA-Bx) control circuit 313 outputs the B bank row address to the address line 314 at the same time. One clock after that, the row address strobe signal / RAS10 is asserted by the control circuit 9 for / RAS and / CAS, and then half a clock later, the address (MA-A
x) The control circuit 311 outputs the column address of the memory of bank A to the address line 312, and the address (M
The A-Bx) control circuit 313 outputs the column address of the memory of the B bank to the address line 314, and in the case of write access, the write enable signal (/ W
E) 11 is asserted.

Up to this point, the control signals for bank A and the control signals for bank B operate at the same timing. If the memory access address is from bank A,
The control circuit 14 for the column address strobe signal group / CAS-Bx remains the same, and one clock after the memory address is changed to the column address, the control circuit 12 for the column address strobe signal group / CAS-Ax controls the control signal line (/ CAS). -Ax) 13 is asserted. At this time,
Only the control signal line (/ CAS-Ax) 13 corresponding to the byte corresponding to the access request is asserted during the single transfer, and all four control signal lines (/ CAS-Ax) 13 during the burst transfer (/
CAS-Ax) 13 is asserted (when accessing from bank B, control signal line (/ CAS-Bx) 1
5 is asserted).

At the time of burst transfer, the control signal line (/ CAS-Bx) 15 is controlled by the control circuit 14 of the column address strobe signal group / CAS-Bx.
S-Ax) 13 is asserted one clock later. In both the A bank and the B bank, the column address strobe signal group / CASx is negated 1.5 clocks after the assertion, and during burst transfer, the column address change of the memory address of each bank / column address strobe signal group / This is performed at the same time as the negation of CASx, and after half a clock, the column address strobe signal group / CASx is asserted. That is, the width of the assert timing of the column address strobe signal group / CASx is 2 clocks, and the A bank and the B bank are asserted with a 1 clock shift, so that they are alternately asserted. The above operation is repeated until the burst transfer is completed, and when the access address to the memory is the access from the B bank, the control signal line (/ CAS-Bx) 15 is accessed first, and the same access is performed.

The above is the operation timing of the control signal and the memory address during the memory access. Next, the data and the response signal / AC during the memory read and the memory write.
The control and timing of K will be described.

First, during memory write, the system bus 1
The data bus 5 from the multiplexer / selector 25 is switched to the data bus 315 of the A bank of the first access by the control signal 308, and the data bus buffer (DT-
Ax buffer) 317 and outputs to the memory data bus 20 of the A bank. At this time, system bus 1
The response signal / ACK is asserted on the bus, and in the case of single transfer the response signal / ACK is negated at the next clock and the system bus is released. The data is switched to the bank data, is switched to the data bus 316 of the B bank by the control signal line 309 like the A bank, is latched in the data bus buffer (DT-Bx buffer) 318, and is output to the memory data bus 22 of the B bank. It Furthermore, after one clock, the data bus 5 from the system
Is switched to data for A bank, and thereafter, the same control is performed until the end of burst transfer. At this time, when the data buffer has one word in each bank, the assertion of the control signal line (/ CAS-Bx) 15 of the B bank is delayed by one clock from the assertion of the control signal line (/ CAS-Ax) 13 of the A bank. Therefore, one weight will be included. If the memory access address is from bank B,
The data for bank B is first latched, and the same control as that for bank A is performed.

Next, at the time of memory read, the memory data bus 20 from the A bank of the first access is controlled by the control signal 30.
8 and 301 to the system bus 1, and the system bus 1 has the control signal line (/ CAS-Ax) 1 of the A bank.
The response signal / ACK is asserted so that the data is determined at the negate timing of 3. In the burst transfer, one clock later, the multiplexer / selector 25 is switched to the B bank data by the control signal 311 and is output to the system bus 1, and the above operation is repeated until the burst transfer is completed. When the access address to the memory is the access from the B bank, the data in the B bank is first selected and the same control as in the A bank is performed. Hereinafter, the memory write operation will be described with reference to the timing chart shown in FIG. 9, and the memory read operation will be described with reference to the timing chart shown in FIG.

In FIG. 9, 401 is a system clock (CLK), 402 is a cycle start signal (TS),
Reference numeral 403 is a read / write signal (R / W), 404 is a response signal (/ ACK), and 405 is a system address / data bus (ADx). The signals 401 to 405 are signals on the system bus 1.

406 is a row address strobe signal / R
AS and 407 are memory write enable signals (/ W
E) and 408 are memory addresses MA- of the A bank.
Ax and 409 are column address strobe signals of A bank / CAS-Ax, and 410 is memory data DT of A bank.
-Ax and 411 are memory addresses MA-B of B bank
x and 412 are column address strobe signals of B bank /
CAS-Bx, 413 are memory data DT- of B bank
Bx is shown.

The system address bus 414 is latched at the rising timing of the system clock 401 when the cycle start signal 402 is asserted, and the row address 415 and column addresses 416 and 417 of the A bank and the row address of the B bank are latched from this address. 41
8 and column addresses 419 and 420. At this time, when the read / write signal 403 is written, the write enable signal (/ WE) 407 is asserted.
System data bus 421 and system data bus 422
To the A bank memory data (DT-AX) 423 and the system data bus 424, and the system data bus 425 and the system data bus 426 to the B bank memory data (DT).
-Bx) 427 and B bank memory data (DT-Bx)
It is output to 428.

Next, as shown in FIG. 10, the memory read timing is the response signal (/ ACK) 4 of the system bus 1.
04, the read / write signal 403, the memory write enable signal 407, and the operation timings other than the data bus are the same as those in the case of the memory write.

If the read / write signal 403 is read at the rise of the system clock 401 when the cycle start signal 401 is asserted, the memory write enable signal 407 to the memory becomes disable and the data 501, 502 from the A bank. To the system data buses 503 and 504, the data 50 from the B bank
5, 506 and system data buses 507 and 508 are output onto the system address / data bus (ADx) 405, respectively, and the response signal 404 of the system bus is fetched at the assert timing.

[0016]

However, in the above-mentioned conventional example, the memory control circuit for controlling access to a plurality of memory banks has the following method (interleave control) for accessing each memory bank at different timings as described above. There were problems shown in (1) to (4).

(1) The access end time of the last accessed memory bank becomes the memory access cycle time, and as a result, the memory access time becomes slow.

(2) It is necessary to change the access timing to each memory bank depending on the memory bank to be accessed first, which complicates the control circuit. Further, in the case of a circuit configuration in which the access timing is not changed, the limited specifications are such that only one bank accesses.

(3) When the number of memory banks is increased due to the change of the system configuration, it is necessary to change the access timing, so that the system expansion cannot be easily accommodated.

(4) Since the access timing of each memory bank is different, a memory address for each memory bank is required and a large address bit width is required, which complicates the memory circuit and increases the circuit cost.

The present invention has been made in order to solve the above-mentioned problems. By controlling the assert timing of the column address of each memory bank based on the access mode to each memory bank, each memory bank is controlled. It is an object of the present invention to obtain a memory control circuit that can reduce the overhead during continuous access of.

[0022]

A memory control circuit according to the present invention includes a plurality of memory banks to which address bit lines other than both least significant bit lines of a memory address of each bank are connected in common, and to each memory bank. Address setting control means for controlling the same or individual memory address setting for each memory bank based on the access mode;
Timing control means for controlling the assert timing of the column address based on the address set by the address setting control means, a data buffer for storing write data to each memory bank or read data from each memory bank, and timing control means. And a transfer control means for controlling transfer of write data to each memory bank or read data from each memory bank based on the column address asserted by.

[0023]

According to the present invention, when the access mode to each memory bank is set, the address setting control means causes the plurality of memories in which the address bit lines except the least significant bit lines of the memory address of each bank are connected in common. By controlling the address setting to the bank, the timing control means controls the transfer of write data to each memory bank or read data from each memory bank via the data buffer in accordance with the asserted column address strobe signal. , It is possible to reduce the overhead at the time of continuous access to each memory bank.

[0024]

1 is a system configuration diagram showing an example of an information processing apparatus having a memory control circuit showing an embodiment of the present invention.

In the figure, 201 is a CPU that controls the entire apparatus, and 202 is a memory control circuit (Memory) according to the present invention.
Controller) controls memory access to the memory banks 203 and 204. Programs executed by the CPU 201 are stored in the memory banks 203 and 204, and also function as a work area of the CPU 201. Two
05 is a direct memory access controller (DMA
C), the memory bank 203 without the CPU 201,
Data is transferred between the I / O device 204 and the I / O device. 20
6 is LA such as Ethernet (registered trademark of Xerox Co., Ltd.)
N (local area network) interface (LAN-i / f), 207 ROM, SRAM, RS
Input / output devices (I / O) including 232C, 20
8 is a hard disk, 209 is a floppy disk, 2
10 is a disk interface (Disk-i /
f), hard disk 208, floppy disk 20
9 is a disk interface for access, 211 is a printer, 212 is a printer interface (Print
ter-i / f), 213 is a keyboard or mouse interface (Key-i / f), 214 is a keyboard,
A mouse 215 is a pointing device.
Is a local area network such as Ethernet, 21
7 is an image display such as a CRT, 218 is the image display 2
17 interfaces (Video-i / f).

The operation of each unit will be described below.

When the CPU 201 is powered on, a startup process such as a system check is performed according to the programs in the ROM of the input / output devices 207, and then the programs such as the OS stored in the hard disk 208 are executed. Bring it to main memory. The application program operates according to an instruction from the user's keyboard 214 or mouse 215. Memory (ABank Memor
y) 203, memory (BBank Memory) 20
4 are accessed from the memory control circuit 202 at the same timing.

FIG. 2 shows the memory control circuit 20 shown in FIG.
2 is a block diagram illustrating a detailed configuration of FIG. 2, and the same components as those in FIG. 1 are denoted by the same reference numerals.

In the figure, 1 is a system bus, 2 is a system address / data bus, 3 is a multiplexer for separating address and data, 4 is a system address bus,
Reference numeral 5 is a system data bus, 6 is a clock and control signal bus, 7 is a state controller for controlling the entire memory control circuit, 8 is a control signal from the state controller 7, and 9 is a row address strobe signal (/ RAS).
A signal notation / indicates active low) 10 and a control circuit for controlling generation of a write enable signal (/ WE) 11,
Reference numeral 12 is a control circuit for outputting a column address strobe signal group (/ CAS-Ax) 13 (-A is a van tip, x is a plurality of signals) to the memory 203 (A bank), and 14 is the memory. A control circuit for outputting a column address strobe signal group / CAS-Bx15 (-B indicates a van tip and x indicates a plurality of signals) to 204 (B bank), 16 is an address latch, and an address of system address 2 Latch. Reference numeral 17 denotes a memory address control circuit, which is a memory address (MAx) control line 18, 19, 20
Is output to the corresponding memories 203 and 204. The memory address (MAx) control line 19 is connected to the least significant bit MAA0 of the address of the memory 203 in the A bank,
The memory address (MAx) control line 20 is connected to the least significant bit MAB0 of the address of the memory 204 of the B bank.

Reference numeral 21 is a buffer (DT-AxB), which holds the contents of the data line DT-Ax22 of the memory 203 of the A bank. A buffer (DT-BxB) 23 holds the content of the data line DT-Bx 24 of the memory 204 of the B bank. 25 is a multiplexer for the system data bus 5, and a buffer (data bus buffer) 21,
A multiplexer / function having a function as a selector of 23 /
It is a selector.

In the memory control circuit thus configured, the memory 203 of each A bank and the memory 2 of the B bank
When the access mode to 04 is set, the memory address control circuit 17 controls the address setting to a plurality of memory banks to which the address bit lines except the least significant bit lines of the memory address of each bank are shared and connected. Sequential access to each memory bank for controlling transfer of write data to or read data from each memory bank via the buffers 21 and 23 in response to the asserted column address strobe signal by the control means 12 and 14. It is possible to reduce the overhead in time.

FIG. 3 shows the memory control circuit 20 shown in FIG.
9 is a block diagram illustrating a detailed configuration of a main part of FIG. 2, and the same components as those in FIG. 8 are denoted by the same reference numerals.

The interleave control operation of two banks in the memory control circuit according to the present invention will be described below with reference to the timing charts shown in FIGS. It should be noted that the difference from the memory access method shown in FIG. 8 is that during burst transfer, column address strobe signal group / CAS-Ax13 and column address strobe signal group / CAS-Bx15 (column address strobe signal / CASx) are simultaneously applied to both banks. During the odd word transfer, only the column address strobe signal / CASx of the bank corresponding to the address of the last word is asserted. Also, the memory address is common to both banks,
The least significant bit of the memory address of Bank A (MAA0)
The memory address control line 19 and the memory address control line 20 that becomes the least significant bit (MAB0) of the memory address of the B bank are separately configured.
The basic operation of memory access in FIG. 3 will be described below.

First, from the address 310 latched by the memory address control signal 601 from the state controller 7, the memory address control circuit 17 starts A, B.
In both banks, the row address of the memory is the memory address (M
Ax) Output on control lines 18-20. One clock later, the control circuit 9 causes the row address strobe signal 10
Is asserted, and half a clock later, the memory address control circuit 17 outputs the column addresses of the memories of both banks to the memory address (MAX) control lines 18 to 20, and the write enable signal (/
WE) 11 is asserted.

At the time of single transfer, the timing is the same as the conventional timing, but at the time of burst transfer, the conventional A bank and B are used.
Although the column address strobe signals / CASx of the banks are alternately accessed, the column address strobe signals / CASx of both banks are simultaneously accessed in the present invention. That is, the column address strobe signal / CASx of both banks is accessed at the assert timing of the column address strobe signal / CASx of the bank previously accessed by the conventional method.
CASx is asserted, and in the case of odd transfer, only the column address strobe signal / CASx of the bank corresponding to the address of the last word is asserted. Further, the same signal is output to the memory address control lines 19 and 20 which become the least significant bit (MAA0) of the memory addresses of both banks when accessing from bank A in burst transfer, but the same signal is output from bank B in burst transfer. At the time of access, a signal corresponding to the access address is output from the memory address control line 20 which is the least significant bit (MAB0) of the memory address of the B bank, and the memory address control line 19 which is the least significant bit MAA0 of the A bank is the B bank. A signal obtained by inverting the memory address control line 20 which is the least significant bit MAB0 is output.

When transferring three or more words, the memory address control line 19 for the least significant bit MAA0 of the A bank and the memory address control line 20 for the least significant bit MAB0 of the B bank at the negate timing of the column address strobe signal / CASx. Invert. As a result, even if the burst transfer from the B bank address boundary is 4
Wrap-round access of words will be possible.

The above is the operation timing of the control signal and memory address at the time of memory access. Next, the control and timing of data at the time of memory read and memory write will be described. [Example of data control during memory write] First, during memory write, a response signal / AC is sent to the system bus with no wait.
K is asserted, the data signal 5 from the system bus 1 is switched by the multiplexer / selector 25 to the data bus 315 of A bank of the first access by the control signal 308, and latched in the data bus buffer (DT-Ax) 21. It is output to the data line (DT-Ax) 22 of the bank. For single transfer, the response signal /
ACK is negated and the system bus is released,
At the time of burst transfer, the data bus 5 from the system is switched to data for the B bank after one clock, and like the A bank, the data bus 316 of the B bank is controlled by the control signal 309.
Data bus buffer (DT-Bx) 23
And is output to the data line DT-Bx24 of the B bank. Furthermore, after one clock, the system bus 1
The data bus 5 is switched to the data for the A bank, and thereafter, the same control is performed until the end of the burst transfer. At this time, when the data buffer has one word in each bank, 1 wait is entered in the conventional interleave control, but in the case of the present invention, it operates in no wait.

Specifically, the memory write access cycle is executed according to the timing chart shown in FIG. The same parts as those in FIG. 9 are designated by the same reference numerals.

In FIG. 4, reference numeral 701 indicates the memory address MAx of both banks, and the cycle start signal (TS).
System clock when 402 is asserted (CL
K) The system address bus 414 is latched at the rising timing of 401, and from this address, the row address 702 and the column address 703 of both banks, the least significant bit MAA0 of the memory address of the A bank, the address 7
Converted to 04. At this time, when the read / write signal (R / W) 403 is written, the write enable signal (/ WE) 407 is asserted. Addresses 705 and 70 of the system address / data bus (ADx) 405
6 is data 707 and 708 of the memory data DT-Ax 410 of the A bank, and addresses 709 and 710 of the system address / data bus (ADx) 405 are data 711 and 7 of the memory data DT-Bx 413 of the B bank.
It is output as 12. [Data Control Example During Memory Read] During memory read, the data on the data line DT-Ax22 from the A bank and the data on the data line DT-Bx24 from the B bank are transferred to the data bus buffer (control signal 308, 309). D
T-Ax) 21, data bus buffer (DT-Bx) 2
3 is latched at the negation timing of the column address strobe signal / CASx409, the data of the bank corresponding to the first access address is selected by the multiplexer / selector 25, passes through the data bus 5, and is output to the system bus 1 by the control signal 301. Column address strobe signal / CASx40 on the system bus 1.
The response signal (/ ACK) 409 is asserted so that the data is determined at the negation timing of 9. At the burst transfer, one clock later, the multiplexer / selector 25 outputs the data of bank B to the system bus 1 by the control signal 309, and the above operation is repeated until the end of the burst transfer. When the access address to the memory is the access from the B bank, the data for the B bank is first latched, and the control is performed as in the case of the A bank.

Specifically, the memory write access cycle is executed according to the timing chart shown in FIG. The same parts as those in FIG. 10 are designated by the same reference numerals.

Response signal (/ ACK) 4 of system bus 1
04, read / write signal (R / W) 403, memory write enable signal 407, operation timings other than the data bus are the same as in the case of memory write.

When the system clock (CLK) 401 rises when the cycle start signal (TS) 402 is asserted, and the read / write signal (R / W) 40
When 3 is a read, the memory write enable signal (/ WE) 407 to the memory is disabled and the data 801 and 802 of the memory data DT-Ax410 of the A bank.
Is the data 803 of the system data bus system address / data bus (ADx) 405 and the data 80 of the memory data DT-Ax 413 from the bank.
5, 806 are output as data 807 and 808 of the system data bus system address / data bus (ADx) 405, and the response signal (/ ACK) 4 of the system bus 1 is output.
It is taken in at the timing of 04 assertion.

FIG. 6 is a flow chart showing an example of a read access processing procedure in the memory control circuit according to the present invention. In addition, (1) to (30) show each step.

First, waiting for the cycle start signal 402 to be asserted (1), the cycle start signal 40 is
When 2 is asserted, it waits for the system address bus to be latched (2), sets the counter clk of the system clock 1 to "0", and outputs the memory row address to both banks (3). Next, the system clock 1 waits for one clock to elapse (4), and the row address strobe signal (/ RASx) 10 is asserted (5).
, After this, half a clock of the system clock 1 (6),
It is judged whether it is a read access (7), and if YES, the write enable signal (/ WE) 11 is asserted (8),
The process proceeds to step (9) and thereafter. If NO, it is determined whether or not the bank destination is A (9). If YES, the memory address (MA
x) is a column address, the least significant bit MAA0 of the memory address of the A bank and the least significant bit MAB0 of the memory address of the B bank are the same (11), and if NO, the least significant bit MAA0 of the memory address of the A bank is determined. The least significant bit MAB0 of the memory address of bank B is inverted and output (10). Then, one clock after the system clock 1 (12), it is judged whether or not it is in the burst mode (13), and N
If it is O, the control signal line (/ CAS-Ax) 13 for bytes corresponding to the access request is asserted (14), and if YES, all four control signal lines (/ CAS-Ax) 13 are asserted (15). .

Then, it is judged whether it is a single transfer (1
6) If YES, determine whether the transfer destination is bank A (1
7) If YES, the column address strobe signal (CAS-Ax) 409 of the A bank is asserted (18), and half a clock of the system clock 1 (20) after this, the column address strobe signal (CAS-Ax) 409 is sent. Negated (22), row address strobe signal (/ RASx) 1
0, negate write enable signal (/ WE) 11
(24), the process ends.

On the other hand, if the determination in step (17) is NO, the column address strobe signal (CAS-Bx) 4
12 is asserted (19), and half a clock of the system clock 1 after this (21), the column address strobe signal (C
The AS-Bx) 412 is negated (23), the write enable signal (/ WE) 11 is negated (24), and the process ends.

On the other hand, if the judgment in step (16) is NO, the step is the column address strobe signal (CAS-A).
x) 409, column address strobe signal (CAS-
Bx) 412 is asserted at the same time (25), half a clock after the system clock 1 (26), and the column address strobe signal (CAS-Ax) 409 and the column address strobe signal (CAS-Bx) 412 are simultaneously negated (27). ,
It is determined whether the word is the last word (28). If YES, the row address strobe signal (/ RASx) 10 and the write enable signal (/ WE) 11 are negated (24), and the processing is ended.

On the other hand, if the decision in step (28) is NO, the least significant bit MAA0 of the memory address of bank A is MAA0.
And the least significant bit MAB0 of the memory address of the B bank is inverted (29), half clock of the system clock 1 is passed (30), and the process returns to the step (15).

FIG. 7 is a flow chart showing an example of a write access processing procedure in the memory control circuit according to the present invention. In addition, (1) to (28) indicate each step.

First, waiting for the cycle start signal 402 to be asserted (1), the cycle start signal 40 is
When 2 is asserted, it waits for the system address bus to be latched (2), sets the counter clk of the system clock 1 to "0" (3), and determines whether the access mode is the write mode (4), If YES, the response signal (/ A
CK) 404 is asserted (5) and it is determined whether the bank destination is A (6). If YES, the memory data (DT-Ax) 410 of the A bank is latched (7), and if NO, the B bank Latch the memory data (DT-Bx) 413
(8), 1 clock after system clock 1 from this (9)
, It is judged whether it is the last word (10), if NO, return to step (5), and if YES, response signal (/ ACK)
404 is negated (11), and the process ends.

On the other hand, if the judgment in step (4) is NO,
Three clocks after the system clock 1 (12), the response signal (/
ACK) is asserted (13), it is judged whether the bank destination is A (14), and if YES, the multiplexer / selector 23
Switches the data bus of the access destination to A bank (15),
At the next system clock 1, (16), data bus buffer (DT-Ax) 21, data bus buffer (DT-B)
x) 23 is latched (17), it is judged whether it is a single transfer (18), if NO, the process returns to step (11), and if YES, the multiplexer / selector 23 switches the data bus of the access destination to the B bank ( 19), at the next system clock 1 (20), it is judged whether or not it is the last word (21). If NO, return to step (13), and if YES, return to step (11) to return the response signal (/ ACK ) Is negated (11), and the process ends.

On the other hand, if the determination in step (14) is NO, the multiplexer / selector 23 switches the access destination data bus to the B bank (22), and at the next system clock 1 (23) the data bus buffer ( DT-Ax) 21,
Latched in the data bus buffer (DT-Bx) 23 (2
4) It is judged whether it is a single transfer (25), if NO, the process returns to step (11), and if YES, the multiplexer / selector 23 switches the data bus of the access destination to the A bank (26), and the next system clock. In 1 (27), it is judged whether or not it is the last word (28). If NO, the process returns to step (13), and if YES, the process returns to step (11) and the response signal (/ A
CK) 404 is negated (11), and the process ends.

As a result, the memory access cycle becomes shorter when reading and transferring even-numbered words than in the conventional interleaving.
The precharge of S is completed early, and the overhead is reduced during continuous access.

Further, at the time of writing, when the data buffer has one word in both banks, it can operate without a wait, and the overhead due to the above reason is reduced.

Furthermore, since access is made at the same timing in both banks, memory addresses can be reduced and miniaturization can be achieved.

Further, since the least significant bit of the memory address is set separately for each bank, wrap round access of 4 words becomes possible during burst transfer.

In the above embodiment, the case where there are two memory banks has been described. However, since both banks are accessed simultaneously, the same control can be performed even if the number of memory banks is increased.

Further, in the above embodiment, the memory addresses of both banks are set so that only the least significant bit is separate so that a 4-word wrap round burst transfer can be performed. However, by separating the least significant 2 bits, an 8-word wrap round is realized. Burst transfer is possible. Similarly, if the number of bits is increased by 1 bit, it is possible to easily cope with 16, 32, 64, ... Word wrap rounds.

Further, in the above embodiment, the memory addresses of both banks are set so that only the least significant bit is separated so that 4-word lap land burst transfer can be performed. However, instead of using the same memory address for both banks, By setting the number to "4", 4-word lapland burst transfer becomes possible. Similarly, the memory banks can be used for 8, 16, 32 ... Word wrap round.

[0060]

As described above, according to the present invention, when the access mode to each memory bank is set, the address setting control means shares the address bit lines except the least significant bit lines of the memory address of each bank. The write data to each memory bank or the read data from each memory bank is controlled by the timing control means in accordance with the asserted column address strobe signal for controlling the address setting to the connected memory banks. Since it is configured to control transfer,
Since memory access becomes shorter when transferring even-numbered words as compared with conventional interleaving, precharging of the row address strobe signal ends earlier, and overhead during continuous access to each memory bank can be reduced.

Further, at the time of writing, when the data buffer has one word in both banks, the operation can be performed without a wait, and the overhead at the time of continuous access to each memory bank can be reduced.

Further, since both memory banks are accessed at the same timing, the memory address can be reduced and the memory control circuit can be downsized.

Further, since the least significant bits of both memory banks are separately provided, a number of excellent effects such as 4-word wrap round access becomes possible during burst transfer.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an example of an information processing apparatus having a memory control circuit showing an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a detailed configuration of a memory control circuit shown in FIG.

FIG. 3 is a block diagram illustrating a detailed configuration of a main part of the memory control circuit shown in FIG.

FIG. 4 is a timing chart illustrating a memory write operation in the memory control circuit according to the present invention.

FIG. 5 is a timing chart illustrating a memory read operation in the memory control circuit according to the present invention.

FIG. 6 is a flowchart showing an example of a read access processing procedure in the memory control circuit according to the present invention.

FIG. 7 is a flowchart showing an example of a write access processing procedure in the memory control circuit according to the present invention.

FIG. 8 is a block diagram illustrating a configuration of a conventional memory control circuit.

FIG. 9 is a timing chart explaining a memory write operation in a conventional memory control circuit.

FIG. 10 is a timing chart explaining a memory read operation in a conventional memory control circuit.

[Explanation of symbols]

 1 System Bus 2 System Address / Data Bus 5 System Data Bus 7 State Controller 9 Control Circuit 12 Control Circuit 14 Control Circuit 16 Address Latch 17 Memory Address Control Circuit 21 Buffer 22 Buffer

Claims (1)

[Claims] 1. A plurality of memory banks to which address bit lines other than both least significant bit lines of a memory address of each bank are connected in common, and the same or individual memory banks for each memory bank based on an access mode to each memory bank. Address setting control means for controlling the memory address setting, timing control means for controlling the assert timing of the column address based on the address set by the address setting control means, write data to each memory bank or from each memory bank A data buffer for storing read data; and a transfer control means for controlling transfer of write data to each memory bank or read data from each memory bank based on a column address asserted by the timing control means. Characteristic memory Control circuit.