JPH0619998A - Critical pass checking method - Google Patents

Abstract

(57) [Abstract] [Purpose] In the operation simulation of the semiconductor integrated circuit design, the critical path is checked without calculating the delay time of the path between cells synchronized with the clock. [Configuration] A setup time / hold time for a clock of a cell in a circuit operating in synchronization with a clock is calculated from the result of logic simulation (step 5), and it is determined whether the calculated result is within an allowable value.
This is performed for all the cells (cells in the list) in the circuit that operate in synchronization with the clock. [Effect] A program can be created with a relatively simple algorithm.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a critical path check method which is one of operation simulation methods in the design of semiconductor integrated circuits.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have been rapidly increasing in size and miniaturization. Along with this, accurate operation confirmation at the circuit design stage has become indispensable for early development of semiconductor integrated circuits. A critical path check is one of the methods for confirming this operation.

A conventional critical path check method will be described below. FIG. 2 shows a flowchart of a conventional critical path check method. Figure 2
In, 11 to 17 are respective steps. In this conventional critical path check method, first, in step 11, a cell (cell
Search (a). Then in step 12, another cell (cell cell) connected to the output of cell (a)
(refer to (b)) and search for cells in step 13.
Determine if (b) is in sync with the clock. If cell (b) is not synchronized, the delay time of that cell is stored (step 14). Then, again, the cell (c) connected to the output of the cell (b) is searched, and if the cell (c) is not synchronized with the clock, the cell (c) is searched.
The delay time of (c) is added to the accumulated delay time so far (steps 12 to 14). The processes of steps 12 to 14 are repeated until a cell synchronized with the clock is found.

When a cell synchronized with the clock is found in step 13, it is determined in step 15 whether the accumulated delay time calculated in step 14 is within the allowable value. If the accumulated delay time exceeds the allowable value, the accumulated delay time is output and displayed in step 16. In step 17, it is determined whether or not there is another path to be subjected to the critical path check in the circuit, and the processing of steps 11 to 17 is repeated until the execution of the processing for all the paths in the circuit is completed.

[0005]

A cell used at the stage of circuit design may have a plurality of output pins.
Therefore, in the above-described conventional configuration, many paths may be divided while tracing the circuit from the cell synchronized with the clock to the cell synchronized with the next clock. In order to check the path, you have to develop a program with a fairly complex algorithm.

The present invention solves the above-mentioned conventional problems, and provides a critical path check method capable of checking a critical path without checking a delay time of a path between cells synchronized with a clock. The purpose is to provide.

[0007]

To achieve this object, the critical path checking method of the present invention comprises a first process for creating a list of cells in a circuit which operates in synchronization with a clock, and A second process of calculating a setup time / hold time for a cell clock from a result of logic simulation, a third process of determining whether a calculation result of the second process is within an allowable value, and a third process of the third process. The fourth process for outputting and displaying the calculation result when the determination result of the process is error.

[0008]

According to the structure of the present invention, the setup time / hold time for the clock of the cell in the circuit operating in synchronization with the clock is calculated from the result of the logic simulation, and whether the calculated result is within the allowable value or not. judge. By doing this for all the cells in the circuit (cells in the list) that operate in synchronization with the clock,
The critical path can be checked without checking the path between the cells synchronized with the clock, and the program can be created by a relatively simple algorithm.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart of a critical path check method according to an embodiment of the present invention. In FIG. 1, 1 to 8 are steps. In this critical path checking method, first, logic simulation is performed in step 1, and the execution result is read in the form of text data (step 2). Also, in step 3, a list of cells synchronized with the clock in the circuit is created. This list can be easily created by searching for cells connected to the same clock.

Next, one cell in the list created in step 3 is selected, and the selected cell (hereinafter, "selected cell") is selected.
Is called in the circuit (step 4). Then, in step 5, the setup time and hold time of the selected cell are calculated based on the logic simulation data read in step 2. The setup time is calculated according to how much data is input before the clock, and the hold time is calculated according to how much data is held after the clock is input.

Then, in step 6, the calculation result of the setup time and the hold time is judged, and if the calculation result does not satisfy the allowable value considered by the designer, the unique name of the selected cell and the calculation result are obtained. Is output and displayed (step 7). And in step 8,
If it is determined that all the cells in the list have been processed, and if it is determined that the processing has not been completed for all cells in the list, steps 4 to 7 are repeated,
Check all cells in the list.

In step 6, if the setup time and hold time satisfy the allowable values, the F.S. F. It can be determined that the (flip-flop) operates normally. Thus, according to this embodiment,
The critical path can be checked without checking the delay time of the path between the cells synchronized with the clock, and the program can be created by a relatively simple algorithm.

[0013]

According to the critical path check method of the present invention, the setup time / hold time for the clock of the cell in the circuit operating in synchronization with the clock is calculated from the result of the logic simulation, and the calculated result is within the allowable value. Determine if there is. By doing this for all cells in the circuit that operate in synchronization with the clock (cells in the list), it is possible to check the critical path without checking the path between cells that are synchronized with the clock. , A program can be created with a relatively simple algorithm.

[Brief description of drawings]

FIG. 1 is a flowchart of a critical path check method according to an embodiment of the present invention.

FIG. 2 is a flowchart of a conventional critical path check method.

[Explanation of symbols]

1 Logic simulation execution step 2 Logic simulation execution result reading step 3 Cell list creation step synchronized with the clock in the circuit 4 Cell search inside the circuit step 5 Cell setup time / hold time Calculation step 6 Determination step of calculation result in step 5 Step 7 Error display of setup time / hold time 8 Step of determining whether all cells in the list have been processed

Claims (1)

[Claims] 1. A first process for creating a list of cells in a circuit that operates in synchronization with a clock, and a second process for calculating a setup time / hold time for a clock of a cell in the list from a result of logic simulation. Process, a third process for determining whether the calculation result of the second process is within an allowable value, and a fourth process for outputting and displaying the calculation result when the determination result of the third process is an error. The critical path check method including the processing of.