JPH0620040B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention includes a method for manufacturing a semiconductor device such as a semiconductor laser or FET, and particularly includes a first crystal growth step, a selective etching step, and a second vapor phase growth step. The present invention relates to a manufacturing method which is excellent in mass productivity without deterioration of crystallinity due to transformation of a semiconductor surface such as an oxide film.

(Prior Art) The prior art will be described by taking a semiconductor laser manufacturing method as an example. FIG. 3 is a cross-sectional view showing the structure of a semiconductor laser manufactured according to the prior art, and FIGS. 4 (a) to 4 (c) are process drawings showing its manufacture. (For example IEDM'83 Proceedings pp292-29
Five). A first vapor phase growth method, for example, a metal organic chemical paper deposition method (hereinafter referred to as MOCVD method) is used to form an n-type Al _0.45 Ga _0.55 on the n-type GaAs substrate 12.
As layer 13, Al _0.15 Ga _0.85 As active layer 14, P-type Al _0.45 Ga
_{A 0.55} As layer 15 and an n-type GaAs layer 16 are formed (FIG. 4 (a)). Next, perform selective etching by wet etching
A groove 17 exposing the P-type Al _0.45 Ga _0.55 As layer 15 is formed (4th
(B)), after this, a second vapor phase buried growth was performed
l _0.45 Ga _0.55 As layer 18 and P-type GaAs layer 19 are formed (see FIG. 4).
(c)) The semiconductor laser crystal shown in FIG. 3 is completed. n type G
The aAs layer 16 functions as a current confinement layer and a light absorption layer for controlling the transverse mode by the loss guide. Since this manufacturing uses the MOCVD method which is excellent in mass productivity, the mass productivity is far superior to the case where the conventional liquid phase epitaxial growth method is used at least in the crystal growth step.

(Problems to be Solved by the Invention) However, the problem in this case is the selective etching step of the groove 17. Al _x Ga _1-x As is more likely to be oxidized as x increases, and the exposed surface of Al _x Ga _{1- x} As easily forms an oxide film in the air, and the oxide film is not removed by heating. Compared with this, the GaAs surface also forms an oxide film in the air, but it is easily decomposed when heated in a reducing gas. Therefore, since the bottom surface of the groove 17 is exposed to the air, vapor phase buried growth is performed on the oxide film. A
When the x value of the l _x Ga _1-x As layer 15 is large, the electrical characteristics are deteriorated, crystal dislocations are generated in the buried layers 18 and 19, and further the buried growth itself cannot be performed.

Further, the _p- type Al _0.45 Ga _0.55 As layer 15 is usually 2000 to 5000
Since it is thin, it is difficult to control the bottom surface of the groove 17 so as not to penetrate the p-type Al _0.45 Ga _0.55 As layer 15 by wet etching. It is conceivable to use a selective etchant of GaAs and Al _x Ga _1-x As, but a normal selective etchant forms a thick oxide film on the surface of the Al _x Ga _1-x As layer.

The present invention is to provide a method of manufacturing a semiconductor device that solves this problem.

(Means for Solving the Problems) In the present invention, Al _x is provided between the first GaAs layer and the second GaAs layer.
At least a Ga _1-x As layer (x> 0.1) and
First crystal growth step of forming a multilayer structure having at least a laminated structure in which the GaAs layer is the uppermost layer on the substrate, and a groove having a depth to expose the first GaAs layer is formed in the multilayer structure. After the step of forming and the second GaAs layer and the first GaAs layer exposed at the bottom of the groove are removed by vapor phase etching with hydrogen chloride, the groove and Al _{x are} removed.
A second crystal growth step of forming a semiconductor layer on the Ga _1-x As layer is provided at least.

(Function) The GaAs layer is exposed on the crystal surface of the present invention immediately before the vapor phase etching except the groove side portion. As mentioned above, GaAs
Since the oxide layer of the layer can be easily removed by heating, it is possible to obtain a clean surface. In vapor phase etching using hydrogen chloride, GaAs and Al _x Ga _1-x As (x>
0.1) has an extremely low etching rate, so GaAs
The s layer can be selectively removed. Furthermore although the vapor phase etching with hydrogen chloride it is difficult to obtain a mirror surface of the GaAs surface to remove the GaAs layer, the exposed Al _x Ga
The specularity of the _1-x As layer (x> 0.1) is good. In this way, vapor phase etching is performed to remove the GaAs layer and perform a second vapor phase buried growth on the surface of the cleaned and mirror-finished Al _x Ga _1-x As layer to form a good quality semiconductor layer with few crystal dislocations. be able to. Further, the Al _x Ga _1-x As layer is exposed on the groove side portion, but if x <0.5, the crystallinity of the buried layer is not significantly affected.

(Example) FIG. 1 is a diagram showing an example of the present invention.

The first crystal growth is performed using, for example, the MOCVD method, and n
N-type Al _0.45 Ga _0.55 As layer 2, Al _0.15 G on the type GaAs substrate 1
a _0.85 As active layer 3, p-type Al _0.45 Ga _0.55 As layer 4, n-type GaAs
Layer (first GaAs layer) 5, n-type Al _0.2 Ga _0.8 As layer 6, n-type GaAs
A layer (second GaAs layer) 10 is formed (FIG. 1 (a)). Next, selective etching is performed to form a groove 11 having a depth such that the n-type GaAs layer 5 does not penetrate (FIG. 1 (b)). Then, vapor phase etching using hydrogen chloride is performed to remove the n-type GaAs layer 10 and the n-type GaAs layer 5 at the bottom of the groove 7 (FIG. 1 (c)). Immediately after this, vapor phase growth using the second MOCVD method was performed to form a p-type Al _0.45 Ga _0.45 As layer 8 and a p-type GaAs layer 9 (see FIG. 1).
(d)) The semiconductor laser crystal according to the present invention is completed. The conditions of vapor phase etching used in the manufacturing process of the present invention are, for example, at a temperature of 850 ° C., a net flow rate of HCl of 5 cc / min, a net flow rate of AsH _{3 of} 50 cc / min, and a flow rate of hydrogen gas of 12 as a carrier gas.
At l / min, the GaAs etch rate is about 2600Å / min. Under the same conditions, the etching rate of Al _0.2 Ga _0.8 As is GaAs
It is about 1/6 of s. Therefore, the thickness of the n-type GaAs layer 10 is 3
000Å, the thickness of the n-type GaAs layer 5 at the bottom of the groove 7 is 3000Å,
If the etching time is set to about 2 minutes, the n-type GaAs layer 10 and the n-type GaAs layer 5 at the bottom of the groove 7 are completely removed, and the mirror-finished n-type Al _0.2 Ga.
_{The 0.8} As layer 6 and the p-type Al _0.45 Ga _0.55 As layer 4 are exposed.
And its surface is very clean without any oxide film. Therefore, the buried layers 8 and 9 formed immediately after the vapor phase etching have few crystal dislocations and are of good quality.

2 (a) to (e) show F obtained by the manufacturing method according to the present invention.
An example of an ET manufacturing process is shown.

By the first MOCVD growth, a high resistance Al _0.5 Ga _0.5 As layer 21, an n-type GaAs layer 22, a high resistance Al _{0.5 is formed} on the high resistance GaAs substrate 20.
A Ga _0.5 As layer 23 and a high resistance GaAs layer 24 are formed (Fig. 2).
(a)). Next, by selective etching, grooves 25 and 26 which do not penetrate the n-type GaAs layer are formed (FIG. 2 (b)). At this time, a SiO ₂ mask is used as the etching mask, and the SiO ₂ mask 27 is left in the portions sandwiched by the grooves 25 and 26 even after the selective etching. After that, vapor-phase etching is performed in a MOCVD reactor to obtain a high-resistivity GaAs layer 24 in a portion without a SiO ₂ mask.
And the n-type GaAs layer 22 at the bottoms of the trenches 25 and 26 are removed (FIG. 2 (c)), and n-type Al _0.3
A Ga _0.7 As layer 28 and an n-type GaAs layer are sequentially formed (see FIG. 2).
(d)). Finally gate electrode 30, drain electrode 31, lease electrode
32 is formed to complete the FET according to the present invention.
(e)). The FET according to the present invention is suitable for integration because the current injection region is limited to the trenches 25 and 26 and the portion sandwiched between these trenches.

(Effects of the Invention) As described above, according to the present invention, a good quality crystal layer can be formed on a clean crystal surface, and a semiconductor device having excellent reliability and device characteristics can be easily obtained. . As described above, the present invention is expected to be applied not only to semiconductor lasers but also to the manufacture of FETs, integrated circuits and the like.

[Brief description of drawings]

1 (a) to (d) are process drawings showing a first embodiment of the present invention,
2 (a) to (e) are views showing a manufacturing process of the second embodiment, FIG. 3 is a sectional view showing a structure of an example of a semiconductor laser obtained by a conventional technique, and FIGS. 4 (a) to (a) c) is a diagram showing the manufacturing process. In the figure, 1,12 ... n-type GaAs substrate, 2,13 ... n-type Al _0.45 Ga _0.65 As layer, 3,14 ... Al _0.15 Ga _0.85 As active layer, 4,15 ... p-type Al _0.45 Ga _0.55 As layer, 5,10,16 …… n type GaAs layer, 6 …… n type Al _0.2 Ga _0.8 As layer, 7,11,17,25,26 …… groove, 8,18 …… p type Al _0.45 Ga _0.55 As layer, 9,19 ... p-type GaAs layer, 20 ... GaAs substrate, 21, 23 ... Al _0.5 Ga _0.5 As layer, 22 ... n-type GaAs layer, 24 ... high resistance GaAs layer, respectively. Show.

Claims (1)

[Claims] 1. An Al _x Ga _1-x As layer (x> 0.1) is provided at least between the first GaAs layer and the second GaAs layer, and the second GaAs layer is a top layer. A first crystal growth step for forming a multi-layer structure having at least a laminated structure on a substrate, forming a groove having a depth to expose the first GaAs layer in the multi-layer structure, The second GaAs layer and the first GaAs layer exposed at the bottom of the groove are removed by vapor phase etching with hydrogen chloride, and then a semiconductor layer is formed on the groove and the Al _x Ga _1-x As layer. 2. A method of manufacturing a semiconductor device, comprising at least the step 2 of growing a crystal.