JPH0620173Y2 - Reference voltage circuit having starting circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a reference voltage circuit having a starting circuit.

[Prior Art] FIG. 1 is a connection diagram showing an example of a conventional starting circuit together with a reference voltage circuit. In this figure, the portion of the J-FET Q ₁ surrounded by the broken line is the starting circuit, and the circuit composed of the transistors Q _{2 to} Q ₅ and the differential amplification circuit A ₁ is the portion that generates the bandgap reference voltage Vref. .

In this circuit, in order for the circuit composed of the transistors Q _{2 to} Q ₅ to start, the voltage at the Eref terminal is 0.5V.
It is necessary to some extent. Therefore, the J-FET Q ₁ supplies the reference generator with a voltage and a current sufficient to output 0.5 V to the Eref terminal, the circuit rises, and a predetermined reference voltage (6.4 V) is output to the Vref terminal. Sometimes you have to pinch off.

Given these conditions theoretically, pinch-off voltage VP of the J-FETs Q ₁ must be 3.8V ≦ -VP ≦ 7.6V. Further, considering variations in each resistance, VP becomes 4.7V ≦ −VP ≦ 7.2V, and the process margin is reduced. In addition, since a parasitic capacitance is generated between the source of J-FETQ ₁ and the substrate,
A pole was generated near KHz, which was a factor of oscillation.

[Purpose of Invention] The present invention has been made in view of the above problems.
The purpose thereof is to realize a start-up circuit that can increase the process margin and prevent the parasitic capacitance from affecting the circuit by adopting the current start-up type.

[Configuration of the Invention] The present invention that achieves this object is a J-FE in which a gate is connected to a common line between a power supply line and a common line.
It is characterized in that T and a constant current circuit are connected in series, and the drain current of the J-FET is caused to flow through a circuit for generating a bandgap reference voltage to activate the circuit.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a connection diagram showing an example of a circuit according to the present invention. In this circuit, parts corresponding to the parts of the circuit shown in FIG. 1 are designated by the same reference numerals. A part surrounded by a broken line is a starting circuit which is a feature of the present invention, and is composed of a series circuit of a J-FET Q ₁ whose gate is connected to a common line COM and a constant current circuit CI including transistors Q ₇ and Q _8. is, the series circuit is connected between the power supply line V _S and the common line COM. And J-
The drain current ID of the FET Q ₁ is set to the transistors Q _{2 to} Q ₅
The reference generation circuit consists of

Here, the condition of the J-FET Q _{1 that} can start the circuit is determined by the saturation current (IDSS).

That is, assuming that the circuit starts up when the voltage at the Eref terminal is V _E (V), the current IR flowing through the resistor R _{2 is given} by the equation (1).

IR = V _E / R ₂ (1) Further, when h _{FE of the} transistor Q ₃ is h _FE Q ₃ , the drain current ID is given by the formula (2).

ID = IR / h _FE Q ₃ = (V _E / R ₂ ) / h _FE Q ₃ (2) Therefore, the saturation current IDSS of the J-FET Q ₁ is IDSS ≧ (V _E / R ₂ ) / h _FE Q ₃ At that time, it will start.

FIG. 3 is a characteristic diagram showing a starting characteristic when the drain current ID of the J-FET Q ₁ is ID ≧ 1 μA in the circuit of the present invention.

As is clear from the results of this experiment, the starting voltage (voltage of the power supply line V _a ) was 9 to 10 V, although there was some variation depending on the temperature.

[Effects of the Invention] As described above, the starting circuit of the present invention has the following features.

(A) As a condition of the J-FET Q ₁ , there is no upper limit, so that the process margin becomes large and the yield can be improved.

(B) Even if there is a parasitic capacitance in the J-FET Q ₁ , since it does not affect the critical line of the circuit, a low frequency pole does not occur, and the cause of oscillation can be eliminated.

The lateral PNP transistors Q ₇ and Q ₈ forming the constant current circuit have a small parasitic capacitance, and a low frequency pole does not occur.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an example of a conventional circuit, FIG. 2 is a connection diagram showing an embodiment of a circuit of the present invention, and FIG. 3 is a diagram showing a starting characteristic. _{Q 1 ... J-FET, CI} ... constant current circuit V _S ... power supply line, COM ... common line _{Q 3, Q 4, Q 5} ... reference generator unit A ₁ ... differential increase width circuit

Claims (1)

[Scope of utility model registration request] 1. A pair of transistors Q3, Vref terminals and a common line whose bases are commonly connected and whose collectors are connected to a power supply line to take out voltage Va from one emitter and take out voltage Vref from the other emitter. A terminal connected to the voltage dividing point of the resistor connected between the two to take out the voltage Eref, a collector of which is connected to the power supply line and an emitter of which is connected to the base of the transistor Q3, and the bases of which are connected to each other. The transistors Q4 and Q5 are connected to the pressure point, the emitters are connected to the common line, and the collectors are connected to the emitters of the transistor Q2. The input terminals are connected to the collectors of the transistors Q4 and Q5 and the output terminals are connected to the base of the transistor Q2. The amplifier A1 and the power supply line And a base connected in common to the transistors Q7 and Q8. The collector of the transistor Q7 is connected to the collectors of the transistors Q4 and Q5, and the collector of the transistor Q8 is connected to the common line. A reference voltage circuit equipped with a starting circuit connected to a common line via