JPH06201780A - Integrated circuit - Google Patents

Abstract

PURPOSE:To shorten the test hour of a sequential circuit where a BIST test is practicable and to reduce hardwear overhead. CONSTITUTION:In an integrated circuit equipped with a scan flip flop which has data being an input into a flip flop when a tested circuit 10 makes ordinary motion as one of inputs into the scan flip flop and the exclusive OR of the output of the flip flop on the front stage of a scan chain, a test pattern generator 11 is connected to the input of the scan chain, and the output of the scan chain is input into a test output compressor 12 together with a source output.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to integrated circuits, and more particularly to testable integrated circuits.

[0002]

2. Description of the Related Art As the degree of integration increases, it becomes more and more difficult to test logical functions of integrated circuits. One of the methods proposed to solve this problem is the BIST method that incorporates a test function inside the chip. This BIS
Various methods have been proposed for realizing the T method, but most of them are for combinational circuits, and few have been proposed for sequential circuits. As a method for applying the BIST method to a sequential circuit, the one shown in FIG. 5 is known (Hideo Fujiwara, Logic Testing and Design for Testability (Logic Tes).
toning and Design for Testab
ility), published by MIT Press, p. 261). In the method shown in FIG. 5, the BIS is used for the sequential circuit of the scan path design.
The T method is applied.

In FIG. 5, a pseudo random pattern generator 51 for applying a test pattern to the primitive input of the circuit under test 50 and a pseudo random pattern generator 5 for applying a test pattern to the scan chain of the circuit under test 50.
2, a multi-input output compressor 53 that compresses the test output from the source output of the circuit under test 50, and a one-input output compressor 54 that compresses the output from the scan chain of the circuit under test 50. . Further, the circuit under test 50 has a scan operation mode and a normal operation mode as in a general scan-designed logic circuit.

The operation will be described with reference to FIG. First, the circuit under test 50 is set to the scan operation mode, the first test pattern generated by the pseudo random pattern generator 52 that supplies the test pattern to the scan chain is scanned in, and each flip-flop that constitutes the scan chain is scanned. Test pattern is set in the The circuit is then returned to normal operating mode and a test pattern is applied from another pseudo-random pattern generator 51 to the normal circuit input. A circuit operation is performed by this test pattern and the test pattern set in each flip-flop, and the result is taken in each flip-flop, and at the same time, the test output from the original output of the circuit under test 50 is sent to the multi-input output compressor 53. Is entered. In this state, the circuit under test 50 is set to the scan operation mode again,
The content of each flip-flop is shifted out of the scantain and sequentially input to the one-input output compressor 54.
At this time, the next test pattern generated by the pseudo random pattern generator 52 is simultaneously shifted into each flip-flop by using the scan chain. Less than,
The same operation as the first pattern is repeated, the output from the primitive output is compressed by the multi-input output compressor 53, and the contents of each flip-flop read from the scan chain are input to the one-input compressor 54 and compressed. . After all the test patterns have been applied, the contents of the multi-input output compressor 53 and the one-input output compressor 54 are compared with expected values to judge pass / fail.

[0005]

As described above, in the conventional example, the test is performed by using the outputs from the different pseudo random pattern generators for the primitive input and the scan input of the circuit under test 50, respectively. That is, the scan test is basically performed, and the input pattern is simply replaced with the pseudo random pattern. Therefore, every time one pattern is applied to the primitive input, it is necessary to set the initial value data in all scan chained flip-flops and read the data fetched by the flip-flops. Since the setting of the initial value and the reading of the fetched data can be performed at the same time, the application of clocks of the number of scan flip-flops is required in order to apply one test pattern. In general, a test using a random pattern requires more patterns than a test using an algorithmically derived pattern. Therefore, the conventional method has a problem that the test takes an enormous amount of time. Another problem is that separate test hardware is required for the original input / output and the scan input / output, and the hardware overhead is large.

An object of the present invention is to provide an integrated circuit capable of BIST test which solves the above-mentioned problems of the prior art and has a short test time and a small amount of additional hardware.

[0007]

The first invention of the present invention is as follows:
In a scan-designed integrated circuit, a test pattern generator for supplying a test pattern to a primitive input and a scan input of a circuit under test, and a test output compressor having a primitive output and a scan output of the circuit under test as inputs It is characterized by that.

According to a second aspect of the present invention, in the integrated circuit of the first aspect, the scan flip-flop has at least data obtained from a normal operation of the integrated circuit and a scan flip-flop in a preceding stage of the flip-flop. It is characterized by having an exclusive OR with an output as an input.

[0009]

The present invention will be described in detail below with reference to the drawings. 1 is a block diagram showing an integrated circuit of a first embodiment of the present invention. In FIG. 1, in this embodiment, the test pattern generator 11 is composed of a linear feedback shift register capable of generating a pseudo random pattern, and the test output compressor 12 is composed of a multi-input code analyzer. There is. The test pattern generator 11 and the test output compressor 12 operate as simple input registers and output registers during normal operation. FIG. 2 shows a specific example of the scan flip-flop in this embodiment.

In FIG. 2, the j-th scan flip-flop of the scan chain is shown, and when the control signal CMUX of the multiplexer 22 is logic "0", it is the normal operation mode, and the normal data input DINj is the D type. It is input to the flip-flop (DF / F) 20. When the control signal CMUX of the multiplexer 22 is logic "1",
In the test mode, the output of the exclusive OR gate 21 is input to the D-F / F 20. Exclusive OR gate 21
Takes as inputs the normal data input DINj and the output of the output DOUTj-1 of the previous stage F / F (not shown).

In the present embodiment, during normal operation, the test pattern generator 11 in FIG. 1 operates as a simple input register as described above, and the test output compressor 12 operates as a simple output register. In the scan flip-flop shown in FIG. 2, the control signal CMUX of the multiplexer 22 is controlled to the logic "0", and the normal DF / F
To work as. Therefore, the integrated circuit performs the desired function.

Next, at the time of testing, the reset signal φR
After initializing each scan flip-flop by activating, the clock signal CLK is input to the test pattern generator 11 to generate a pseudo random pattern. The generated test pattern is applied not only to the primitive input of the circuit under test 10 but also to the scan chain input. The circuit under test 10 performs a desired logical operation, and the result is output from the original output and input to the test output compressor 12. The circuit under test 10
Each scan flip-flop in the multiplexer 22
Control signal CMUX is controlled to logic "1", the result of the normal logic operation performed by the pattern applied to the primitive input of the circuit under test 10 and the value of each initialized flip-flop, and the scan chain The exclusive OR of the outputs of the scan flip-flops in the preceding stage is input. The exclusive OR of the result of the normal logic operation for the applied pattern and the test pattern input from the scan input is input to the first flip-flop of the scan chain, and the output of the last flip-flop of the scan chain is Test output Compressor 12 same as original output
Entered in. The same operation is repeated thereafter until a predetermined test pattern is applied. When a predetermined number of test patterns are applied, the contents of the test output compressor 12 obtained by compressing the original output of the circuit under test 10 and the scan chain output are read and compared with the expected value prepared in advance, and they match. If so, it is determined to be normal, and if they do not match, it is determined to be a failure.

As shown in this embodiment, the contents of the scan flip-flop reflect both the output of the previous flip-flop and the result of the normal logic operation of the circuit during the test. Therefore, the scan flip-flops included in the scan chain fulfill the same function as the test output compressor 12, and this output is also used as a test pattern.

A block diagram of the integrated circuit of the second embodiment of the present invention is shown in FIG. In the first embodiment, the scan chain could not be used for the original scan test application, but the first embodiment makes it possible.

In FIG. 3, the difference from the first embodiment of the present embodiment is that a multiplexer 33 is inserted between the test pattern generator 31 and the scan chain input of the circuit under test 30, and a control signal C31 is inserted. By switching between the two, the data from the scan input terminal Sin is given to the scan chain, and the scan chain output can be observed at the scan output terminal Sout. Along with this, the scan flip-flop used also has the configuration shown in FIG.

The scan flip-flop shown in FIG. 4 is provided by adding another multiplexer 41 to the scan flip-flop shown in FIG. 2 and providing a normal scan mode. That is, the control signal C41 of the multiplexer 41 is controlled to the logic "1", and the multiplexer 42
By controlling the control signal C42 of
The output OUTj-1 of the previous stage F / F can be taken into the D-F / F 40, and the normal scan mode can be realized.

The normal operation mode can be realized by setting the control signal C41 to logic "0". In the BIST mode according to this embodiment, the control signal C41 is set to logic "1" and the control signal C42 is set to logic "0". It can be realized by controlling. Therefore, the test operation described in the first embodiment can be realized in the same manner in the second embodiment. That is, in this embodiment, the scan mode test function is further added to the first embodiment. This allows BIST
After performing a high-speed test with a random pattern using the function, the scan function can be tested for a small number of undetected remaining faults using a test pattern that is algorithmically derived, providing a higher-performance test. it can.

The first and second embodiments improve the problems in the prior art by adopting the above construction. That is, according to this embodiment, the exclusive OR of the output of the preceding flip-flop and the data obtained from the normal operation of the circuit under test is input to each flip-flop that is scan-chained during the test. Therefore, the content of each flip-flop is determined by both the preceding data, that is, the test pattern and the circuit normal operation output, and effectively operates as the test output compressor. Furthermore, by using this output as a test pattern, it also has a function as a test pattern generator. As a result, it is not necessary to set test data in the scan chain every time, and it is possible to reduce the test time and the hardware overhead. In other words, in the present embodiment, the scan chain flip-flop is not allowed to have only one function, but is allowed to have two functions at the same time, thereby shortening the test time and reducing the hardware overhead at the same time. I am doing it.

[0019]

As described above, the integrated circuit of the present invention has an effect that a BIST testable integrated circuit having a small number of test patterns can be obtained with a small area overhead.

[Brief description of drawings]

FIG. 1 is a block diagram showing an integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a scan flip-flop used in the embodiment shown in FIG.

FIG. 3 is a block diagram showing an integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a scan flip-flop used in the second embodiment.

FIG. 5 is a block diagram showing a conventional BIST test-easy integrated circuit.

[Explanation of symbols]

 10, 30, 50 Test circuit 11, 31 Test pattern generator 12, 32 Test output compressor 51, 52 Pseudo random pattern generator 53 Multi-input output compressor 54 One-input output compressor 20, 40 D flip-flop ( DF / F) 21, 43 Exclusive OR gate 22, 33, 41, 42 Multiplexer CMUX, C31, C41, C42 Control signal Sin Scan input terminal Sout Scan output terminal CLK Clock signal φR Reset signal DINj Normal data input DOUTj output DOUTj-1 Previous F / F output

Claims (2)

[Claims] 1. In a scan-designed integrated circuit,
An integrated circuit comprising: a test pattern generator for supplying a test pattern to a primitive input and a scan input of a circuit under test; and a test output compressor having the primitive output and scan output of the circuit under test as inputs. . 2. The integrated circuit according to claim 1, wherein the scan flip-flop has an exclusive logic of at least data obtained from a normal operation of the integrated circuit and an output of the scan flip-flop in a preceding stage of the flip-flop. An integrated circuit characterized by having a sum as an input.