JPH0620179B2 - Signal processing circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter, and more particularly to a pulse width that determines the integration time of an integral D / A converter suitable for linearity and low power consumption. The present invention relates to a signal processing circuit such as a generation circuit.

[Background of the Invention]

Conventional integral type 16 used in digital signal reproducing devices, etc.
As a bit DA converter, JP-A-57-99821
As described in JP, a current of 2 ⁸ pairs of two constant current sources weighted to 1, a pulse width conversion unit, corresponding to the data set at the higher 8-bit low-order 8 bits of the counter, respectively The capacity of the integrator is charged only for time, and an analog output is obtained. The clock frequency f necessary for the counter is, for example, a sampling period of 20 μsec (50 KHZ), the conversion time is T = 10 μsec, and the number of bits is N = 8.
Then, Therefore, it is possible to realize a DA converter as a monolithic IC. If the input data is divided into three or more, the clock frequency required for the counter can be further reduced.

However, a bipolar process is suitable for realizing an integrator and a constant current source that form a DA converter, but assuming a monolithic IC, a counter requires a power consumption of I ² L, ECL, etc. There is no choice but to use a large logic element.

In addition, since the current of the upper current source is 256 times that of the lower current source, if the signal for controlling the charging period is slightly deviated due to switching jitter, an error occurs in the output. If the clock frequency is 25MHz, the allowable jitter value is Is.

Particularly in the case of IC, the linearity of the analog output is deteriorated by the jitter of the counter clock.

FIG. 9 shows an example of the relationship between clock jitter and S / N. When the clock is FM-modulated to generate jitter in a simulated manner, the S / N ratio of the DA converter is -6d shown at 33 in the same figure.
It can be seen that the curve becomes a β / oct curve and the S / N deteriorates due to clock jitter.

[Object of the Invention]

An object of the present invention is to solve the above-mentioned drawbacks of the prior art and to provide a low power consumption signal processing circuit using a D / A converter having good linearity.

[Outline of Invention]

To this end, it provides an input to a DA converter. At least an error detection and correction circuit and an error correction circuit are required, and these circuits can be realized by CMOS, which consumes less power than ECL and I ² L. Furthermore, the switching jitter of the pulse width generation circuit causes the power supply of the counter. Paying attention to two factors that cause the fluctuation of the line that supplies power, the pulse width generation circuit is integrated on the same semiconductor substrate as the error detection / correction circuit and the error correction circuit, and the error detection / correction circuit and the error correction circuit are further integrated. By separating the wiring that supplies power to the circuit and the wiring that supplies power to the pulse width generation circuit, a current switch control signal that reduces power consumption and has no jitter is obtained, and analog output with good linearity is obtained. Is to get.

Example of Invention

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a signal processing circuit according to the present invention, in which 9 is a timing control circuit and 10 is a timing control circuit.
Counter for loading and counting the upper data of the input data, 11 is a counter for loading and counting the lower data of the input data, 12 and 13 are RS-F / F,
Reference numeral 14 is a pulse width generating circuit IC by the CNOS process, which is composed of these timing control circuit 9, counters 10, 11 and RS-F / F 12, 13, 18, 19 are analog switches, and 20, 21 are constant switches. In the current source, 20A is an IC by a bipolar process consisting of these switches 18, 19 and current sources 20, 21, 22 is an analog switch, 23 is a capacitance, 24 is an operational amplifier, and 25 is an output terminal. is there.

In the circuit operation of FIG. 1, the input 16-bit data is divided into upper 8 bits and lower 8 bits, which are loaded into counters 10 and 11, respectively, and RS-F / F 12 and 13 are set. The high-order counter 10 and the low-order counter 11 perform a counting operation after being loaded, and when the predetermined value is reached, the RS-F / F is reset and a pulse signal having a time width proportional to the size of the input data. Are obtained in 12a and 12b. The switches 18 and 19 are controlled by the pulse signals 12a and 12b, and the constant current source 2 weights the current value 2 ⁸ to 1
A current is supplied to the capacitor 13 by 0 and 21. Immediately before supplying the current to the capacitor 13, the switch 22 is closed and the charge accumulated in the capacitor 13 is discharged to perform the integration operation.
An analog signal corresponding to the input data is obtained at 25.

Next, an embodiment of the present invention will be described as a compact disc (hereinafter referred to as CD
A player will be described as an example with reference to the drawings. For digital signals by CD format,
"Introduction to CD Players" (Published by Corona Publishing Co., July 20, 1983)
As discussed on pages 129 to 136 of the book entitled "Analog Signals", the data sampled at a sampling frequency of 44.1KHz is quantized with 16 bits, and then interleaved, error detection and correction code added, EFM Processing such as modulation is performed.

FIG. 2 is a block diagram showing an embodiment of a signal processing circuit used in the CD player according to the present invention, in which 1 is a disk, 2 is a laser pickup, 3 is a preamplifier, 8 is a demodulation circuit 4, and error detection is performed. A signal processing circuit including a correction circuit 5, an error correction circuit 6, and a first timing control circuit 7, 14 is a second timing control circuit 9, a lower counter 11 of the upper counters 10 and 11, R-SF / F 12,1
Pulse width generation circuit consisting of 3, 15 is a semiconductor substrate, 16a, 16b
Is a first power supply means, 17a, 17b is a second power supply means, 18, 19 are switches, 20, 21 are constant current sources, 22 are switches, 23 is a capacitance, 24 is an operational amplifier, 25 is an output terminal Is.

In the same figure, a laser pickup 2 from a disc 1
The signal 2a read by is converted into a digital signal 3a by the preamplifier 3 and input to the demodulation circuit 4. The demodulation circuit 4 outputs the signal 4a, which has been subjected to EFM modulation and interleave modulation of the digital signal 3a, to the error detection and correction circuit 5. The error detection / correction circuit 5 detects and corrects an error in the signal 4a. The error correction circuit 6 receives the output 5a of the error detection / correction circuit 5 as input, corrects the data that has no error or the data in which the error has been corrected, and corrects the data that cannot be corrected. The data 6a is output. The 16-bit data 6a obtained by the error correction circuit is used as the upper 8-bit and the lower 8-bit data.
Divide and load each into upper counter 10 and lower counter 11, and set R-SF / F12,13. The upper counter 10 and the lower counter 11 perform a counting operation after being loaded, and when they reach a predetermined value, R-
Reset the SF / F, the pulse signal 12a having a magnitude proportional to the time width of the data obtained by dividing the error correction circuit output data, to obtain 12b, closing the switches 18 and 19, the current value 2 ^8: 1 Current is supplied to the capacitor 13 by the weighted constant current sources 20 and 21. Just before the current is supplied to the capacitor 13, the switch 22
Is closed and the charge accumulated in the capacitor 13 is discharged. By doing so, an analog signal is obtained at the output terminal 25 of the integrator 24. The first timing control circuit controls the timings of the demodulation circuit 4, the error detection / correction circuit 5, the error correction circuit 6, and the second timing control circuit 9, and the second timing control circuit 9 controls the first timing. Upon receiving the data confirmation signal 7b from the control circuit 7, the upper counter 10, the lower counter 11, and RS
It controls the timing of the F / F 12, 13 and the switch 22.

Here, the signal processing circuit 8 and the pulse width generation circuit 14 are integrated on the same semiconductor substrate 15, and the first power supply wirings 16a and 16b provide the signal processing circuit 8 with a second power supply wiring. Power is supplied to the pulse width generation circuit 14 by 17a and 17b, respectively.

Therefore, when the signal processing circuit 8 operates, the mutual interference received by the pulse width generation circuit 14 is removed, and the switches 18 and 19 are removed.
It is possible to reduce the switching jitter of the pulse signals 12a and 13a for controlling the pulse width, and obtain an analog signal with good linearity. Further, if the signal processing circuit 8 and the pulse width generation circuit 14 are realized by CMOS, the power consumption can be reduced.

FIG. 3 (a) is an embodiment in which the signal processing circuit 8 and the pulse width generating circuit 14 of FIG. 1 are arranged on the semiconductor substrate 5, and the components with the same numbers as in FIG. 2 shows the same components as in FIG. The signal processing circuit 8 integrated on the semiconductor substrate 15 and the pulse width generating circuit 14 are the first power supply wiring.
16a and 16b and the second power supply sources 17a and 17b are independently wired to reduce the common impedance of the respective power supplies and to output 9a and 12 of the pulse width generation circuit 14.
The wirings a and 13a are arranged in the middle of the second power supply wirings 17a and 17b to eliminate the influence of the operation of the signal processing circuit 8. Even if the first and second power supply wirings are not necessarily provided to the pins of the integrated circuit independently, it is still effective to reduce the common impedance as shown in FIG.

FIG. 4 shows an embodiment of another CD player according to the present invention. The components having the same numbers as those in FIG. 2 show the same components as those in FIG. FIG. 32 shows 26 third timing control circuit, 27 ROM, 28 RAM,
A digital filter circuit including 29 multiplication circuits, 30 cumulative addition circuits, and 31 latches. The 16-bit data output 6a of the signal processing circuit 8 is written in the RAM 28,
The data 28a sequentially read from 28 and the coefficient data 27a read from the ROM 27 are multiplied by the multiplication circuit 29a to obtain the multiplication result 29a. The cumulative addition circuit 30 adds the output 30a and the multiplication result 29a of the multiplication circuit 29.
Just before performing the cumulative addition, if the output 30a of the cumulative addition circuit 30 is held in the latch 31 and the cumulative addition circuit 30 is reset, the output of the latch 31 is a 16-bit filter output.
31a is obtained. Similarly to FIG. 2 below, the pulse width generation circuit 14 outputs pulses 12a and 13a having a time width proportional to the size of data obtained by dividing the filter output 31a into upper 8 bits and lower 8 bits, and outputs the output terminals. Get an analog signal to 25. The third timing control circuit 26 receives the data confirmation signal 7b as an input, RAM 28, multiplication circuit 29, R
While controlling the OM27, the cumulative addition circuit 30, and the latch 31,
The filter output confirmation signal 26a is output to the pulse width generation circuit 14.

Here, digital filter circuit 32 and pulse width generation circuit
14 are integrated on the same semiconductor substrate 15, and the digital filter circuit 32 is formed by the first power supply wirings 16a and 16b.
Then, power is supplied to the pulse width generation circuit 14 by the second power supply wirings 17a and 17b, respectively.

FIG. 5 shows another embodiment according to the present invention,
The components having the same numbers as those in FIG. 4 and FIG. 4 indicate the same components. In this example, the signal processing circuit 8, the digital filter circuit 32, and the pulse width generation circuit 14 are integrated on the same semiconductor substrate, and the signal processing circuit 8 and the digital filter circuit 32 are connected to each other by the first power supply wirings 16a and 16b. Power is supplied to the pulse width generation circuit 14 by the second power supply wirings 17a and 17b, respectively.

Therefore, the signal processing circuit 8 and the digital filter circuit 32
By the operation of and, the mutual interference received by the pulse width conversion circuit 14 can be removed, the switching jitter of the pulse signals 12a, 13a for controlling the switches 18, 19 can be reduced, and an analog signal with good linearity can be obtained. . Further, if the signal processing circuit 8, the digital filter circuit 32, and the pulse width conversion circuit 14 are realized by CMOS, the power consumption can be reduced.

In each of the embodiments shown in FIGS. 1, 2, 4, and 5, the data is divided into two, that is, the upper 8 bits and the lower 8 bits, but this is divided into 3 or more, for example, 16 bits. Similar effects can be obtained by dividing the data into 5 bits, 5 bits, and 6 bits from the lower side. Then the number of the constant current source becomes three, the ratio of the current values, from the lower side a pair 2 ⁵
It should be 2 to ¹⁰ .

The audio performance of the embodiment of the present invention shown in FIGS. 2, 4 and 5 is further improved. An embodiment of the pulse width generating circuit is shown in FIG. FIG. 6 is a block diagram of a pulse width generating circuit of the present invention, and FIG. 7 shows operation waveforms of each part of FIG.

In FIG. 6, 40 is a 16-stage shift register, 40CK is a clock input terminal for performing pulse width conversion, 40D is a data confirmation signal input terminal, 41 and 42 are inverter circuits, 43 and 44 are AND circuits, 45 is an OR circuit, 46 and 47 are load counters, 4
6D and 47D are 16-bit data input terminals, 48 and 49 are AND circuits, 50 and 51 are flip-flop circuits, and 52 to 55
Is a NOR circuit, and 56 and 57 are buffer circuits. Also, the seventh
The symbols on the left side of the operation waveforms of the respective parts in the figure correspond to the symbols of FIG. 6, and show the signal waveforms of the symbols of FIG.

The operation of FIG. 6 will be described using the operation waveform of FIG.

The basic clock input terminal 40CK for pulse width conversion is
From equation (1), a clock of about 25MHz is added. The data confirmation signal and the data are 40C as shown in FIG. 40D, 46D, 47D.
Add to each pin in synchronization with the falling edge of K.
The shift register 40 shifts the data confirmation signal by the clock 40CK, and the first stage, the second stage,
For the 15th and 16th stage outputs 40Q1, 40Q2, 40Q15, 40Q16,
The timing shown in FIG. 7 is output. Also, these signals are decoded by the inverter circuits 41, 42 and the circuits 43, 44 and delayed from the falling edge of 40D at which the data is fixed as shown in FIG. 7 to generate a pulse. This pulse
The pulse widths of 43C and 45C are determined by the number of stages of the shift register 40. The output 43C of the AND circuit 43 is supplied as a pulse for loading the data of the counters 46 and 47, and also the reset pulse of the flip-flop circuits 50 and 51 and the RS flip-flop and NOR circuit composed of the NOR circuits 52 and 53. Five
It is supplied to an RS flip-flop composed of 4,55.
Also, the output of the AND circuit 44 is clocked by the OR circuit 45 and 40CK
, And its output 45C has the waveform shown in FIG.

The data 46D and 47D, 8 bits each, are loaded into the counters 46 and 47 by the output 43C of the AND circuit 43, and the OR circuit
45 Output 45 Counts with the clock of 45C. The AND circuit 48 detects that all the outputs of the counter 46 have become 1 level, the flip-flop 50 removes the hazard, and a pulse is applied to the NOR circuit 53. The NOR circuits 52 and 53 are R
Since the S flip-flop is configured, the output pulse of the AND circuit 43 changes the output of the flip-flop 50.
The pulse width up to the pulse of 50Q is obtained at the output 52C of the NOR circuit 52. Therefore, depending on the data added to 46D, the counter 46
Is controlled until the output becomes all 1, and the output terminal 56C
Therefore, the pulse width generation output can be obtained. Output terminal
Also for 57C, the pulse width controlled by the data 47D is obtained by the same operation as 56C. Where the data 46D
However, when all 1's data is added, the output 43C of the AND circuit 43 which is the load pulse of the counter 46 as shown in FIG.
Becomes 1 level, the output 48C of the AND circuit 48 which decodes the output of the counter 46 also becomes 1 level. However, since the clock 45C of the counter 46 and the flip-flop 50 is not changed, no pulse is added to the NOR circuit 53,
The output 52C of the NOR circuit 52 holds 1 level. This output 52C holds 1 level until the clock 45C next rises, and becomes 0 level. Therefore, the minimum pulse width of the output 52C is the clock 45C from the rising point of the output 43C pulse.
Can be specified up to the first rising point of. In this embodiment, the minimum pulse width is 16 clock pulses with the clock 40CK. With this, when switching the constant current source with the output 56C of the buffer 56, the load capacity of the buffer 56
As shown in FIG. 7C, the constant current source maintaining the pulse width can be switched even when the waveform changes exponentially. FIG. 8 shows changes in the pulse width for switching the constant current source when the minimum pulse width of the pulse width conversion output 56C is defined by the waveform of the buffer 56 and when it is not specified. FIG. 8 (a) defines the minimum pulse width, and FIG. 8 (b) does not define the minimum pulse width, and the fall is performed before the pulse rises completely. Corresponding to the data in FIG. 8, from the minimum pulse width to the clock in FIG.
The pulse width changes at a period t of 40CK. In FIG. 8 (a), even if the waveform changes exponentially, since the pulse starts to fall after the pulse completely rises, the change width t of the pulse at the threshold bell V _TH is also changed. Is maintained. On the other hand, in the case of (b), since the falling operation is performed from the middle of the rising edge of the pulse, the change width of the pulse shifts from t to t ₁ , t ₂ , t ₃ as shown in the figure. As described above, according to the embodiment shown in FIG. 6, by defining the minimum pulse width, it is possible to obtain a pulse width generating circuit having excellent linearity.

〔The invention's effect〕

As described above, according to the present invention, even if the pulse width conversion unit, the error detection / correction unit, and the error correction unit are integrated on the same semiconductor substrate, the error detection / correction unit and the error correction unit, and the pulse Since mutual interference with the width generating means can be eliminated and switching jitter for controlling a plurality of constant current sources can be reduced, a D / A converter having good linearity can be realized with low power consumption, and an excellent function. A digital signal reproducing device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a signal processing circuit according to the present invention, and FIG. 2 is a C- using the signal processing circuit of FIG.
3 is a block diagram of a D player, FIGS. 3 (a) and 3 (b) are layout diagrams in which the embodiment of FIG. 2 is integrated on a semiconductor substrate, and FIG. 4 is a block diagram showing another embodiment of the present invention. FIG. 5 is a diagram showing yet another embodiment according to the present invention, FIG. 6 is a circuit diagram of an embodiment of a pulse width generating circuit, and FIGS. 7 and 8 are diagrams showing operation waveforms of FIG. 6 and FIG. The figure shows the relationship between clock jitter and S / N. 5 ... error detection / correction circuit, 6 ... error correction circuit, 14 ... pulse width generation circuit, 15 ... semiconductor substrate, 16a, 16b ... first power supply means, 17a, 17b ... second power supply Supply means, 20, 21 ... constant current source, 23 ... operational amplifier circuit, 29 ... multiplication circuit, 30 ... cumulative addition circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takao Arai 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Home Appliance Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-52-116124 (JP, A) Sho 62-112222 (JP, U)

Claims (1)

[Claims] 1. A first circuit constituting a pulse width generating means for determining an integration time corresponding to digital data, a current switch circuit for turning on / off a current of a current source at least according to the integration time, and a current source circuit. And a second circuit consisting of an integrated circuit on a separate chip, and the first circuit is a complementary type MO
In the integration type D / A converter configured by an S FET transistor, the second circuit configured by a bipolar process, and performing a D / A conversion by integrating a constant current in a capacitance with time, the pulse width generating means is A pulse width generating circuit for generating a pulse having a time width proportional to the size of data, and a pulse width adding circuit for giving a pulse width of a constant time, the minimum pulse width of the pulse width generating circuit being a pulse of the constant time. A signal processing circuit characterized by being set to a width or more.